[people/ms/u-boot.git] / include / configs / sh7757lcr.h

/*
 * Configuation settings for the sh7757lcr board
 *
 * Copyright (C) 2011 Renesas Solutions Corp.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __SH7757LCR_H
#define __SH7757LCR_H

#undef DEBUG
#define CONFIG_CPU_SH7757	1
#define CONFIG_SH7757LCR	1
#define CONFIG_SH7757LCR_DDR_ECC	1

#define CONFIG_SYS_TEXT_BASE	0x8ef80000
#define CONFIG_SYS_LDSCRIPT	"board/renesas/sh7757lcr/u-boot.lds"

#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_MD5SUM
#define CONFIG_MD5
#define CONFIG_DOS_PARTITION
#define CONFIG_MAC_PARTITION

#define CONFIG_BAUDRATE		115200
#define CONFIG_BOOTARGS		"console=ttySC2,115200 root=/dev/nfs ip=dhcp"

#define CONFIG_VERSION_VARIABLE
#undef	CONFIG_SHOW_BOOT_PROGRESS

/* MEMORY */
#define SH7757LCR_SDRAM_BASE		(0x80000000)
#define SH7757LCR_SDRAM_SIZE		(240 * 1024 * 1024)
#define SH7757LCR_SDRAM_ECC_SETTING	0x0f000000	/* 240MByte */
#define SH7757LCR_SDRAM_DVC_SIZE	(16 * 1024 * 1024)

#define CONFIG_SYS_LONGHELP
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_PBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_BARGSIZE		512
#define CONFIG_SYS_BAUDRATE_TABLE	{ 115200 }

/* SCIF */
#define CONFIG_SCIF_CONSOLE	1
#define CONFIG_CONS_SCIF2	1
#undef	CONFIG_SYS_CONSOLE_INFO_QUIET
#undef	CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
#undef	CONFIG_SYS_CONSOLE_ENV_OVERWRITE

#define CONFIG_SYS_MEMTEST_START	(SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + \
					 224 * 1024 * 1024)
#undef	CONFIG_SYS_ALT_MEMTEST
#undef	CONFIG_SYS_MEMTEST_SCRATCH
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE

#define CONFIG_SYS_SDRAM_BASE		(SH7757LCR_SDRAM_BASE)
#define CONFIG_SYS_SDRAM_SIZE		(SH7757LCR_SDRAM_SIZE)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + \
					 (128 + 16) * 1024 * 1024)

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)
#define CONFIG_SYS_MALLOC_LEN		(4 * 1024 * 1024)
#define CONFIG_SYS_BOOTMAPSZ		(8 * 1024 * 1024)

/* FLASH */
#define CONFIG_SYS_NO_FLASH

/* Ether */
#define CONFIG_SH_ETHER			1
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	1
#define CONFIG_SH_ETHER_CACHE_WRITEBACK	1
#define CONFIG_PHYLIB
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII

#define SH7757LCR_ETHERNET_MAC_BASE_SPI	0x000b0000
#define SH7757LCR_SPI_SECTOR_SIZE	(64 * 1024)
#define SH7757LCR_ETHERNET_MAC_BASE	SH7757LCR_ETHERNET_MAC_BASE_SPI
#define SH7757LCR_ETHERNET_MAC_SIZE	17
#define SH7757LCR_ETHERNET_NUM_CH	2
#define CONFIG_BOARD_LATE_INIT

/* Gigabit Ether */
#define SH7757LCR_GIGA_ETHERNET_NUM_CH	2

/* SPI */
#define CONFIG_SH_SPI			1
#define CONFIG_SH_SPI_BASE		0xfe002000

/* MMCIF */
#define CONFIG_MMC			1
#define CONFIG_GENERIC_MMC		1
#define CONFIG_SH_MMCIF			1
#define CONFIG_SH_MMCIF_ADDR		0xffcb0000
#define CONFIG_SH_MMCIF_CLK		48000000

/* SH7757 board */
#define SH7757LCR_SDRAM_PHYS_TOP	0x40000000
#define SH7757LCR_GRA_OFFSET		0x1f000000
#define SH7757LCR_PCIEBRG_ADDR_B0	0x000a0000
#define SH7757LCR_PCIEBRG_SIZE_B0	(64 * 1024)
#define SH7757LCR_PCIEBRG_ADDR		0x00090000
#define SH7757LCR_PCIEBRG_SIZE		(96 * 1024)

/* ENV setting */
#define CONFIG_ENV_IS_EMBEDDED
#define CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_SECT_SIZE	(64 * 1024)
#define CONFIG_ENV_ADDR		(0x00080000)
#define CONFIG_ENV_OFFSET	(CONFIG_ENV_ADDR)
#define CONFIG_ENV_OVERWRITE	1
#define CONFIG_ENV_SIZE		(CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SECT_SIZE)
#define CONFIG_EXTRA_ENV_SETTINGS				\
		"netboot=bootp; bootm\0"

/* Board Clock */
#define CONFIG_SYS_CLK_FREQ	48000000
#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
#define CONFIG_SYS_TMU_CLK_DIV	4
#endif	/* __SH7757LCR_H */
Commit	Line	Data
8e9c897b YS	1	/*
	2	* Configuation settings for the sh7757lcr board
	3	*
	4	* Copyright (C) 2011 Renesas Solutions Corp.
	5	*
1a459660	6	* SPDX-License-Identifier: GPL-2.0+
8e9c897b YS	7	*/
	8
	9	#ifndef __SH7757LCR_H
	10	#define __SH7757LCR_H
	11
	12	#undef DEBUG
8e9c897b YS	13	#define CONFIG_CPU_SH7757 1
8e9c897b YS	14	#define CONFIG_SH7757LCR 1
3ed81645	15	#define CONFIG_SH7757LCR_DDR_ECC 1
8e9c897b YS	16
	17	#define CONFIG_SYS_TEXT_BASE 0x8ef80000
	18	#define CONFIG_SYS_LDSCRIPT "board/renesas/sh7757lcr/u-boot.lds"
	19
8e9c897b	20	#define CONFIG_CMD_SDRAM
8e9c897b YS	21	#define CONFIG_CMD_MD5SUM
8e9c897b YS	22	#define CONFIG_MD5
566f63d5 YS	23	#define CONFIG_DOS_PARTITION
566f63d5 YS	24	#define CONFIG_MAC_PARTITION
8e9c897b YS	25
8e9c897b YS	26	#define CONFIG_BAUDRATE 115200
8e9c897b YS	27	#define CONFIG_BOOTARGS "console=ttySC2,115200 root=/dev/nfs ip=dhcp"
	28
	29	#define CONFIG_VERSION_VARIABLE
	30	#undef CONFIG_SHOW_BOOT_PROGRESS
	31
	32	/* MEMORY */
	33	#define SH7757LCR_SDRAM_BASE (0x80000000)
	34	#define SH7757LCR_SDRAM_SIZE (240 * 1024 * 1024)
	35	#define SH7757LCR_SDRAM_ECC_SETTING 0x0f000000 /* 240MByte */
	36	#define SH7757LCR_SDRAM_DVC_SIZE (16 * 1024 * 1024)
	37
	38	#define CONFIG_SYS_LONGHELP
8e9c897b YS	39	#define CONFIG_SYS_CBSIZE 256
	40	#define CONFIG_SYS_PBSIZE 256
	41	#define CONFIG_SYS_MAXARGS 16
	42	#define CONFIG_SYS_BARGSIZE 512
	43	#define CONFIG_SYS_BAUDRATE_TABLE { 115200 }
	44
	45	/* SCIF */
	46	#define CONFIG_SCIF_CONSOLE 1
	47	#define CONFIG_CONS_SCIF2 1
	48	#undef CONFIG_SYS_CONSOLE_INFO_QUIET
	49	#undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE
	50	#undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE
	51
	52	#define CONFIG_SYS_MEMTEST_START (SH7757LCR_SDRAM_BASE)
	53	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \
	54	224 * 1024 * 1024)
	55	#undef CONFIG_SYS_ALT_MEMTEST
	56	#undef CONFIG_SYS_MEMTEST_SCRATCH
	57	#undef CONFIG_SYS_LOADS_BAUD_CHANGE
	58
	59	#define CONFIG_SYS_SDRAM_BASE (SH7757LCR_SDRAM_BASE)
	60	#define CONFIG_SYS_SDRAM_SIZE (SH7757LCR_SDRAM_SIZE)
	61	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + \
	62	(128 + 16) * 1024 * 1024)
	63
	64	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	65	#define CONFIG_SYS_MONITOR_LEN (256 * 1024)
	66	#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024)
	67	#define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024)
	68
	69	/* FLASH */
	70	#define CONFIG_SYS_NO_FLASH
	71
	72	/* Ether */
8e9c897b YS	73	#define CONFIG_SH_ETHER 1
	74	#define CONFIG_SH_ETHER_USE_PORT 0
	75	#define CONFIG_SH_ETHER_PHY_ADDR 1
	76	#define CONFIG_SH_ETHER_CACHE_WRITEBACK 1
0c2a37a5 YS	77	#define CONFIG_PHYLIB
	78	#define CONFIG_BITBANGMII
	79	#define CONFIG_BITBANGMII_MULTI
a80a6619	80	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_MII
8e9c897b YS	81
	82	#define SH7757LCR_ETHERNET_MAC_BASE_SPI 0x000b0000
	83	#define SH7757LCR_SPI_SECTOR_SIZE (64 * 1024)
	84	#define SH7757LCR_ETHERNET_MAC_BASE SH7757LCR_ETHERNET_MAC_BASE_SPI
	85	#define SH7757LCR_ETHERNET_MAC_SIZE 17
	86	#define SH7757LCR_ETHERNET_NUM_CH 2
9660e442	87	#define CONFIG_BOARD_LATE_INIT
8e9c897b YS	88
	89	/* Gigabit Ether */
	90	#define SH7757LCR_GIGA_ETHERNET_NUM_CH 2
	91
	92	/* SPI */
	93	#define CONFIG_SH_SPI 1
	94	#define CONFIG_SH_SPI_BASE 0xfe002000
8e9c897b	95
566f63d5 YS	96	/* MMCIF */
	97	#define CONFIG_MMC 1
	98	#define CONFIG_GENERIC_MMC 1
	99	#define CONFIG_SH_MMCIF 1
	100	#define CONFIG_SH_MMCIF_ADDR 0xffcb0000
	101	#define CONFIG_SH_MMCIF_CLK 48000000
	102
8e9c897b YS	103	/* SH7757 board */
	104	#define SH7757LCR_SDRAM_PHYS_TOP 0x40000000
	105	#define SH7757LCR_GRA_OFFSET 0x1f000000
	106	#define SH7757LCR_PCIEBRG_ADDR_B0 0x000a0000
	107	#define SH7757LCR_PCIEBRG_SIZE_B0 (64 * 1024)
	108	#define SH7757LCR_PCIEBRG_ADDR 0x00090000
	109	#define SH7757LCR_PCIEBRG_SIZE (96 * 1024)
	110
	111	/* ENV setting */
	112	#define CONFIG_ENV_IS_EMBEDDED
	113	#define CONFIG_ENV_IS_IN_SPI_FLASH
	114	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	115	#define CONFIG_ENV_ADDR (0x00080000)
	116	#define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR)
	117	#define CONFIG_ENV_OVERWRITE 1
	118	#define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE)
	119	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE)
	120	#define CONFIG_EXTRA_ENV_SETTINGS \
	121	"netboot=bootp; bootm\0"
	122
	123	/* Board Clock */
	124	#define CONFIG_SYS_CLK_FREQ 48000000
684a501e NI	125	#define CONFIG_SH_TMU_CLK_FREQ CONFIG_SYS_CLK_FREQ
684a501e NI	126	#define CONFIG_SH_SCIF_CLK_FREQ CONFIG_SYS_CLK_FREQ
8e9c897b	127	#define CONFIG_SYS_TMU_CLK_DIV 4
8e9c897b	128	#endif /* __SH7757LCR_H */