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0d53a47d NI |
1 | /* |
2 | * Configuation settings for the Renesas Technology R0P7785LC0011RL board | |
3 | * | |
4 | * Copyright (C) 2008 Yoshihiro Shimoda <shimoda.yoshihiro@renesas.com> | |
5 | * | |
6 | * See file CREDITS for list of people who contributed to this | |
7 | * project. | |
8 | * | |
9 | * This program is free software; you can redistribute it and/or | |
10 | * modify it under the terms of the GNU General Public License as | |
11 | * published by the Free Software Foundation; either version 2 of | |
12 | * the License, or (at your option) any later version. | |
13 | * | |
14 | * This program is distributed in the hope that it will be useful, | |
15 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
16 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
17 | * GNU General Public License for more details. | |
18 | * | |
19 | * You should have received a copy of the GNU General Public License | |
20 | * along with this program; if not, write to the Free Software | |
21 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
22 | * MA 02111-1307 USA | |
23 | */ | |
24 | ||
25 | #ifndef __SH7785LCR_H | |
26 | #define __SH7785LCR_H | |
27 | ||
28 | #undef DEBUG | |
29 | #define CONFIG_SH 1 | |
30 | #define CONFIG_SH4A 1 | |
31 | #define CONFIG_CPU_SH7785 1 | |
32 | #define CONFIG_SH7785LCR 1 | |
33 | ||
34 | #define CONFIG_CMD_FLASH | |
35 | #define CONFIG_CMD_MEMORY | |
36 | #define CONFIG_CMD_PCI | |
37 | #define CONFIG_CMD_NET | |
38 | #define CONFIG_CMD_PING | |
39 | #define CONFIG_CMD_NFS | |
0d53a47d NI |
40 | #define CONFIG_CMD_SDRAM |
41 | #define CONFIG_CMD_RUN | |
bdab39d3 | 42 | #define CONFIG_CMD_SAVEENV |
9375253e | 43 | #define CONFIG_CMD_SH_ZIMAGEBOOT |
0d53a47d NI |
44 | |
45 | #define CONFIG_CMD_USB | |
46 | #define CONFIG_USB_STORAGE | |
47 | #define CONFIG_CMD_EXT2 | |
48 | #define CONFIG_CMD_FAT | |
49 | #define CONFIG_DOS_PARTITION | |
50 | #define CONFIG_MAC_PARTITION | |
51 | ||
52 | #define CONFIG_BAUDRATE 115200 | |
53 | #define CONFIG_BOOTDELAY 3 | |
54 | #define CONFIG_BOOTARGS "console=ttySC1,115200 root=/dev/nfs ip=dhcp" | |
55 | ||
56 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
57 | "bootdevice=0:1\0" \ | |
58 | "usbload=usb reset;usbboot;usb stop;bootm\0" | |
59 | ||
60 | #define CONFIG_VERSION_VARIABLE | |
61 | #undef CONFIG_SHOW_BOOT_PROGRESS | |
62 | ||
63 | /* MEMORY */ | |
ada93182 | 64 | #if defined(CONFIG_SH_32BIT) |
59272c6b | 65 | #define CONFIG_SYS_TEXT_BASE 0x8FF80000 |
915d6b7d NI |
66 | /* 0x40000000 - 0x47FFFFFF does not use */ |
67 | #define CONFIG_SH_SDRAM_OFFSET (0x8000000) | |
68 | #define SH7785LCR_SDRAM_PHYS_BASE (0x40000000 + CONFIG_SH_SDRAM_OFFSET) | |
69 | #define SH7785LCR_SDRAM_BASE (0x80000000 + CONFIG_SH_SDRAM_OFFSET) | |
ada93182 YS |
70 | #define SH7785LCR_SDRAM_SIZE (384 * 1024 * 1024) |
71 | #define SH7785LCR_FLASH_BASE_1 (0xa0000000) | |
72 | #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) | |
73 | #define SH7785LCR_USB_BASE (0xa6000000) | |
74 | #else | |
59272c6b | 75 | #define CONFIG_SYS_TEXT_BASE 0x0FF80000 |
0d53a47d NI |
76 | #define SH7785LCR_SDRAM_BASE (0x08000000) |
77 | #define SH7785LCR_SDRAM_SIZE (128 * 1024 * 1024) | |
78 | #define SH7785LCR_FLASH_BASE_1 (0xa0000000) | |
79 | #define SH7785LCR_FLASH_BANK_SIZE (64 * 1024 * 1024) | |
80 | #define SH7785LCR_USB_BASE (0xb4000000) | |
ada93182 | 81 | #endif |
0d53a47d | 82 | |
6d0f6bcf JCPV |
83 | #define CONFIG_SYS_LONGHELP |
84 | #define CONFIG_SYS_PROMPT "=> " | |
85 | #define CONFIG_SYS_CBSIZE 256 | |
86 | #define CONFIG_SYS_PBSIZE 256 | |
87 | #define CONFIG_SYS_MAXARGS 16 | |
88 | #define CONFIG_SYS_BARGSIZE 512 | |
89 | #define CONFIG_SYS_BAUDRATE_TABLE { 115200 } | |
0d53a47d NI |
90 | |
91 | /* SCIF */ | |
1c98172e | 92 | #define CONFIG_SCIF_CONSOLE 1 |
0d53a47d NI |
93 | #define CONFIG_CONS_SCIF1 1 |
94 | #define CONFIG_SCIF_EXT_CLOCK 1 | |
6d0f6bcf JCPV |
95 | #undef CONFIG_SYS_CONSOLE_INFO_QUIET |
96 | #undef CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE | |
97 | #undef CONFIG_SYS_CONSOLE_ENV_OVERWRITE | |
0d53a47d NI |
98 | |
99 | ||
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_MEMTEST_START (SH7785LCR_SDRAM_BASE) |
101 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + \ | |
0d53a47d NI |
102 | (SH7785LCR_SDRAM_SIZE) - \ |
103 | 4 * 1024 * 1024) | |
6d0f6bcf JCPV |
104 | #undef CONFIG_SYS_ALT_MEMTEST |
105 | #undef CONFIG_SYS_MEMTEST_SCRATCH | |
106 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE | |
0d53a47d | 107 | |
6d0f6bcf JCPV |
108 | #define CONFIG_SYS_SDRAM_BASE (SH7785LCR_SDRAM_BASE) |
109 | #define CONFIG_SYS_SDRAM_SIZE (SH7785LCR_SDRAM_SIZE) | |
110 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 16 * 1024 * 1024) | |
0d53a47d | 111 | |
6d0f6bcf JCPV |
112 | #define CONFIG_SYS_MONITOR_BASE (SH7785LCR_FLASH_BASE_1) |
113 | #define CONFIG_SYS_MONITOR_LEN (512 * 1024) | |
114 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) | |
6d0f6bcf | 115 | #define CONFIG_SYS_BOOTMAPSZ (8 * 1024 * 1024) |
0d53a47d NI |
116 | |
117 | /* FLASH */ | |
1c98172e | 118 | #define CONFIG_FLASH_CFI_DRIVER |
6d0f6bcf JCPV |
119 | #define CONFIG_SYS_FLASH_CFI |
120 | #undef CONFIG_SYS_FLASH_QUIET_TEST | |
121 | #define CONFIG_SYS_FLASH_EMPTY_INFO | |
122 | #define CONFIG_SYS_FLASH_BASE (SH7785LCR_FLASH_BASE_1) | |
123 | #define CONFIG_SYS_MAX_FLASH_SECT 512 | |
124 | ||
125 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 | |
126 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE + \ | |
0d53a47d NI |
127 | (0 * SH7785LCR_FLASH_BANK_SIZE) } |
128 | ||
6d0f6bcf JCPV |
129 | #define CONFIG_SYS_FLASH_ERASE_TOUT (3 * 1000) |
130 | #define CONFIG_SYS_FLASH_WRITE_TOUT (3 * 1000) | |
131 | #define CONFIG_SYS_FLASH_LOCK_TOUT (3 * 1000) | |
132 | #define CONFIG_SYS_FLASH_UNLOCK_TOUT (3 * 1000) | |
0d53a47d | 133 | |
6d0f6bcf JCPV |
134 | #undef CONFIG_SYS_FLASH_PROTECTION |
135 | #undef CONFIG_SYS_DIRECT_FLASH_TFTP | |
0d53a47d NI |
136 | |
137 | /* R8A66597 */ | |
0d53a47d NI |
138 | #define CONFIG_USB_R8A66597_HCD |
139 | #define CONFIG_R8A66597_BASE_ADDR SH7785LCR_USB_BASE | |
140 | #define CONFIG_R8A66597_XTAL 0x0000 /* 12MHz */ | |
141 | #define CONFIG_R8A66597_LDRV 0x8000 /* 3.3V */ | |
142 | #define CONFIG_R8A66597_ENDIAN 0x0000 /* little */ | |
143 | ||
144 | /* PCI Controller */ | |
145 | #define CONFIG_PCI | |
146 | #define CONFIG_SH4_PCI | |
147 | #define CONFIG_SH7780_PCI | |
ada93182 YS |
148 | #if defined(CONFIG_SH_32BIT) |
149 | #define CONFIG_SH7780_PCI_LSR 0x1ff00001 | |
150 | #define CONFIG_SH7780_PCI_LAR 0x5f000000 | |
151 | #define CONFIG_SH7780_PCI_BAR 0x5f000000 | |
152 | #else | |
06b18163 YS |
153 | #define CONFIG_SH7780_PCI_LSR 0x07f00001 |
154 | #define CONFIG_SH7780_PCI_LAR CONFIG_SYS_SDRAM_SIZE | |
155 | #define CONFIG_SH7780_PCI_BAR CONFIG_SYS_SDRAM_SIZE | |
ada93182 | 156 | #endif |
0d53a47d NI |
157 | #define CONFIG_PCI_PNP |
158 | #define CONFIG_PCI_SCAN_SHOW 1 | |
159 | ||
160 | #define CONFIG_PCI_MEM_BUS 0xFD000000 /* Memory space base addr */ | |
161 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
162 | #define CONFIG_PCI_MEM_SIZE 0x01000000 /* Size of Memory window */ | |
163 | ||
164 | #define CONFIG_PCI_IO_BUS 0xFE200000 /* IO space base address */ | |
165 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
166 | #define CONFIG_PCI_IO_SIZE 0x00200000 /* Size of IO window */ | |
167 | ||
ada93182 YS |
168 | #if defined(CONFIG_SH_32BIT) |
169 | #define CONFIG_PCI_SYS_PHYS SH7785LCR_SDRAM_PHYS_BASE | |
170 | #else | |
b3061b40 | 171 | #define CONFIG_PCI_SYS_PHYS CONFIG_SYS_SDRAM_BASE |
ada93182 YS |
172 | #endif |
173 | #define CONFIG_PCI_SYS_BUS CONFIG_SYS_SDRAM_BASE | |
b3061b40 YS |
174 | #define CONFIG_PCI_SYS_SIZE CONFIG_SYS_SDRAM_SIZE |
175 | ||
0d53a47d | 176 | /* Network device (RTL8169) support */ |
0d53a47d NI |
177 | #define CONFIG_RTL8169 |
178 | ||
179 | /* ENV setting */ | |
5a1aceb0 | 180 | #define CONFIG_ENV_IS_IN_FLASH |
0d53a47d | 181 | #define CONFIG_ENV_OVERWRITE 1 |
0e8d1586 JCPV |
182 | #define CONFIG_ENV_SECT_SIZE (256 * 1024) |
183 | #define CONFIG_ENV_SIZE (CONFIG_ENV_SECT_SIZE) | |
6d0f6bcf JCPV |
184 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + CONFIG_SYS_MONITOR_LEN) |
185 | #define CONFIG_ENV_OFFSET (CONFIG_ENV_ADDR - CONFIG_SYS_FLASH_BASE) | |
0e8d1586 | 186 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SECT_SIZE) |
0d53a47d NI |
187 | |
188 | /* Board Clock */ | |
189 | /* The SCIF used external clock. system clock only used timer. */ | |
190 | #define CONFIG_SYS_CLK_FREQ 50000000 | |
be45c632 | 191 | #define CONFIG_SYS_TMU_CLK_DIV 4 |
8dd29c87 | 192 | #define CONFIG_SYS_HZ 1000 |
0d53a47d NI |
193 | |
194 | #endif /* __SH7785LCR_H */ |