[thirdparty/u-boot.git] / include / configs / silk.h

/* SPDX-License-Identifier: GPL-2.0 */
/*
 * include/configs/silk.h
 *     This file is silk board configuration.
 *
 * Copyright (C) 2015 Renesas Electronics Corporation
 * Copyright (C) 2015 Cogent Embedded, Inc.
 */

#ifndef __SILK_H
#define __SILK_H

#include "rcar-gen2-common.h"

#define CONFIG_SYS_INIT_SP_ADDR		0x4f000000
#define STACK_AREA_SIZE			0x00100000
#define LOW_LEVEL_MERAM_STACK \
		(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)

/* MEMORY */
#define RCAR_GEN2_SDRAM_BASE		0x40000000
#define RCAR_GEN2_SDRAM_SIZE		(1024u * 1024 * 1024)
#define RCAR_GEN2_UBOOT_SDRAM_SIZE	(512 * 1024 * 1024)

/* FLASH */
#define CONFIG_SPI_FLASH_QUAD

/* SH Ether */
#define CONFIG_SH_ETHER_USE_PORT	0
#define CONFIG_SH_ETHER_PHY_ADDR	0x1
#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
#define CONFIG_SH_ETHER_CACHE_WRITEBACK
#define CONFIG_SH_ETHER_CACHE_INVALIDATE
#define CONFIG_SH_ETHER_ALIGNE_SIZE	64
#define CONFIG_BITBANGMII
#define CONFIG_BITBANGMII_MULTI

/* Board Clock */
#define RMOBILE_XTAL_CLK	20000000u
#define CONFIG_SYS_CLK_FREQ	RMOBILE_XTAL_CLK
#define CONFIG_SH_TMU_CLK_FREQ	(CONFIG_SYS_CLK_FREQ / 2)

#define CONFIG_SYS_TMU_CLK_DIV	4

#define CONFIG_EXTRA_ENV_SETTINGS	\
	"fdt_high=0xffffffff\0"		\
	"initrd_high=0xffffffff\0"

/* SPL support */
#define CONFIG_SPL_TEXT_BASE		0xe6300000
#define CONFIG_SPL_STACK		0xe6340000
#define CONFIG_SPL_MAX_SIZE		0x4000
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x140000
#ifdef CONFIG_SPL_BUILD
#define CONFIG_CONS_SCIF2
#define CONFIG_SH_SCIF_CLK_FREQ		65000000
#endif

#endif /* __SILK_H */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0 */
3b7f0e10 VB	2	/*
	3	* include/configs/silk.h
	4	* This file is silk board configuration.
	5	*
	6	* Copyright (C) 2015 Renesas Electronics Corporation
	7	* Copyright (C) 2015 Cogent Embedded, Inc.
3b7f0e10 VB	8	*/
	9
	10	#ifndef __SILK_H
	11	#define __SILK_H
	12
3b7f0e10 VB	13	#include "rcar-gen2-common.h"
3b7f0e10 VB	14
f7aa3cd4 MV	15	#define CONFIG_SYS_INIT_SP_ADDR 0x4f000000
f7aa3cd4 MV	16	#define STACK_AREA_SIZE 0x00100000
3b7f0e10 VB	17	#define LOW_LEVEL_MERAM_STACK \
	18	(CONFIG_SYS_INIT_SP_ADDR + STACK_AREA_SIZE - 4)
	19
	20	/* MEMORY */
	21	#define RCAR_GEN2_SDRAM_BASE 0x40000000
	22	#define RCAR_GEN2_SDRAM_SIZE (1024u * 1024 * 1024)
	23	#define RCAR_GEN2_UBOOT_SDRAM_SIZE (512 * 1024 * 1024)
	24
3b7f0e10	25	/* FLASH */
3b7f0e10	26	#define CONFIG_SPI_FLASH_QUAD
3b7f0e10 VB	27
3b7f0e10 VB	28	/* SH Ether */
3b7f0e10 VB	29	#define CONFIG_SH_ETHER_USE_PORT 0
	30	#define CONFIG_SH_ETHER_PHY_ADDR 0x1
	31	#define CONFIG_SH_ETHER_PHY_MODE PHY_INTERFACE_MODE_RMII
	32	#define CONFIG_SH_ETHER_CACHE_WRITEBACK
	33	#define CONFIG_SH_ETHER_CACHE_INVALIDATE
	34	#define CONFIG_SH_ETHER_ALIGNE_SIZE 64
3b7f0e10 VB	35	#define CONFIG_BITBANGMII
	36	#define CONFIG_BITBANGMII_MULTI
	37
	38	/* Board Clock */
	39	#define RMOBILE_XTAL_CLK 20000000u
	40	#define CONFIG_SYS_CLK_FREQ RMOBILE_XTAL_CLK
f7aa3cd4 MV	41	#define CONFIG_SH_TMU_CLK_FREQ (CONFIG_SYS_CLK_FREQ / 2)
	42
	43	#define CONFIG_SYS_TMU_CLK_DIV 4
	44
	45	#define CONFIG_EXTRA_ENV_SETTINGS \
	46	"fdt_high=0xffffffff\0" \
	47	"initrd_high=0xffffffff\0"
	48
	49	/* SPL support */
	50	#define CONFIG_SPL_TEXT_BASE 0xe6300000
	51	#define CONFIG_SPL_STACK 0xe6340000
	52	#define CONFIG_SPL_MAX_SIZE 0x4000
	53	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x140000
	54	#ifdef CONFIG_SPL_BUILD
	55	#define CONFIG_CONS_SCIF2
	56	#define CONFIG_SH_SCIF_CLK_FREQ 65000000
	57	#endif
3b7f0e10 VB	58
3b7f0e10 VB	59	#endif /* __SILK_H */