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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
3b5df50e HS |
2 | /* |
3 | * (C) Copyright 2007-2008 | |
4 | * Stelian Pop <stelian@popies.net> | |
5 | * Lead Tech Design <www.leadtechdesign.com> | |
6 | * | |
7 | * (C) Copyright 2010 | |
8 | * Achim Ehrlich <aehrlich@taskit.de> | |
9 | * taskit GmbH <www.taskit.de> | |
10 | * | |
11 | * (C) Copyright 2012 | |
12 | * Markus Hubig <mhubig@imko.de> | |
13 | * IMKO GmbH <www.imko.de> | |
14 | * | |
15 | * (C) Copyright 2014 | |
16 | * Heiko Schocher <hs@denx.de> | |
17 | * DENX Software Engineering GmbH | |
18 | * | |
19 | * Configuation settings for the smartweb. | |
3b5df50e HS |
20 | */ |
21 | ||
22 | #ifndef __CONFIG_H | |
23 | #define __CONFIG_H | |
24 | ||
25 | /* | |
26 | * SoC must be defined first, before hardware.h is included. | |
27 | * In this case SoC is defined in boards.cfg. | |
28 | */ | |
29 | #include <asm/hardware.h> | |
e8b81eef | 30 | #include <linux/sizes.h> |
3b5df50e HS |
31 | |
32 | /* | |
33 | * Warning: changing CONFIG_SYS_TEXT_BASE requires adapting the initial boot | |
34 | * program. Since the linker has to swallow that define, we must use a pure | |
35 | * hex number here! | |
36 | */ | |
3b5df50e HS |
37 | |
38 | /* ARM asynchronous clock */ | |
39 | #define CONFIG_SYS_AT91_SLOW_CLOCK 32768 /* slow clock xtal */ | |
40 | #define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* 18.432MHz crystal */ | |
41 | ||
42 | /* misc settings */ | |
43 | #define CONFIG_CMDLINE_TAG /* pass commandline to Kernel */ | |
44 | #define CONFIG_SETUP_MEMORY_TAGS /* pass memory defs to kernel */ | |
45 | #define CONFIG_INITRD_TAG /* pass initrd param to kernel */ | |
13ee7890 | 46 | #define CONFIG_SKIP_LOWLEVEL_INIT_ONLY /* U-Boot is loaded by a bootloader */ |
3b5df50e | 47 | |
b96fd825 MM |
48 | /* We set the max number of command args high to avoid HUSH bugs. */ |
49 | #define CONFIG_SYS_MAXARGS 32 | |
50 | ||
3b5df50e | 51 | /* setting board specific options */ |
94ba26f2 | 52 | #define CONFIG_MACH_TYPE MACH_TYPE_SMARTWEB |
b96fd825 | 53 | #define CONFIG_ENV_OVERWRITE 1 /* Overwrite ethaddr / serial# */ |
b96fd825 MM |
54 | #define CONFIG_SYS_AUTOLOAD "yes" |
55 | #define CONFIG_RESET_TO_RETRY | |
3b5df50e HS |
56 | |
57 | /* The LED PINs */ | |
58 | #define CONFIG_RED_LED AT91_PIN_PA9 | |
59 | #define CONFIG_GREEN_LED AT91_PIN_PA6 | |
60 | ||
61 | /* | |
62 | * SDRAM: 1 bank, 64 MB, base address 0x20000000 | |
63 | * Already initialized before u-boot gets started. | |
64 | */ | |
65 | #define CONFIG_NR_DRAM_BANKS 1 | |
66 | #define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1 | |
e8b81eef | 67 | #define CONFIG_SYS_SDRAM_SIZE (64 * SZ_1M) |
3b5df50e HS |
68 | |
69 | /* | |
70 | * Perform a SDRAM Memtest from the start of SDRAM | |
71 | * till the beginning of the U-Boot position in RAM. | |
72 | */ | |
73 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
74 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_TEXT_BASE - 0x100000) | |
75 | ||
76 | /* Size of malloc() pool */ | |
77 | #define CONFIG_SYS_MALLOC_LEN \ | |
e8b81eef | 78 | ROUND(3 * CONFIG_ENV_SIZE + (4 * SZ_1M), 0x1000) |
3b5df50e HS |
79 | |
80 | /* NAND flash settings */ | |
81 | #define CONFIG_NAND_ATMEL | |
3b5df50e HS |
82 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 |
83 | #define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3 | |
84 | #define CONFIG_SYS_NAND_DBW_8 | |
85 | #define CONFIG_SYS_NAND_MASK_ALE (1 << 21) | |
86 | #define CONFIG_SYS_NAND_MASK_CLE (1 << 22) | |
87 | #define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14 | |
88 | #define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13 | |
89 | ||
3b5df50e | 90 | #define CONFIG_MTD_DEVICE |
3b5df50e HS |
91 | |
92 | /* general purpose I/O */ | |
93 | #define CONFIG_ATMEL_LEGACY /* required until (g)pio is fixed */ | |
94 | #define CONFIG_AT91_GPIO /* enable the GPIO features */ | |
95 | #define CONFIG_AT91_GPIO_PULLUP 1 /* keep pullups on peripheral pins */ | |
96 | ||
97 | /* serial console */ | |
98 | #define CONFIG_ATMEL_USART | |
99 | #define CONFIG_USART_BASE ATMEL_BASE_DBGU | |
100 | #define CONFIG_USART_ID ATMEL_ID_SYS | |
3b5df50e HS |
101 | |
102 | /* | |
103 | * Ethernet configuration | |
104 | * | |
105 | */ | |
106 | #define CONFIG_MACB | |
107 | #define CONFIG_RMII /* use reduced MII inteface */ | |
108 | #define CONFIG_NET_RETRY_COUNT 20 /* # of DHCP/BOOTP retries */ | |
109 | #define CONFIG_AT91_WANTS_COMMON_PHY | |
110 | ||
111 | /* BOOTP and DHCP options */ | |
112 | #define CONFIG_BOOTP_BOOTFILESIZE | |
3b5df50e HS |
113 | #define CONFIG_NFSBOOTCOMMAND \ |
114 | "setenv autoload yes; setenv autoboot yes; " \ | |
115 | "setenv bootargs ${basicargs} ${mtdparts} " \ | |
116 | "root=/dev/nfs ip=dhcp nfsroot=${serverip}:/srv/nfs/rootfs; " \ | |
117 | "dhcp" | |
118 | ||
119 | /* Enable the watchdog */ | |
120 | #define CONFIG_AT91SAM9_WATCHDOG | |
121 | #if !defined(CONFIG_SPL_BUILD) | |
122 | #define CONFIG_HW_WATCHDOG | |
123 | #endif | |
124 | #define CONFIG_AT91_HW_WDT_TIMEOUT 15 | |
125 | ||
126 | #if !defined(CONFIG_SPL_BUILD) | |
127 | /* USB configuration */ | |
128 | #define CONFIG_USB_ATMEL | |
129 | #define CONFIG_USB_ATMEL_CLK_SEL_PLLB | |
130 | #define CONFIG_USB_OHCI_NEW | |
3b5df50e HS |
131 | #define CONFIG_SYS_USB_OHCI_CPU_INIT |
132 | #define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE | |
133 | #define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260" | |
134 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2 | |
e8b81eef | 135 | |
e8b81eef | 136 | /* USB DFU support */ |
e8b81eef HS |
137 | #define CONFIG_MTD_DEVICE |
138 | #define CONFIG_MTD_PARTITIONS | |
139 | ||
e8b81eef HS |
140 | #define CONFIG_USB_GADGET_AT91 |
141 | ||
142 | /* DFU class support */ | |
e8b81eef HS |
143 | #define CONFIG_SYS_DFU_DATA_BUF_SIZE SZ_1M |
144 | #define DFU_MANIFEST_POLL_TIMEOUT 25000 | |
3b5df50e HS |
145 | #endif |
146 | ||
147 | /* General Boot Parameter */ | |
3b5df50e | 148 | #define CONFIG_BOOTCOMMAND "run flashboot" |
3b5df50e | 149 | #define CONFIG_SYS_CBSIZE 512 |
3b5df50e HS |
150 | |
151 | /* | |
152 | * RAM Memory address where to put the | |
153 | * Linux Kernel befor starting. | |
154 | */ | |
155 | #define CONFIG_SYS_LOAD_ADDR 0x22000000 | |
156 | ||
157 | /* | |
158 | * The NAND Flash partitions: | |
159 | */ | |
3b5df50e HS |
160 | #define CONFIG_ENV_OFFSET (0x100000) |
161 | #define CONFIG_ENV_OFFSET_REDUND (0x180000) | |
e8b81eef HS |
162 | #define CONFIG_ENV_RANGE (SZ_512K) |
163 | #define CONFIG_ENV_SIZE (SZ_128K) | |
3b5df50e HS |
164 | |
165 | /* | |
166 | * Predefined environment variables. | |
167 | * Usefull to define some easy to use boot commands. | |
168 | */ | |
169 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
170 | \ | |
171 | "basicargs=console=ttyS0,115200\0" \ | |
172 | \ | |
43ede0bc | 173 | "mtdparts="CONFIG_MTDPARTS_DEFAULT"\0" |
3b5df50e | 174 | |
3b5df50e HS |
175 | #ifdef CONFIG_SPL_BUILD |
176 | #define CONFIG_SYS_INIT_SP_ADDR 0x301000 | |
177 | #define CONFIG_SPL_STACK_R | |
178 | #define CONFIG_SPL_STACK_R_ADDR CONFIG_SYS_TEXT_BASE | |
179 | #else | |
180 | /* | |
181 | * Initial stack pointer: 4k - GENERATED_GBL_DATA_SIZE in internal SRAM, | |
182 | * leaving the correct space for initial global data structure above that | |
183 | * address while providing maximum stack area below. | |
184 | */ | |
185 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
186 | (ATMEL_BASE_SRAM1 + 0x1000 - GENERATED_GBL_DATA_SIZE) | |
187 | #endif | |
188 | ||
3b5df50e | 189 | /* Defines for SPL */ |
3b5df50e | 190 | #define CONFIG_SPL_TEXT_BASE 0x0 |
e8b81eef | 191 | #define CONFIG_SPL_MAX_SIZE (SZ_4K) |
3b5df50e HS |
192 | |
193 | #define CONFIG_SPL_BSS_START_ADDR CONFIG_SYS_SDRAM_BASE | |
e8b81eef | 194 | #define CONFIG_SPL_BSS_MAX_SIZE (SZ_16K) |
3b5df50e HS |
195 | #define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SPL_BSS_START_ADDR + \ |
196 | CONFIG_SPL_BSS_MAX_SIZE) | |
197 | #define CONFIG_SYS_SPL_MALLOC_SIZE CONFIG_SYS_MALLOC_LEN | |
3b5df50e | 198 | |
3b5df50e | 199 | #define CONFIG_SYS_NAND_ENABLE_PIN_SPL (2*32 + 14) |
3b5df50e HS |
200 | #define CONFIG_SYS_USE_NANDFLASH 1 |
201 | #define CONFIG_SPL_NAND_DRIVERS | |
202 | #define CONFIG_SPL_NAND_BASE | |
203 | #define CONFIG_SPL_NAND_ECC | |
204 | #define CONFIG_SPL_NAND_RAW_ONLY | |
205 | #define CONFIG_SPL_NAND_SOFTECC | |
206 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x20000 | |
e8b81eef | 207 | #define CONFIG_SYS_NAND_U_BOOT_SIZE SZ_512K |
3b5df50e HS |
208 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE |
209 | #define CONFIG_SYS_NAND_U_BOOT_DST CONFIG_SYS_TEXT_BASE | |
210 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
211 | ||
e8b81eef HS |
212 | #define CONFIG_SYS_NAND_SIZE (SZ_256M) |
213 | #define CONFIG_SYS_NAND_PAGE_SIZE SZ_2K | |
214 | #define CONFIG_SYS_NAND_BLOCK_SIZE (SZ_128K) | |
3b5df50e HS |
215 | #define CONFIG_SYS_NAND_PAGE_COUNT (CONFIG_SYS_NAND_BLOCK_SIZE / \ |
216 | CONFIG_SYS_NAND_PAGE_SIZE) | |
217 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
218 | #define CONFIG_SYS_NAND_ECCSIZE 256 | |
219 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
220 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
221 | #define CONFIG_SYS_NAND_ECCPOS { 40, 41, 42, 43, 44, 45, 46, 47, \ | |
222 | 48, 49, 50, 51, 52, 53, 54, 55, \ | |
223 | 56, 57, 58, 59, 60, 61, 62, 63, } | |
224 | ||
225 | #define CONFIG_SPL_ATMEL_SIZE | |
226 | #define CONFIG_SYS_MASTER_CLOCK (198656000/2) | |
227 | #define AT91_PLL_LOCK_TIMEOUT 1000000 | |
228 | #define CONFIG_SYS_AT91_PLLA 0x2060bf09 | |
229 | #define CONFIG_SYS_MCKR 0x100 | |
230 | #define CONFIG_SYS_MCKR_CSS (0x02 | CONFIG_SYS_MCKR) | |
231 | #define CONFIG_SYS_AT91_PLLB 0x10483f0e | |
232 | ||
233 | #if defined(CONFIG_SPL_BUILD) | |
3b5df50e HS |
234 | #define CONFIG_SYS_ICACHE_OFF |
235 | #define CONFIG_SYS_DCACHE_OFF | |
3b5df50e HS |
236 | #endif |
237 | #endif /* __CONFIG_H */ |