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81a8824f WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
792a09eb | 5 | * Gary Jennejohn <garyj@denx.de> |
81a8824f WD |
6 | * David Mueller <d.mueller@elsoft.ch> |
7 | * | |
8 | * Configuation settings for the SAMSUNG SMDK2410 board. | |
9 | * | |
1a459660 | 10 | * SPDX-License-Identifier: GPL-2.0+ |
81a8824f WD |
11 | */ |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
81a8824f WD |
16 | /* |
17 | * High Level Configuration Options | |
18 | * (easy to change) | |
19 | */ | |
f2168440 | 20 | #define CONFIG_S3C24X0 /* This is a SAMSUNG S3C24x0-type SoC */ |
d0b375f6 DMEA |
21 | #define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ |
22 | #define CONFIG_SMDK2410 /* on a SAMSUNG SMDK2410 Board */ | |
81a8824f | 23 | |
4479fc5b DMEA |
24 | #define CONFIG_SYS_TEXT_BASE 0x0 |
25 | ||
7e2e04fe DMEA |
26 | #define CONFIG_SYS_GENERIC_BOARD |
27 | ||
d0b375f6 | 28 | #define CONFIG_SYS_ARM_CACHE_WRITETHROUGH |
81a8824f | 29 | |
d0b375f6 DMEA |
30 | /* input clock of PLL (the SMDK2410 has 12MHz input clock) */ |
31 | #define CONFIG_SYS_CLK_FREQ 12000000 | |
81a8824f | 32 | |
d0b375f6 DMEA |
33 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
34 | #define CONFIG_SETUP_MEMORY_TAGS | |
35 | #define CONFIG_INITRD_TAG | |
81a8824f WD |
36 | |
37 | /* | |
38 | * Hardware drivers | |
39 | */ | |
b1c0eaac BW |
40 | #define CONFIG_CS8900 /* we have a CS8900 on-board */ |
41 | #define CONFIG_CS8900_BASE 0x19000300 | |
42 | #define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ | |
81a8824f WD |
43 | |
44 | /* | |
45 | * select serial console configuration | |
46 | */ | |
300f99f4 | 47 | #define CONFIG_S3C24X0_SERIAL |
d0b375f6 DMEA |
48 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ |
49 | ||
50 | /************************************************************ | |
51 | * USB support (currently only works with D-cache off) | |
52 | ************************************************************/ | |
53 | #define CONFIG_USB_OHCI | |
fb24ffc0 | 54 | #define CONFIG_USB_OHCI_S3C24XX |
d0b375f6 DMEA |
55 | #define CONFIG_USB_KEYBOARD |
56 | #define CONFIG_USB_STORAGE | |
57 | #define CONFIG_DOS_PARTITION | |
81a8824f | 58 | |
48b42616 WD |
59 | /************************************************************ |
60 | * RTC | |
61 | ************************************************************/ | |
d0b375f6 | 62 | #define CONFIG_RTC_S3C24X0 |
48b42616 | 63 | |
81a8824f WD |
64 | |
65 | #define CONFIG_BAUDRATE 115200 | |
66 | ||
079a136c JL |
67 | /* |
68 | * BOOTP options | |
69 | */ | |
70 | #define CONFIG_BOOTP_BOOTFILESIZE | |
71 | #define CONFIG_BOOTP_BOOTPATH | |
72 | #define CONFIG_BOOTP_GATEWAY | |
73 | #define CONFIG_BOOTP_HOSTNAME | |
74 | ||
46da1e96 JL |
75 | /* |
76 | * Command line configuration. | |
77 | */ | |
78 | #include <config_cmd_default.h> | |
79 | ||
d0b375f6 | 80 | #define CONFIG_CMD_BSP |
46da1e96 | 81 | #define CONFIG_CMD_CACHE |
46da1e96 | 82 | #define CONFIG_CMD_DATE |
d0b375f6 | 83 | #define CONFIG_CMD_DHCP |
46da1e96 | 84 | #define CONFIG_CMD_ELF |
d0b375f6 DMEA |
85 | #define CONFIG_CMD_NAND |
86 | #define CONFIG_CMD_PING | |
87 | #define CONFIG_CMD_REGINFO | |
88 | #define CONFIG_CMD_USB | |
89 | ||
90 | #define CONFIG_SYS_HUSH_PARSER | |
d0b375f6 DMEA |
91 | #define CONFIG_CMDLINE_EDITING |
92 | ||
93 | /* autoboot */ | |
94 | #define CONFIG_BOOTDELAY 5 | |
95 | #define CONFIG_BOOT_RETRY_TIME -1 | |
96 | #define CONFIG_RESET_TO_RETRY | |
97 | #define CONFIG_ZERO_BOOTDELAY_CHECK | |
98 | ||
99 | #define CONFIG_NETMASK 255.255.255.0 | |
81a8824f WD |
100 | #define CONFIG_IPADDR 10.0.0.110 |
101 | #define CONFIG_SERVERIP 10.0.0.1 | |
81a8824f | 102 | |
46da1e96 | 103 | #if defined(CONFIG_CMD_KGDB) |
d0b375f6 | 104 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
81a8824f WD |
105 | #endif |
106 | ||
107 | /* | |
108 | * Miscellaneous configurable options | |
109 | */ | |
d0b375f6 DMEA |
110 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
111 | #define CONFIG_SYS_PROMPT "SMDK2410 # " | |
112 | #define CONFIG_SYS_CBSIZE 256 | |
113 | /* Print Buffer Size */ | |
114 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \ | |
115 | sizeof(CONFIG_SYS_PROMPT)+16) | |
116 | #define CONFIG_SYS_MAXARGS 16 | |
117 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE | |
118 | ||
3d3206f1 | 119 | #define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ |
81a8824f | 120 | |
d0b375f6 DMEA |
121 | #define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ |
122 | #define CONFIG_SYS_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ | |
81a8824f | 123 | |
d0b375f6 | 124 | #define CONFIG_SYS_LOAD_ADDR 0x30800000 |
81a8824f | 125 | |
d0b375f6 DMEA |
126 | /* support additional compression methods */ |
127 | #define CONFIG_BZIP2 | |
128 | #define CONFIG_LZO | |
129 | #define CONFIG_LZMA | |
130 | ||
81a8824f WD |
131 | /*----------------------------------------------------------------------- |
132 | * Physical Memory Map | |
133 | */ | |
d0b375f6 | 134 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ |
81a8824f WD |
135 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ |
136 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
137 | ||
d0b375f6 | 138 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #0 */ |
81a8824f | 139 | |
a5ec7f64 | 140 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
81a8824f WD |
141 | |
142 | /*----------------------------------------------------------------------- | |
143 | * FLASH and environment organization | |
144 | */ | |
145 | ||
a5ec7f64 DMEA |
146 | #define CONFIG_SYS_FLASH_CFI |
147 | #define CONFIG_FLASH_CFI_DRIVER | |
148 | #define CONFIG_FLASH_CFI_LEGACY | |
149 | #define CONFIG_SYS_FLASH_LEGACY_512Kx16 | |
150 | #define CONFIG_FLASH_SHOW_PROGRESS 45 | |
81a8824f | 151 | |
a5ec7f64 | 152 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 |
d0b375f6 | 153 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
a5ec7f64 | 154 | #define CONFIG_SYS_MAX_FLASH_SECT (19) |
81a8824f | 155 | |
d0b375f6 DMEA |
156 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) |
157 | #define CONFIG_ENV_IS_IN_FLASH | |
158 | #define CONFIG_ENV_SIZE 0x10000 | |
159 | /* allow to overwrite serial and ethaddr */ | |
160 | #define CONFIG_ENV_OVERWRITE | |
161 | ||
162 | /* | |
163 | * Size of malloc() pool | |
164 | * BZIP2 / LZO / LZMA need a lot of RAM | |
165 | */ | |
166 | #define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) | |
81a8824f | 167 | |
a5ec7f64 DMEA |
168 | #define CONFIG_SYS_MONITOR_LEN (448 * 1024) |
169 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
170 | ||
d0b375f6 DMEA |
171 | /* |
172 | * NAND configuration | |
173 | */ | |
174 | #ifdef CONFIG_CMD_NAND | |
175 | #define CONFIG_NAND_S3C2410 | |
176 | #define CONFIG_SYS_S3C2410_NAND_HWECC | |
177 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
d0b375f6 DMEA |
178 | #define CONFIG_SYS_NAND_BASE 0x4E000000 |
179 | #endif | |
180 | ||
181 | /* | |
182 | * File system | |
183 | */ | |
184 | #define CONFIG_CMD_FAT | |
185 | #define CONFIG_CMD_EXT2 | |
186 | #define CONFIG_CMD_UBI | |
187 | #define CONFIG_CMD_UBIFS | |
188 | #define CONFIG_CMD_MTDPARTS | |
189 | #define CONFIG_MTD_DEVICE | |
190 | #define CONFIG_MTD_PARTITIONS | |
191 | #define CONFIG_YAFFS2 | |
192 | #define CONFIG_RBTREE | |
193 | ||
b9f15902 DMEA |
194 | /* additions for new relocation code, must be added to all boards */ |
195 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
196 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ | |
197 | GENERATED_GBL_DATA_SIZE) | |
198 | ||
d0b375f6 | 199 | #define CONFIG_BOARD_EARLY_INIT_F |
b9f15902 | 200 | |
d0b375f6 | 201 | #endif /* __CONFIG_H */ |