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81a8824f WD |
1 | /* |
2 | * (C) Copyright 2002 | |
3 | * Sysgo Real-Time Solutions, GmbH <www.elinos.com> | |
4 | * Marius Groeger <mgroeger@sysgo.de> | |
5 | * Gary Jennejohn <gj@denx.de> | |
6 | * David Mueller <d.mueller@elsoft.ch> | |
7 | * | |
8 | * Configuation settings for the SAMSUNG SMDK2410 board. | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | #ifndef __CONFIG_H | |
30 | #define __CONFIG_H | |
31 | ||
81a8824f WD |
32 | /* |
33 | * High Level Configuration Options | |
34 | * (easy to change) | |
35 | */ | |
36 | #define CONFIG_ARM920T 1 /* This is an ARM920T Core */ | |
37 | #define CONFIG_S3C2410 1 /* in a SAMSUNG S3C2410 SoC */ | |
38 | #define CONFIG_SMDK2410 1 /* on a SAMSUNG SMDK2410 Board */ | |
39 | ||
40 | /* input clock of PLL */ | |
7f6c2cbc | 41 | #define CONFIG_SYS_CLK_FREQ 12000000/* the SMDK2410 has 12MHz input clock */ |
81a8824f WD |
42 | |
43 | ||
44 | #define USE_920T_MMU 1 | |
45 | #undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ | |
46 | ||
47 | /* | |
48 | * Size of malloc() pool | |
49 | */ | |
699b13a6 | 50 | #define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) |
a8c7c708 | 51 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ |
81a8824f WD |
52 | |
53 | /* | |
54 | * Hardware drivers | |
55 | */ | |
56 | #define CONFIG_DRIVER_CS8900 1 /* we have a CS8900 on-board */ | |
57 | #define CS8900_BASE 0x19000300 | |
58 | #define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ | |
59 | ||
60 | /* | |
61 | * select serial console configuration | |
62 | */ | |
63 | #define CONFIG_SERIAL1 1 /* we use SERIAL 1 on SMDK2410 */ | |
64 | ||
48b42616 WD |
65 | /************************************************************ |
66 | * RTC | |
67 | ************************************************************/ | |
68 | #define CONFIG_RTC_S3C24X0 1 | |
69 | ||
81a8824f WD |
70 | /* allow to overwrite serial and ethaddr */ |
71 | #define CONFIG_ENV_OVERWRITE | |
72 | ||
73 | #define CONFIG_BAUDRATE 115200 | |
74 | ||
46da1e96 | 75 | |
079a136c JL |
76 | /* |
77 | * BOOTP options | |
78 | */ | |
79 | #define CONFIG_BOOTP_BOOTFILESIZE | |
80 | #define CONFIG_BOOTP_BOOTPATH | |
81 | #define CONFIG_BOOTP_GATEWAY | |
82 | #define CONFIG_BOOTP_HOSTNAME | |
83 | ||
84 | ||
46da1e96 JL |
85 | /* |
86 | * Command line configuration. | |
87 | */ | |
88 | #include <config_cmd_default.h> | |
89 | ||
90 | #define CONFIG_CMD_CACHE | |
46da1e96 JL |
91 | #define CONFIG_CMD_DATE |
92 | #define CONFIG_CMD_ELF | |
93 | ||
81a8824f WD |
94 | |
95 | #define CONFIG_BOOTDELAY 3 | |
53677ef1 | 96 | /*#define CONFIG_BOOTARGS "root=ramfs devfs=mount console=ttySA0,9600" */ |
81a8824f WD |
97 | /*#define CONFIG_ETHADDR 08:00:3e:26:0a:5b */ |
98 | #define CONFIG_NETMASK 255.255.255.0 | |
99 | #define CONFIG_IPADDR 10.0.0.110 | |
100 | #define CONFIG_SERVERIP 10.0.0.1 | |
101 | /*#define CONFIG_BOOTFILE "elinos-lart" */ | |
102 | /*#define CONFIG_BOOTCOMMAND "tftp; bootm" */ | |
103 | ||
46da1e96 | 104 | #if defined(CONFIG_CMD_KGDB) |
81a8824f WD |
105 | #define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ |
106 | /* what's this ? it's not used anywhere */ | |
107 | #define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ | |
108 | #endif | |
109 | ||
110 | /* | |
111 | * Miscellaneous configurable options | |
112 | */ | |
113 | #define CFG_LONGHELP /* undef to save memory */ | |
114 | #define CFG_PROMPT "SMDK2410 # " /* Monitor Command Prompt */ | |
115 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
116 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
117 | #define CFG_MAXARGS 16 /* max number of command args */ | |
118 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
119 | ||
120 | #define CFG_MEMTEST_START 0x30000000 /* memtest works on */ | |
121 | #define CFG_MEMTEST_END 0x33F00000 /* 63 MB in DRAM */ | |
122 | ||
123 | #undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ | |
124 | ||
125 | #define CFG_LOAD_ADDR 0x33000000 /* default load address */ | |
126 | ||
127 | /* the PWM TImer 4 uses a counter of 15625 for 10 ms, so we need */ | |
128 | /* it to wrap 100 times (total 1562500) to get 1 sec. */ | |
129 | #define CFG_HZ 1562500 | |
130 | ||
131 | /* valid baudrates */ | |
132 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
133 | ||
134 | /*----------------------------------------------------------------------- | |
135 | * Stack sizes | |
136 | * | |
137 | * The stack sizes are set up in start.S using the settings below | |
138 | */ | |
139 | #define CONFIG_STACKSIZE (128*1024) /* regular stack */ | |
140 | #ifdef CONFIG_USE_IRQ | |
141 | #define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ | |
142 | #define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ | |
143 | #endif | |
144 | ||
145 | /*----------------------------------------------------------------------- | |
146 | * Physical Memory Map | |
147 | */ | |
148 | #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ | |
149 | #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ | |
150 | #define PHYS_SDRAM_1_SIZE 0x04000000 /* 64 MB */ | |
151 | ||
152 | #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ | |
153 | ||
154 | #define CFG_FLASH_BASE PHYS_FLASH_1 | |
155 | ||
156 | /*----------------------------------------------------------------------- | |
157 | * FLASH and environment organization | |
158 | */ | |
159 | ||
160 | #define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ | |
161 | #if 0 | |
162 | #define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ | |
163 | #endif | |
164 | ||
165 | #define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
166 | #ifdef CONFIG_AMD_LV800 | |
167 | #define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ | |
168 | #define CFG_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ | |
169 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x0F0000) /* addr of environment */ | |
170 | #endif | |
171 | #ifdef CONFIG_AMD_LV400 | |
172 | #define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ | |
173 | #define CFG_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ | |
174 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x070000) /* addr of environment */ | |
175 | #endif | |
176 | ||
177 | /* timeout values are in ticks */ | |
178 | #define CFG_FLASH_ERASE_TOUT (5*CFG_HZ) /* Timeout for Flash Erase */ | |
179 | #define CFG_FLASH_WRITE_TOUT (5*CFG_HZ) /* Timeout for Flash Write */ | |
180 | ||
181 | #define CFG_ENV_IS_IN_FLASH 1 | |
182 | #define CFG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
183 | ||
184 | #endif /* __CONFIG_H */ |