projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
| e21185ba CK |
2 | /* |
| 3 | * Copyright (C) 2011 Samsung Electronics | |
| 4 | * | |
| 393cb361 | 5 | * Configuration settings for the SAMSUNG SMDKV310 (EXYNOS4210) board. |
| e21185ba CK |
6 | */ |
| 7 | ||
| 8 | #ifndef __CONFIG_H | |
| 9 | #define __CONFIG_H | |
| 10 | ||
| 1d551100 SG |
11 | #include "exynos4-common.h" |
| 12 | ||
| 13 | #undef CONFIG_BOARD_COMMON | |
| e30824f4 | 14 | #undef CONFIG_USB_GADGET_DWC2_OTG_PHY |
| 1d551100 | 15 | #undef CONFIG_REVISION_TAG |
| 1d551100 | 16 | |
| e21185ba | 17 | /* High Level Configuration Options */ |
| 393cb361 | 18 | #define CONFIG_EXYNOS4210 1 /* which is a EXYNOS4210 SoC */ |
| e21185ba | 19 | |
| b3c5a49b CK |
20 | /* Mach Type */ |
| 21 | #define CONFIG_MACH_TYPE MACH_TYPE_SMDKV310 | |
| 22 | ||
| e21185ba | 23 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
| e21185ba | 24 | |
| e21185ba CK |
25 | /* Handling Sleep Mode*/ |
| 26 | #define S5P_CHECK_SLEEP 0x00000BAD | |
| 27 | #define S5P_CHECK_DIDLE 0xBAD00000 | |
| 643be9c0 | 28 | #define S5P_CHECK_LPA 0xABAD0000 |
| e21185ba | 29 | |
| e21185ba | 30 | /* select serial console configuration */ |
| 393cb361 | 31 | #define EXYNOS4_DEFAULT_UART_OFFSET 0x010000 |
| e21185ba | 32 | |
| e21185ba CK |
33 | /* allow to overwrite serial and ethaddr */ |
| 34 | #define CONFIG_ENV_OVERWRITE | |
| 35 | ||
| 5187d8dd | 36 | /* MMC SPL */ |
| 643be9c0 | 37 | #define CONFIG_SKIP_LOWLEVEL_INIT |
| 9b3ab1c9 | 38 | #define COPY_BL2_FNPTR_ADDR 0x00002488 |
| e21185ba CK |
39 | |
| 40 | #define CONFIG_BOOTCOMMAND "fatload mmc 0 40007000 uImage; bootm 40007000" | |
| 41 | ||
| 42 | /* Miscellaneous configurable options */ | |
| e21185ba | 43 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" |
| e21185ba | 44 | /* memtest works on */ |
| e21185ba CK |
45 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x3E00000) |
| 46 | ||
| e21185ba | 47 | /* SMDKV310 has 4 bank of DRAM */ |
| e21185ba CK |
48 | #define SDRAM_BANK_SIZE (512UL << 20UL) /* 512 MB */ |
| 49 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE | |
| 50 | #define PHYS_SDRAM_1_SIZE SDRAM_BANK_SIZE | |
| 51 | #define PHYS_SDRAM_2 (CONFIG_SYS_SDRAM_BASE + SDRAM_BANK_SIZE) | |
| 52 | #define PHYS_SDRAM_2_SIZE SDRAM_BANK_SIZE | |
| 53 | #define PHYS_SDRAM_3 (CONFIG_SYS_SDRAM_BASE + (2 * SDRAM_BANK_SIZE)) | |
| 54 | #define PHYS_SDRAM_3_SIZE SDRAM_BANK_SIZE | |
| 55 | #define PHYS_SDRAM_4 (CONFIG_SYS_SDRAM_BASE + (3 * SDRAM_BANK_SIZE)) | |
| 56 | #define PHYS_SDRAM_4_SIZE SDRAM_BANK_SIZE | |
| 57 | ||
| 58 | /* FLASH and environment organization */ | |
| e21185ba | 59 | |
| e21185ba CK |
60 | #define CONFIG_CLK_1000_400_200 |
| 61 | ||
| 62 | /* MIU (Memory Interleaving Unit) */ | |
| 63 | #define CONFIG_MIU_2BIT_INTERLEAVED | |
| 64 | ||
| e21185ba | 65 | #define CONFIG_SYS_MMC_ENV_DEV 0 |
| e21185ba CK |
66 | #define RESERVE_BLOCK_SIZE (512) |
| 67 | #define BL1_SIZE (16 << 10) /*16 K reserved for BL1*/ | |
| e21185ba | 68 | |
| 643be9c0 RS |
69 | #define CONFIG_SPL_MAX_FOOTPRINT (14 * 1024) |
| 70 | ||
| 71 | #define CONFIG_SYS_INIT_SP_ADDR 0x02040000 | |
| e21185ba | 72 | |
| a187559e | 73 | /* U-Boot copy size from boot Media to DRAM.*/ |
| e21185ba CK |
74 | #define COPY_BL2_SIZE 0x80000 |
| 75 | #define BL2_START_OFFSET ((CONFIG_ENV_OFFSET + CONFIG_ENV_SIZE)/512) | |
| 76 | #define BL2_SIZE_BLOC_COUNT (COPY_BL2_SIZE/512) | |
| 77 | ||
| 78 | /* Ethernet Controllor Driver */ | |
| 79 | #ifdef CONFIG_CMD_NET | |
| e21185ba CK |
80 | #define CONFIG_ENV_SROM_BANK 1 |
| 81 | #endif /*CONFIG_CMD_NET*/ | |
| 07407d97 | 82 | |
| e21185ba | 83 | #endif /* __CONFIG_H */ |