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075866d8 HS |
1 | /* |
2 | * (C) Copyright 2003-2006 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * (C) Copyright 2004-2005 | |
6 | * Martin Krause, TQ-Systems GmbH, martin.krause@tqs.de | |
7 | * | |
8 | * See file CREDITS for list of people who contributed to this | |
9 | * project. | |
10 | * | |
11 | * This program is free software; you can redistribute it and/or | |
12 | * modify it under the terms of the GNU General Public License as | |
13 | * published by the Free Software Foundation; either version 2 of | |
14 | * the License, or (at your option) any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; if not, write to the Free Software | |
23 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
24 | * MA 02111-1307 USA | |
25 | */ | |
26 | ||
27 | #ifndef __CONFIG_H | |
28 | #define __CONFIG_H | |
29 | ||
30 | /* | |
31 | * High Level Configuration Options | |
32 | * (easy to change) | |
33 | */ | |
34 | ||
35 | #define CONFIG_MPC5xxx 1 /* This is an MPC5xxx CPU */ | |
36 | #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ | |
37 | #define CONFIG_TQM5200 1 /* ... on TQM5200 module */ | |
38 | #undef CONFIG_TQM5200_REV100 /* define for revision 100 modules */ | |
39 | ||
40 | #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ | |
41 | ||
42 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
43 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
44 | ||
075866d8 HS |
45 | /* |
46 | * Serial console configuration | |
47 | */ | |
48 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ | |
49 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
50 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
51 | ||
52 | /* Partitions */ | |
53 | #define CONFIG_MAC_PARTITION | |
54 | #define CONFIG_DOS_PARTITION | |
55 | #define CONFIG_ISO_PARTITION | |
56 | ||
57 | /* POST support */ | |
58 | #define CONFIG_POST (CFG_POST_MEMORY | \ | |
59 | CFG_POST_CPU | \ | |
60 | CFG_POST_I2C) | |
61 | ||
62 | #ifdef CONFIG_POST | |
075866d8 HS |
63 | /* preserve space for the post_word at end of on-chip SRAM */ |
64 | #define MPC5XXX_SRAM_POST_SIZE MPC5XXX_SRAM_SIZE-4 | |
075866d8 HS |
65 | #endif |
66 | ||
46da1e96 | 67 | |
079a136c JL |
68 | /* |
69 | * BOOTP options | |
70 | */ | |
71 | #define CONFIG_BOOTP_BOOTFILESIZE | |
72 | #define CONFIG_BOOTP_BOOTPATH | |
73 | #define CONFIG_BOOTP_GATEWAY | |
74 | #define CONFIG_BOOTP_HOSTNAME | |
75 | ||
76 | ||
075866d8 | 77 | /* |
46da1e96 | 78 | * Command line configuration. |
075866d8 | 79 | */ |
46da1e96 JL |
80 | #include <config_cmd_default.h> |
81 | #define CONFIG_CMD_ASKENV | |
82 | #define CONFIG_CMD_DATE | |
83 | #define CONFIG_CMD_DHCP | |
84 | #define CONFIG_CMD_ECHO | |
85 | #define CONFIG_CMD_EEPROM | |
86 | #define CONFIG_CMD_I2C | |
87 | #define CONFIG_CMD_JFFS2 | |
88 | #define CONFIG_CMD_MII | |
89 | #define CONFIG_CMD_NFS | |
90 | #define CONFIG_CMD_PING | |
46da1e96 JL |
91 | #define CONFIG_CMD_REGINFO |
92 | #define CONFIG_CMD_SNTP | |
93 | ||
af075ee9 JL |
94 | #ifdef CONFIG_POST |
95 | #define CONFIG_CMD_DIAG | |
96 | #endif | |
97 | ||
075866d8 HS |
98 | |
99 | #define CONFIG_TIMESTAMP /* display image timestamps */ | |
100 | ||
101 | #if (TEXT_BASE == 0xFC000000) /* Boot low */ | |
102 | # define CFG_LOWBOOT 1 | |
103 | #endif | |
104 | ||
105 | /* | |
106 | * Autobooting | |
107 | */ | |
108 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
109 | ||
110 | #define CONFIG_PREBOOT "echo;" \ | |
111 | "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ | |
112 | "echo" | |
113 | ||
114 | #undef CONFIG_BOOTARGS | |
115 | ||
116 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
117 | "netdev=eth0\0" \ | |
118 | "rootpath=/opt/eldk/ppc_6xx\0" \ | |
119 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
120 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
121 | "nfsroot=${serverip}:${rootpath}\0" \ | |
122 | "addip=setenv bootargs ${bootargs} " \ | |
123 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
124 | ":${hostname}:${netdev}:off panic=1\0" \ | |
125 | "flash_self=run ramargs addip;" \ | |
126 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ | |
127 | "flash_nfs=run nfsargs addip;" \ | |
128 | "bootm ${kernel_addr}\0" \ | |
129 | "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ | |
130 | "bootfile=/tftpboot/smmaco4/uImage\0" \ | |
131 | "load=tftp 200000 ${u-boot}\0" \ | |
132 | "u-boot=/tftpboot/smmaco4/u-boot.bin\0" \ | |
133 | "update=protect off FC000000 FC05FFFF;" \ | |
134 | "erase FC000000 FC05FFFF;" \ | |
135 | "cp.b 200000 FC000000 ${filesize};" \ | |
136 | "protect on FC000000 FC05FFFF\0" \ | |
137 | "" | |
138 | ||
139 | #define CONFIG_BOOTCOMMAND "run net_nfs" | |
140 | ||
141 | /* | |
142 | * IPB Bus clocking configuration. | |
143 | */ | |
c99512d6 | 144 | #define CFG_IPBCLK_EQUALS_XLBCLK /* define for 133MHz speed */ |
075866d8 | 145 | |
c99512d6 | 146 | #if defined(CFG_IPBCLK_EQUALS_XLBCLK) |
075866d8 HS |
147 | /* |
148 | * PCI Bus clocking configuration | |
149 | * | |
150 | * Actually a PCI Clock of 66 MHz is only set (in cpu_init.c) if | |
c99512d6 BS |
151 | * CFG_IPBCLK_EQUALS_XLBCLK is defined. This is because a PCI Clock |
152 | * of 66 MHz yet hasn't been tested with a IPB Bus Clock of 66 MHz. | |
075866d8 | 153 | */ |
c99512d6 | 154 | #define CFG_PCICLK_EQUALS_IPBCLK_DIV2 /* define for 66MHz speed */ |
075866d8 HS |
155 | #endif |
156 | ||
157 | /* | |
158 | * I2C configuration | |
159 | */ | |
160 | #define CONFIG_HARD_I2C 1 /* I2C with hardware support */ | |
161 | #ifdef CONFIG_TQM5200_REV100 | |
162 | #define CFG_I2C_MODULE 1 /* Select I2C module #1 for rev. 100 board */ | |
163 | #else | |
164 | #define CFG_I2C_MODULE 2 /* Select I2C module #2 for all other revs */ | |
165 | #endif | |
166 | ||
167 | /* | |
168 | * I2C clock frequency | |
169 | * | |
170 | * Please notice, that the resulting clock frequency could differ from the | |
171 | * configured value. This is because the I2C clock is derived from system | |
172 | * clock over a frequency divider with only a few divider values. U-boot | |
173 | * calculates the best approximation for CFG_I2C_SPEED. However the calculated | |
174 | * approximation allways lies below the configured value, never above. | |
175 | */ | |
176 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
177 | #define CFG_I2C_SLAVE 0x7F | |
178 | ||
179 | /* | |
180 | * EEPROM configuration for onboard EEPROM M24C32 (M24C64 should work | |
181 | * also). For other EEPROMs configuration should be verified. On Mini-FAP the | |
182 | * EEPROM (24C64) is on the same I2C address (but on other I2C bus), so the | |
183 | * same configuration could be used. | |
184 | */ | |
185 | #define CFG_I2C_EEPROM_ADDR 0x50 /* 1010000x */ | |
186 | #define CFG_I2C_EEPROM_ADDR_LEN 2 | |
187 | #define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
188 | #define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
189 | ||
190 | /* | |
191 | * Flash configuration | |
192 | */ | |
193 | #define CFG_FLASH_BASE TEXT_BASE /* 0xFC000000 */ | |
194 | ||
195 | /* use CFI flash driver if no module variant is spezified */ | |
196 | #define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ | |
197 | #define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ | |
198 | #define CFG_FLASH_BANKS_LIST { CFG_BOOTCS_START } | |
199 | #define CFG_FLASH_EMPTY_INFO | |
200 | #define CFG_FLASH_SIZE 0x04000000 /* 64 MByte */ | |
201 | #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
202 | #undef CFG_FLASH_USE_BUFFER_WRITE /* not supported yet for AMD */ | |
203 | ||
204 | #if !defined(CFG_LOWBOOT) | |
205 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00760000 + 0x00800000) | |
206 | #else /* CFG_LOWBOOT */ | |
207 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00060000) | |
208 | #endif /* CFG_LOWBOOT */ | |
209 | #define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks | |
210 | (= chip selects) */ | |
211 | #define CFG_FLASH_ERASE_TOUT 240000 /* Flash Erase Timeout (in ms) */ | |
212 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (in ms) */ | |
213 | ||
214 | /* Dynamic MTD partition support */ | |
215 | #define CONFIG_JFFS2_CMDLINE | |
216 | #define MTDIDS_DEFAULT "nor0=TQM5200-0" | |
217 | #define MTDPARTS_DEFAULT "mtdparts=TQM5200-0:640k(firmware)," \ | |
218 | "1408k(kernel)," \ | |
219 | "2m(initrd)," \ | |
220 | "4m(small-fs)," \ | |
221 | "16m(big-fs)," \ | |
222 | "8m(misc)" | |
223 | ||
224 | /* | |
225 | * Environment settings | |
226 | */ | |
227 | #define CFG_ENV_IS_IN_FLASH 1 | |
228 | #define CFG_ENV_SIZE 0x10000 | |
229 | #define CFG_ENV_SECT_SIZE 0x20000 | |
230 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + CFG_ENV_SECT_SIZE) | |
231 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
232 | ||
233 | /* | |
234 | * Memory map | |
235 | */ | |
236 | #define CFG_MBAR 0xF0000000 | |
237 | #define CFG_SDRAM_BASE 0x00000000 | |
238 | #define CFG_DEFAULT_MBAR 0x80000000 | |
239 | ||
240 | /* Use ON-Chip SRAM until RAM will be available */ | |
241 | #define CFG_INIT_RAM_ADDR MPC5XXX_SRAM | |
242 | #ifdef CONFIG_POST | |
243 | /* preserve space for the post_word at end of on-chip SRAM */ | |
244 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_POST_SIZE | |
245 | #else | |
246 | #define CFG_INIT_RAM_END MPC5XXX_SRAM_SIZE | |
247 | #endif | |
248 | ||
249 | ||
250 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
251 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
252 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
253 | ||
254 | #define CFG_MONITOR_BASE TEXT_BASE | |
255 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
256 | # define CFG_RAMBOOT 1 | |
257 | #endif | |
258 | ||
259 | #define CFG_MONITOR_LEN (384 << 10) /* Reserve 384 kB for Monitor */ | |
260 | #define CFG_MALLOC_LEN (256 << 10) /* Reserve 256 kB for malloc() */ | |
261 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
262 | ||
263 | /* | |
264 | * Ethernet configuration | |
265 | */ | |
266 | #define CONFIG_MPC5xxx_FEC 1 | |
267 | /* | |
268 | * Define CONFIG_FEC_10MBIT to force FEC at 10Mb | |
269 | */ | |
270 | /* #define CONFIG_FEC_10MBIT 1 */ | |
271 | #define CONFIG_PHY_ADDR 0x00 | |
272 | ||
273 | /* | |
274 | * GPIO configuration | |
275 | * | |
276 | * use pin gpio_wkup_6 as second SDRAM chip select (mem_cs1): | |
277 | * Bit 0 (mask: 0x80000000): 1 | |
278 | * use ALT CAN position: Bits 2-3 (mask: 0x30000000): | |
279 | * 00 -> No Alternatives, CAN1/2 on PSC2 according to PSC2 setting. | |
280 | * 01 -> CAN1 on I2C1, CAN2 on Tmr0/1. | |
281 | * Use for REV200 STK52XX boards. Do not use with REV100 modules | |
282 | * (because, there I2C1 is used as I2C bus) | |
283 | * use PSC1 as UART: Bits 28-31 (mask: 0x00000007): 0100 | |
284 | * use PSC2 as CAN: Bits 25:27 (mask: 0x00000030) | |
285 | * 000 -> All PSC2 pins are GIOPs | |
286 | * 001 -> CAN1/2 on PSC2 pins | |
287 | * Use for REV100 STK52xx boards | |
288 | * use PSC6: | |
289 | * on STK52xx: | |
290 | * use as UART. Pins PSC6_0 to PSC6_3 are used. | |
291 | * Bits 9:11 (mask: 0x00700000): | |
292 | * 101 -> PSC6 : Extended POST test is not available | |
293 | * on MINI-FAP and TQM5200_IB: | |
294 | * use PSC6_0 to PSC6_3 as GPIO: Bits 9:11 (mask: 0x00700000): | |
295 | * 000 -> PSC6 could not be used as UART, CODEC or IrDA | |
296 | * GPIO on PSC6_3 is used in post_hotkeys_pressed() to enable extended POST | |
297 | * tests. | |
298 | */ | |
299 | #if defined (CONFIG_MINIFAP) | |
300 | # define CFG_GPS_PORT_CONFIG 0x91000004 | |
301 | #elif defined (CONFIG_STK52XX) | |
302 | # if defined (CONFIG_STK52XX_REV100) | |
303 | # define CFG_GPS_PORT_CONFIG 0x81500014 | |
304 | # else /* STK52xx REV200 and above */ | |
305 | # if defined (CONFIG_TQM5200_REV100) | |
306 | # error TQM5200 REV100 not supported on STK52XX REV200 or above | |
307 | # else/* TQM5200 REV200 and above */ | |
308 | # define CFG_GPS_PORT_CONFIG 0x91500004 | |
309 | # endif | |
310 | # endif | |
311 | #else /* TMQ5200 Inbetriebnahme-Board */ | |
312 | # define CFG_GPS_PORT_CONFIG 0x81000004 | |
313 | #endif | |
314 | ||
315 | /* | |
316 | * RTC configuration | |
317 | */ | |
318 | #define CONFIG_RTC_MPC5200 1 /* use internal MPC5200 RTC */ | |
319 | ||
320 | /* | |
321 | * Miscellaneous configurable options | |
322 | */ | |
323 | #define CFG_LONGHELP /* undef to save memory */ | |
324 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
46da1e96 | 325 | #if defined(CONFIG_CMD_KGDB) |
075866d8 HS |
326 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
327 | #else | |
328 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
329 | #endif | |
330 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
331 | #define CFG_MAXARGS 16 /* max number of command args */ | |
332 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
333 | ||
334 | /* Enable an alternate, more extensive memory test */ | |
335 | #define CFG_ALT_MEMTEST | |
336 | ||
337 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
338 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
339 | ||
340 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
341 | ||
342 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
343 | ||
46da1e96 JL |
344 | #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ |
345 | #if defined(CONFIG_CMD_KGDB) | |
346 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ | |
347 | #endif | |
348 | ||
075866d8 | 349 | /* |
079a136c | 350 | * Enable loopw command. |
075866d8 HS |
351 | */ |
352 | #define CONFIG_LOOPW | |
353 | ||
354 | /* | |
355 | * Various low-level settings | |
356 | */ | |
357 | #if defined(CONFIG_MPC5200) | |
358 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
359 | #define CFG_HID0_FINAL HID0_ICE | |
360 | #else | |
361 | #define CFG_HID0_INIT 0 | |
362 | #define CFG_HID0_FINAL 0 | |
363 | #endif | |
364 | ||
365 | #define CFG_BOOTCS_START CFG_FLASH_BASE | |
366 | #define CFG_BOOTCS_SIZE CFG_FLASH_SIZE | |
c99512d6 | 367 | #ifdef CFG_PCICLK_EQUALS_IPBCLK_DIV2 |
075866d8 HS |
368 | #define CFG_BOOTCS_CFG 0x0008DF30 /* for pci_clk = 66 MHz */ |
369 | #else | |
370 | #define CFG_BOOTCS_CFG 0x0004DF30 /* for pci_clk = 33 MHz */ | |
371 | #endif | |
372 | #define CFG_CS0_START CFG_FLASH_BASE | |
373 | #define CFG_CS0_SIZE CFG_FLASH_SIZE | |
374 | ||
375 | #define CFG_CS_BURST 0x00000000 | |
376 | #define CFG_CS_DEADCYCLE 0x33333311 /* 1 dead cycle for flash and SM501 */ | |
377 | ||
378 | #define CFG_RESET_ADDRESS 0xff000000 | |
379 | ||
380 | #endif /* __CONFIG_H */ |