[people/ms/u-boot.git] / include / configs / snapper9260.h

/*
 * Bluewater Systems Snapper 9260 and 9G20 modules
 *
 * (C) Copyright 2011 Bluewater Systems
 *   Author: Andre Renaud <andre@bluewatersys.com>
 *   Author: Ryan Mallon <ryan@bluewatersys.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* SoC type is defined in boards.cfg */
#include <asm/hardware.h>
#include <linux/sizes.h>

#define CONFIG_SYS_TEXT_BASE		0x21f00000

/* ARM asynchronous clock */
#define CONFIG_SYS_AT91_MAIN_CLOCK	18432000 /* External Crystal, in Hz */
#define CONFIG_SYS_AT91_SLOW_CLOCK	32768

/* CPU */
#define CONFIG_ARCH_CPU_INIT

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs	*/
#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_INITRD_TAG
#define CONFIG_SKIP_LOWLEVEL_INIT

/* SDRAM */
#define CONFIG_NR_DRAM_BANKS		1
#define CONFIG_SYS_SDRAM_BASE		ATMEL_BASE_CS1
#define CONFIG_SYS_SDRAM_SIZE		(64 * 1024 * 1024) /* 64MB */
#define CONFIG_SYS_INIT_SP_ADDR		(ATMEL_BASE_SRAM1 + 0x1000 - \
					 GENERATED_GBL_DATA_SIZE)

/* Mem test settings */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + (1024 * 1024))

/* NAND Flash */
#define CONFIG_NAND_ATMEL
#define CONFIG_SYS_NO_FLASH
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_BASE		ATMEL_BASE_CS3
#define CONFIG_SYS_NAND_DBW_8
#define CONFIG_SYS_NAND_MASK_ALE	(1 << 21) /* AD21 */
#define CONFIG_SYS_NAND_MASK_CLE	(1 << 22) /* AD22 */
#define CONFIG_SYS_NAND_ENABLE_PIN	AT91_PIN_PC14
#define CONFIG_SYS_NAND_READY_PIN	AT91_PIN_PC13

/* Ethernet */
#define CONFIG_MACB
#define CONFIG_RMII
#define CONFIG_NET_RETRY_COUNT		20
#define CONFIG_RESET_PHY_R
#define CONFIG_AT91_WANTS_COMMON_PHY
#define CONFIG_TFTP_PORT
#define CONFIG_TFTP_TSIZE

/* USB */
#define CONFIG_USB_ATMEL
#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
#define CONFIG_USB_OHCI_NEW
#define CONFIG_SYS_USB_OHCI_CPU_INIT
#define CONFIG_SYS_USB_OHCI_REGS_BASE	ATMEL_UHP_BASE
#define CONFIG_SYS_USB_OHCI_SLOT_NAME	"at91sam9260"
#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS	2

/* GPIOs and IO expander */
#define CONFIG_ATMEL_LEGACY
#define CONFIG_AT91_GPIO
#define CONFIG_AT91_GPIO_PULLUP		1
#define CONFIG_PCA953X
#define CONFIG_SYS_I2C_PCA953X_ADDR	0x28
#define CONFIG_SYS_I2C_PCA953X_WIDTH	{ {0x28, 16} }

/* UARTs/Serial console */
#define CONFIG_ATMEL_USART
#ifndef CONFIG_DM_SERIAL
#define CONFIG_USART_BASE		ATMEL_BASE_DBGU
#define CONFIG_USART_ID			ATMEL_ID_SYS
#endif
#define CONFIG_BAUDRATE			115200

/* I2C - Bit-bashed */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	100000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define I2C_INIT do {							\
		at91_set_gpio_output(AT91_PIN_PA23, 1);			\
		at91_set_gpio_output(AT91_PIN_PA24, 1);			\
		at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1);	\
		at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1);	\
	} while (0)
#define I2C_SOFT_DECLARATIONS
#define I2C_ACTIVE
#define I2C_TRISTATE	at91_set_gpio_input(AT91_PIN_PA23, 1);
#define I2C_READ	at91_get_gpio_value(AT91_PIN_PA23);
#define I2C_SDA(bit) do {						\
		if (bit) {						\
			at91_set_gpio_input(AT91_PIN_PA23, 1);		\
		} else {						\
			at91_set_gpio_output(AT91_PIN_PA23, 1);		\
			at91_set_gpio_value(AT91_PIN_PA23, bit);	\
		}							\
	} while (0)
#define I2C_SCL(bit)	at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
#define I2C_DELAY	udelay(2)

/* Boot options */
#define CONFIG_SYS_LOAD_ADDR		0x23000000

#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME

/* Environment settings */
#define CONFIG_ENV_IS_IN_NAND
#define CONFIG_ENV_OFFSET		(512 << 10)
#define CONFIG_ENV_SIZE			(256 << 10)
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BOOTARGS			"console=ttyS0,115200 ip=any"

/* Console settings */
#define CONFIG_SYS_CBSIZE		256
#define CONFIG_SYS_MAXARGS		16
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE +		\
					 sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_LONGHELP
#define CONFIG_CMDLINE_EDITING
#define CONFIG_AUTO_COMPLETE

/* U-Boot memory settings */
#define CONFIG_SYS_MALLOC_LEN		(1 << 20)

/* Command line configuration */
#define CONFIG_CMD_NAND
#define CONFIG_CMD_PCA953X
#define CONFIG_CMD_PCA953X_INFO

#endif /* __CONFIG_H */
Commit	Line	Data
b8d41dda RM	1	/*
	2	* Bluewater Systems Snapper 9260 and 9G20 modules
	3	*
	4	* (C) Copyright 2011 Bluewater Systems
	5	* Author: Andre Renaud <andre@bluewatersys.com>
	6	* Author: Ryan Mallon <ryan@bluewatersys.com>
	7	*
1a459660	8	* SPDX-License-Identifier: GPL-2.0+
b8d41dda RM	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14	/* SoC type is defined in boards.cfg */
	15	#include <asm/hardware.h>
1ace4022	16	#include <linux/sizes.h>
b8d41dda	17
5e8a749c	18	#define CONFIG_SYS_TEXT_BASE 0x21f00000
b8d41dda RM	19
	20	/* ARM asynchronous clock */
	21	#define CONFIG_SYS_AT91_MAIN_CLOCK 18432000 /* External Crystal, in Hz */
	22	#define CONFIG_SYS_AT91_SLOW_CLOCK 32768
b8d41dda RM	23
	24	/* CPU */
	25	#define CONFIG_ARCH_CPU_INIT
b8d41dda RM	26
	27	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
	28	#define CONFIG_SETUP_MEMORY_TAGS
	29	#define CONFIG_INITRD_TAG
	30	#define CONFIG_SKIP_LOWLEVEL_INIT
b8d41dda RM	31
	32	/* SDRAM */
	33	#define CONFIG_NR_DRAM_BANKS 1
	34	#define CONFIG_SYS_SDRAM_BASE ATMEL_BASE_CS1
	35	#define CONFIG_SYS_SDRAM_SIZE (64 * 1024 * 1024) /* 64MB */
	36	#define CONFIG_SYS_INIT_SP_ADDR (ATMEL_BASE_SRAM1 + 0x1000 - \
	37	GENERATED_GBL_DATA_SIZE)
	38
	39	/* Mem test settings */
	40	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	41	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + (1024 * 1024))
	42
	43	/* NAND Flash */
	44	#define CONFIG_NAND_ATMEL
	45	#define CONFIG_SYS_NO_FLASH
	46	#define CONFIG_SYS_MAX_NAND_DEVICE 1
	47	#define CONFIG_SYS_NAND_BASE ATMEL_BASE_CS3
	48	#define CONFIG_SYS_NAND_DBW_8
	49	#define CONFIG_SYS_NAND_MASK_ALE (1 << 21) /* AD21 */
	50	#define CONFIG_SYS_NAND_MASK_CLE (1 << 22) /* AD22 */
	51	#define CONFIG_SYS_NAND_ENABLE_PIN AT91_PIN_PC14
	52	#define CONFIG_SYS_NAND_READY_PIN AT91_PIN_PC13
	53
	54	/* Ethernet */
	55	#define CONFIG_MACB
	56	#define CONFIG_RMII
b8d41dda RM	57	#define CONFIG_NET_RETRY_COUNT 20
b8d41dda RM	58	#define CONFIG_RESET_PHY_R
4535a24c	59	#define CONFIG_AT91_WANTS_COMMON_PHY
b8d41dda RM	60	#define CONFIG_TFTP_PORT
	61	#define CONFIG_TFTP_TSIZE
	62
	63	/* USB */
	64	#define CONFIG_USB_ATMEL
dcd2f1a0	65	#define CONFIG_USB_ATMEL_CLK_SEL_PLLB
b8d41dda	66	#define CONFIG_USB_OHCI_NEW
b8d41dda RM	67	#define CONFIG_SYS_USB_OHCI_CPU_INIT
	68	#define CONFIG_SYS_USB_OHCI_REGS_BASE ATMEL_UHP_BASE
	69	#define CONFIG_SYS_USB_OHCI_SLOT_NAME "at91sam9260"
	70	#define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 2
b8d41dda RM	71
b8d41dda RM	72	/* GPIOs and IO expander */
b8d41dda RM	73	#define CONFIG_ATMEL_LEGACY
	74	#define CONFIG_AT91_GPIO
	75	#define CONFIG_AT91_GPIO_PULLUP 1
	76	#define CONFIG_PCA953X
	77	#define CONFIG_SYS_I2C_PCA953X_ADDR 0x28
	78	#define CONFIG_SYS_I2C_PCA953X_WIDTH { {0x28, 16} }
	79
	80	/* UARTs/Serial console */
	81	#define CONFIG_ATMEL_USART
1a1927f3	82	#ifndef CONFIG_DM_SERIAL
b8d41dda RM	83	#define CONFIG_USART_BASE ATMEL_BASE_DBGU
b8d41dda RM	84	#define CONFIG_USART_ID ATMEL_ID_SYS
1a1927f3	85	#endif
b8d41dda	86	#define CONFIG_BAUDRATE 115200
b8d41dda RM	87
b8d41dda RM	88	/* I2C - Bit-bashed */
ea818dbb HS	89	#define CONFIG_SYS_I2C
	90	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	91	#define CONFIG_SYS_I2C_SOFT_SPEED 100000
	92	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
b8d41dda	93	#define CONFIG_SOFT_I2C_READ_REPEATED_START
b8d41dda RM	94	#define I2C_INIT do { \
	95	at91_set_gpio_output(AT91_PIN_PA23, 1); \
	96	at91_set_gpio_output(AT91_PIN_PA24, 1); \
	97	at91_set_pio_multi_drive(AT91_PIO_PORTA, 23, 1); \
	98	at91_set_pio_multi_drive(AT91_PIO_PORTA, 24, 1); \
	99	} while (0)
	100	#define I2C_SOFT_DECLARATIONS
	101	#define I2C_ACTIVE
	102	#define I2C_TRISTATE at91_set_gpio_input(AT91_PIN_PA23, 1);
	103	#define I2C_READ at91_get_gpio_value(AT91_PIN_PA23);
	104	#define I2C_SDA(bit) do { \
	105	if (bit) { \
	106	at91_set_gpio_input(AT91_PIN_PA23, 1); \
	107	} else { \
	108	at91_set_gpio_output(AT91_PIN_PA23, 1); \
	109	at91_set_gpio_value(AT91_PIN_PA23, bit); \
	110	} \
	111	} while (0)
	112	#define I2C_SCL(bit) at91_set_pio_value(AT91_PIO_PORTA, 24, bit)
	113	#define I2C_DELAY udelay(2)
	114
	115	/* Boot options */
	116	#define CONFIG_SYS_LOAD_ADDR 0x23000000
b8d41dda RM	117
	118	#define CONFIG_BOOTP_BOOTFILESIZE
	119	#define CONFIG_BOOTP_BOOTPATH
	120	#define CONFIG_BOOTP_GATEWAY
	121	#define CONFIG_BOOTP_HOSTNAME
	122
	123	/* Environment settings */
	124	#define CONFIG_ENV_IS_IN_NAND
	125	#define CONFIG_ENV_OFFSET (512 << 10)
	126	#define CONFIG_ENV_SIZE (256 << 10)
	127	#define CONFIG_ENV_OVERWRITE
	128	#define CONFIG_BOOTARGS "console=ttyS0,115200 ip=any"
	129
	130	/* Console settings */
	131	#define CONFIG_SYS_CBSIZE 256
	132	#define CONFIG_SYS_MAXARGS 16
	133	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	134	sizeof(CONFIG_SYS_PROMPT) + 16)
	135	#define CONFIG_SYS_LONGHELP
b8d41dda RM	136	#define CONFIG_CMDLINE_EDITING
b8d41dda RM	137	#define CONFIG_AUTO_COMPLETE
b8d41dda RM	138
	139	/* U-Boot memory settings */
	140	#define CONFIG_SYS_MALLOC_LEN (1 << 20)
b8d41dda RM	141
b8d41dda RM	142	/* Command line configuration */
b8d41dda RM	143	#define CONFIG_CMD_NAND
	144	#define CONFIG_CMD_PCA953X
	145	#define CONFIG_CMD_PCA953X_INFO
	146
	147	#endif /* __CONFIG_H */