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c115a0d4 MV |
1 | /* |
2 | * Copyright (C) 2014 Marek Vasut <marex@denx.de> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | #ifndef __CONFIG_SOCFPGA_ARRIA5_H__ | |
7 | #define __CONFIG_SOCFPGA_ARRIA5_H__ | |
8 | ||
9 | #include <asm/arch/socfpga_base_addrs.h> | |
10 | #include "../../board/altera/socfpga/pinmux_config.h" | |
11 | #include "../../board/altera/socfpga/iocsr_config.h" | |
12 | #include "../../board/altera/socfpga/pll_config.h" | |
13 | ||
14 | /* U-Boot Commands */ | |
15 | #define CONFIG_SYS_NO_FLASH | |
16 | #include <config_cmd_default.h> | |
17 | #define CONFIG_DOS_PARTITION | |
18 | #define CONFIG_FAT_WRITE | |
19 | #define CONFIG_HW_WATCHDOG | |
20 | ||
21 | #define CONFIG_CMD_ASKENV | |
22 | #define CONFIG_CMD_BOOTZ | |
23 | #define CONFIG_CMD_CACHE | |
24 | #define CONFIG_CMD_DFU | |
25 | #define CONFIG_CMD_DHCP | |
26 | #define CONFIG_CMD_EXT4 | |
27 | #define CONFIG_CMD_EXT4_WRITE | |
28 | #define CONFIG_CMD_FAT | |
29 | #define CONFIG_CMD_FPGA | |
30 | #define CONFIG_CMD_FS_GENERIC | |
31 | #define CONFIG_CMD_GREPENV | |
32 | #define CONFIG_CMD_MII | |
33 | #define CONFIG_CMD_MMC | |
34 | #define CONFIG_CMD_NET | |
35 | #define CONFIG_CMD_PING | |
36 | #define CONFIG_CMD_SETEXPR | |
37 | #define CONFIG_CMD_USB | |
38 | #define CONFIG_CMD_USB_MASS_STORAGE | |
39 | ||
c115a0d4 MV |
40 | |
41 | /* Memory configurations */ | |
42 | #define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */ | |
43 | ||
44 | /* Booting Linux */ | |
45 | #define CONFIG_BOOTDELAY 3 | |
46 | #define CONFIG_BOOTFILE "zImage" | |
47 | #define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE) | |
48 | #ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET | |
49 | #define CONFIG_BOOTCOMMAND "run ramboot" | |
50 | #else | |
51 | #define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot" | |
52 | #endif | |
53 | #define CONFIG_LOADADDR 0x8000 | |
54 | #define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR | |
55 | ||
56 | /* Ethernet on SoC (EMAC) */ | |
57 | #if defined(CONFIG_CMD_NET) | |
58 | #define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS | |
59 | #define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII | |
60 | ||
61 | /* PHY */ | |
62 | #define CONFIG_PHY_MICREL | |
63 | #define CONFIG_PHY_MICREL_KSZ9021 | |
64 | #define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew" | |
65 | #define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0 | |
66 | #define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew" | |
67 | #define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0 | |
68 | ||
69 | #endif | |
70 | ||
71 | /* USB */ | |
72 | #ifdef CONFIG_CMD_USB | |
73 | #define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS | |
74 | #endif | |
75 | #define CONFIG_G_DNL_MANUFACTURER "Altera" | |
76 | ||
77 | /* Extra Environment */ | |
78 | #define CONFIG_HOSTNAME socfpga_arria5 | |
79 | ||
80 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
81 | "verify=n\0" \ | |
82 | "loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \ | |
83 | "ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \ | |
84 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | |
85 | "bootimage=zImage\0" \ | |
86 | "fdt_addr=100\0" \ | |
87 | "fdtimage=socfpga.dtb\0" \ | |
88 | "fsloadcmd=ext2load\0" \ | |
89 | "bootm ${loadaddr} - ${fdt_addr}\0" \ | |
90 | "mmcroot=/dev/mmcblk0p2\0" \ | |
91 | "mmcboot=setenv bootargs " CONFIG_BOOTARGS \ | |
92 | " root=${mmcroot} rw rootwait;" \ | |
93 | "bootz ${loadaddr} - ${fdt_addr}\0" \ | |
94 | "mmcload=mmc rescan;" \ | |
95 | "load mmc 0:1 ${loadaddr} ${bootimage};" \ | |
96 | "load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \ | |
97 | "qspiroot=/dev/mtdblock0\0" \ | |
98 | "qspirootfstype=jffs2\0" \ | |
99 | "qspiboot=setenv bootargs " CONFIG_BOOTARGS \ | |
100 | " root=${qspiroot} rw rootfstype=${qspirootfstype};"\ | |
101 | "bootm ${loadaddr} - ${fdt_addr}\0" | |
102 | ||
103 | /* The rest of the configuration is shared */ | |
104 | #include <configs/socfpga_common.h> | |
105 | ||
106 | #endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */ |