[thirdparty/u-boot.git] / include / configs / socfpga_arria5.h

/*
 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
#define __CONFIG_SOCFPGA_ARRIA5_H__

#include <asm/arch/socfpga_base_addrs.h>
#include "../../board/altera/socfpga/pinmux_config.h"
#include "../../board/altera/socfpga/iocsr_config.h"
#include "../../board/altera/socfpga/pll_config.h"

/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DFU
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_USB_MASS_STORAGE


/* Memory configurations */
#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */

/* Booting Linux */
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTFILE		"zImage"
#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND	"run ramboot"
#else
#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
#endif
#define CONFIG_LOADADDR		0x8000
#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR

/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)
#define CONFIG_EMAC_BASE		SOCFPGA_EMAC1_ADDRESS
#define CONFIG_PHY_INTERFACE_MODE	PHY_INTERFACE_MODE_RGMII

/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0

#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER      "Altera"

/* Extra Environment */
#define CONFIG_HOSTNAME		socfpga_arria5

#define CONFIG_EXTRA_ENV_SETTINGS \
	"verify=n\0" \
	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
		"bootm ${loadaddr} - ${fdt_addr}\0" \
	"bootimage=zImage\0" \
	"fdt_addr=100\0" \
	"fdtimage=socfpga.dtb\0" \
		"fsloadcmd=ext2load\0" \
	"bootm ${loadaddr} - ${fdt_addr}\0" \
	"mmcroot=/dev/mmcblk0p2\0" \
	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
		" root=${mmcroot} rw rootwait;" \
		"bootz ${loadaddr} - ${fdt_addr}\0" \
	"mmcload=mmc rescan;" \
		"load mmc 0:1 ${loadaddr} ${bootimage};" \
		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
	"qspiroot=/dev/mtdblock0\0" \
	"qspirootfstype=jffs2\0" \
	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
		"bootm ${loadaddr} - ${fdt_addr}\0"

/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

#endif	/* __CONFIG_SOCFPGA_ARRIA5_H__ */
Commit	Line	Data
c115a0d4 MV	1	/*
	2	* Copyright (C) 2014 Marek Vasut <marex@denx.de>
	3	*
	4	* SPDX-License-Identifier: GPL-2.0+
	5	*/
	6	#ifndef __CONFIG_SOCFPGA_ARRIA5_H__
	7	#define __CONFIG_SOCFPGA_ARRIA5_H__
	8
	9	#include <asm/arch/socfpga_base_addrs.h>
	10	#include "../../board/altera/socfpga/pinmux_config.h"
	11	#include "../../board/altera/socfpga/iocsr_config.h"
	12	#include "../../board/altera/socfpga/pll_config.h"
	13
	14	/* U-Boot Commands */
	15	#define CONFIG_SYS_NO_FLASH
c115a0d4 MV	16	#define CONFIG_DOS_PARTITION
	17	#define CONFIG_FAT_WRITE
	18	#define CONFIG_HW_WATCHDOG
	19
	20	#define CONFIG_CMD_ASKENV
	21	#define CONFIG_CMD_BOOTZ
	22	#define CONFIG_CMD_CACHE
	23	#define CONFIG_CMD_DFU
	24	#define CONFIG_CMD_DHCP
	25	#define CONFIG_CMD_EXT4
	26	#define CONFIG_CMD_EXT4_WRITE
	27	#define CONFIG_CMD_FAT
c115a0d4 MV	28	#define CONFIG_CMD_FS_GENERIC
	29	#define CONFIG_CMD_GREPENV
	30	#define CONFIG_CMD_MII
	31	#define CONFIG_CMD_MMC
c115a0d4	32	#define CONFIG_CMD_PING
c115a0d4 MV	33	#define CONFIG_CMD_USB
	34	#define CONFIG_CMD_USB_MASS_STORAGE
	35
c115a0d4 MV	36
	37	/* Memory configurations */
	38	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
	39
	40	/* Booting Linux */
	41	#define CONFIG_BOOTDELAY 3
	42	#define CONFIG_BOOTFILE "zImage"
	43	#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
	44	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
	45	#define CONFIG_BOOTCOMMAND "run ramboot"
	46	#else
	47	#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
	48	#endif
	49	#define CONFIG_LOADADDR 0x8000
	50	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
	51
	52	/* Ethernet on SoC (EMAC) */
	53	#if defined(CONFIG_CMD_NET)
	54	#define CONFIG_EMAC_BASE SOCFPGA_EMAC1_ADDRESS
	55	#define CONFIG_PHY_INTERFACE_MODE PHY_INTERFACE_MODE_RGMII
	56
	57	/* PHY */
	58	#define CONFIG_PHY_MICREL
	59	#define CONFIG_PHY_MICREL_KSZ9021
	60	#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
	61	#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
	62	#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
	63	#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
	64
	65	#endif
	66
	67	/* USB */
	68	#ifdef CONFIG_CMD_USB
	69	#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
	70	#endif
	71	#define CONFIG_G_DNL_MANUFACTURER "Altera"
	72
	73	/* Extra Environment */
	74	#define CONFIG_HOSTNAME socfpga_arria5
	75
	76	#define CONFIG_EXTRA_ENV_SETTINGS \
	77	"verify=n\0" \
	78	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	79	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
	80	"bootm ${loadaddr} - ${fdt_addr}\0" \
	81	"bootimage=zImage\0" \
	82	"fdt_addr=100\0" \
	83	"fdtimage=socfpga.dtb\0" \
	84	"fsloadcmd=ext2load\0" \
	85	"bootm ${loadaddr} - ${fdt_addr}\0" \
	86	"mmcroot=/dev/mmcblk0p2\0" \
	87	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
	88	" root=${mmcroot} rw rootwait;" \
	89	"bootz ${loadaddr} - ${fdt_addr}\0" \
	90	"mmcload=mmc rescan;" \
	91	"load mmc 0:1 ${loadaddr} ${bootimage};" \
	92	"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
	93	"qspiroot=/dev/mtdblock0\0" \
	94	"qspirootfstype=jffs2\0" \
	95	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
	96	" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
	97	"bootm ${loadaddr} - ${fdt_addr}\0"
	98
	99	/* The rest of the configuration is shared */
100	#include <configs/socfpga_common.h>
101
102	#endif /* __CONFIG_SOCFPGA_ARRIA5_H__ */