[thirdparty/u-boot.git] / include / configs / socfpga_common.h

/* SPDX-License-Identifier: GPL-2.0+ */
/*
 * Copyright (C) 2012 Altera Corporation <www.altera.com>
 */
#ifndef __CONFIG_SOCFPGA_COMMON_H__
#define __CONFIG_SOCFPGA_COMMON_H__

/*
 * High level configuration
 */
#define CONFIG_CLOCKS

#define CONFIG_SYS_BOOTMAPSZ		(64 * 1024 * 1024)

#define CONFIG_TIMESTAMP		/* Print image info with timestamp */

/* add target to build it automatically upon "make" */
#define CONFIG_BUILD_TARGET		"u-boot-with-spl.sfp"

/*
 * Memory configurations
 */
#define PHYS_SDRAM_1			0x0
#define CONFIG_SYS_MALLOC_LEN		(64 * 1024 * 1024)
#define CONFIG_SYS_MEMTEST_START	PHYS_SDRAM_1
#define CONFIG_SYS_MEMTEST_END		PHYS_SDRAM_1_SIZE
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFFF0000
#define CONFIG_SYS_INIT_RAM_SIZE	0x10000
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SYS_INIT_RAM_ADDR	0xFFE00000
#define CONFIG_SYS_INIT_RAM_SIZE	0x40000 /* 256KB */
#endif
#define CONFIG_SYS_INIT_SP_ADDR			\
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)

#define CONFIG_SYS_SDRAM_BASE		PHYS_SDRAM_1

/*
 * U-Boot general configurations
 */
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O buffer size */
						/* Print buffer size */
#define CONFIG_SYS_MAXARGS	32		/* Max number of command args */
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE
						/* Boot argument buffer size */

#ifndef CONFIG_SYS_HOSTNAME
#define CONFIG_SYS_HOSTNAME	CONFIG_SYS_BOARD
#endif

/*
 * Cache
 */
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE		SOCFPGA_MPUL2_ADDRESS

/*
 * EPCS/EPCQx1 Serial Flash Controller
 */
#ifdef CONFIG_ALTERA_SPI
#define CONFIG_SF_DEFAULT_SPEED		30000000
/*
 * The base address is configurable in QSys, each board must specify the
 * base address based on it's particular FPGA configuration. Please note
 * that the address here is incremented by  0x400  from the Base address
 * selected in QSys, since the SPI registers are at offset +0x400.
 * #define CONFIG_SYS_SPI_BASE		0xff240400
 */
#endif

/*
 * Ethernet on SoC (EMAC)
 */
#ifdef CONFIG_CMD_NET
#define CONFIG_DW_ALTDESCRIPTOR
#endif

/*
 * FPGA Driver
 */
#ifdef CONFIG_CMD_FPGA
#define CONFIG_FPGA_COUNT		1
#endif

/*
 * L4 OSC1 Timer 0
 */
/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
#define CONFIG_SYS_TIMERBASE		SOCFPGA_OSC1TIMER0_ADDRESS
#define CONFIG_SYS_TIMER_COUNTS_DOWN
#define CONFIG_SYS_TIMER_COUNTER	(CONFIG_SYS_TIMERBASE + 0x4)
#define CONFIG_SYS_TIMER_RATE		25000000

/*
 * L4 Watchdog
 */
#ifdef CONFIG_HW_WATCHDOG
#define CONFIG_DESIGNWARE_WATCHDOG
#define CONFIG_DW_WDT_BASE		SOCFPGA_L4WD0_ADDRESS
#define CONFIG_DW_WDT_CLOCK_KHZ		25000
#define CONFIG_WATCHDOG_TIMEOUT_MSECS	30000
#endif

/*
 * MMC Driver
 */
#ifdef CONFIG_CMD_MMC
#define CONFIG_BOUNCE_BUFFER
/* FIXME */
/* using smaller max blk cnt to avoid flooding the limited stack we have */
#define CONFIG_SYS_MMC_MAX_BLK_COUNT	256	/* FIXME -- SPL only? */
#endif

/*
 * NAND Support
 */
#ifdef CONFIG_NAND_DENALI
#define CONFIG_SYS_MAX_NAND_DEVICE	1
#define CONFIG_SYS_NAND_ONFI_DETECTION
#define CONFIG_SYS_NAND_REGS_BASE	SOCFPGA_NANDREGS_ADDRESS
#define CONFIG_SYS_NAND_DATA_BASE	SOCFPGA_NANDDATA_ADDRESS
#endif

/*
 * I2C support
 */
#ifndef CONFIG_DM_I2C
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_BASE		SOCFPGA_I2C0_ADDRESS
#define CONFIG_SYS_I2C_BASE1		SOCFPGA_I2C1_ADDRESS
#define CONFIG_SYS_I2C_BASE2		SOCFPGA_I2C2_ADDRESS
#define CONFIG_SYS_I2C_BASE3		SOCFPGA_I2C3_ADDRESS
/* Using standard mode which the speed up to 100Kb/s */
#define CONFIG_SYS_I2C_SPEED		100000
#define CONFIG_SYS_I2C_SPEED1		100000
#define CONFIG_SYS_I2C_SPEED2		100000
#define CONFIG_SYS_I2C_SPEED3		100000
/* Address of device when used as slave */
#define CONFIG_SYS_I2C_SLAVE		0x02
#define CONFIG_SYS_I2C_SLAVE1		0x02
#define CONFIG_SYS_I2C_SLAVE2		0x02
#define CONFIG_SYS_I2C_SLAVE3		0x02
#ifndef __ASSEMBLY__
/* Clock supplied to I2C controller in unit of MHz */
unsigned int cm_get_l4_sp_clk_hz(void);
#define IC_CLK				(cm_get_l4_sp_clk_hz() / 1000000)
#endif
#endif /* CONFIG_DM_I2C */

/*
 * QSPI support
 */
/* Enable multiple SPI NOR flash manufacturers */
#ifndef CONFIG_SPL_BUILD
#define CONFIG_SPI_FLASH_MTD
#endif
/* QSPI reference clock */
#ifndef __ASSEMBLY__
unsigned int cm_get_qspi_controller_clk_hz(void);
#define CONFIG_CQSPI_REF_CLK		cm_get_qspi_controller_clk_hz()
#endif

/*
 * Designware SPI support
 */

/*
 * Serial Driver
 */
#define CONFIG_SYS_NS16550_SERIAL

/*
 * USB
 */

/*
 * USB Gadget (DFU, UMS)
 */
#if defined(CONFIG_CMD_DFU) || defined(CONFIG_CMD_USB_MASS_STORAGE)
#define CONFIG_SYS_DFU_DATA_BUF_SIZE	(16 * 1024 * 1024)
#define DFU_DEFAULT_POLL_TIMEOUT	300

/* USB IDs */
#define CONFIG_G_DNL_UMS_VENDOR_NUM	0x0525
#define CONFIG_G_DNL_UMS_PRODUCT_NUM	0xA4A5
#endif

/*
 * U-Boot environment
 */
#if !defined(CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE			(8 * 1024)
#endif

/* Environment for SDMMC boot */
#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_SYS_MMC_ENV_DEV		0 /* device 0 */
#define CONFIG_ENV_OFFSET		(34 * 512) /* just after the GPT */
#endif

/* Environment for QSPI boot */
#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
#define CONFIG_ENV_OFFSET		0x00100000
#define CONFIG_ENV_SECT_SIZE		(64 * 1024)
#endif

/*
 * mtd partitioning for serial NOR flash
 *
 * device nor0 <ff705000.spi.0>, # parts = 6
 * #: name                size            offset          mask_flags
 * 0: u-boot              0x00100000      0x00000000      0
 * 1: env1                0x00040000      0x00100000      0
 * 2: env2                0x00040000      0x00140000      0
 * 3: UBI                 0x03e80000      0x00180000      0
 * 4: boot                0x00e80000      0x00180000      0
 * 5: rootfs              0x01000000      0x01000000      0
 *
 */

/*
 * SPL
 *
 * SRAM Memory layout for gen 5:
 *
 * 0xFFFF_0000 ...... Start of SRAM
 * 0xFFFF_xxxx ...... Top of stack (grows down)
 * 0xFFFF_yyyy ...... Malloc area
 * 0xFFFF_zzzz ...... Global Data
 * 0xFFFF_FF00 ...... End of SRAM
 *
 * SRAM Memory layout for Arria 10:
 * 0xFFE0_0000 ...... Start of SRAM (bottom)
 * 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
 * 0xFFEy_yyyy ...... Global Data
 * 0xFFEz_zzzz ...... Malloc area (grows up to top)
 * 0xFFE3_FFFF ...... End of SRAM (top)
 */
#define CONFIG_SPL_TEXT_BASE		CONFIG_SYS_INIT_RAM_ADDR
#define CONFIG_SPL_MAX_SIZE		CONFIG_SYS_INIT_RAM_SIZE

#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
/* SPL memory allocation configuration, this is for FAT implementation */
#ifndef CONFIG_SYS_SPL_MALLOC_START
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
#define CONFIG_SYS_SPL_MALLOC_START	(CONFIG_SYS_INIT_RAM_SIZE - \
					 CONFIG_SYS_SPL_MALLOC_SIZE + \
					 CONFIG_SYS_INIT_RAM_ADDR)
#endif
#endif

/* SPL SDMMC boot support */
#ifdef CONFIG_SPL_MMC_SUPPORT
#if defined(CONFIG_SPL_FAT_SUPPORT) || defined(CONFIG_SPL_EXT_SUPPORT)
#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME		"u-boot-dtb.img"
#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION	1
#endif
#else
#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION	1
#endif
#endif

/* SPL QSPI boot support */
#ifdef CONFIG_SPL_SPI_SUPPORT
#define CONFIG_SYS_SPI_U_BOOT_OFFS	0x40000
#endif

/* SPL NAND boot support */
#ifdef CONFIG_SPL_NAND_SUPPORT
#define CONFIG_SYS_NAND_BAD_BLOCK_POS	0
#define CONFIG_SYS_NAND_U_BOOT_OFFS	0x40000
#endif

/*
 * Stack setup
 */
#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
#define CONFIG_SPL_STACK		CONFIG_SYS_INIT_SP_ADDR
#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
#define CONFIG_SPL_STACK		CONFIG_SYS_SPL_MALLOC_START
#endif

/* Extra Environment */
#ifndef CONFIG_SPL_BUILD

#ifdef CONFIG_CMD_DHCP
#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
#else
#define BOOT_TARGET_DEVICES_DHCP(func)
#endif

#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
#else
#define BOOT_TARGET_DEVICES_PXE(func)
#endif

#ifdef CONFIG_CMD_MMC
#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
#else
#define BOOT_TARGET_DEVICES_MMC(func)
#endif

#define BOOT_TARGET_DEVICES(func) \
	BOOT_TARGET_DEVICES_MMC(func) \
	BOOT_TARGET_DEVICES_PXE(func) \
	BOOT_TARGET_DEVICES_DHCP(func)

#include <config_distro_bootcmd.h>

#ifndef CONFIG_EXTRA_ENV_SETTINGS
#define CONFIG_EXTRA_ENV_SETTINGS \
	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	"bootm_size=0xa000000\0" \
	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	"fdt_addr_r=0x02000000\0" \
	"scriptaddr=0x02100000\0" \
	"pxefile_addr_r=0x02200000\0" \
	"ramdisk_addr_r=0x02300000\0" \
	BOOTENV

#endif
#endif

#endif	/* __CONFIG_SOCFPGA_COMMON_H__ */
Commit	Line	Data
83d290c5	1	/* SPDX-License-Identifier: GPL-2.0+ */
5095ee08 PM	2	/*
5095ee08 PM	3	* Copyright (C) 2012 Altera Corporation <www.altera.com>
5095ee08	4	*/
48275c96 DN	5	#ifndef __CONFIG_SOCFPGA_COMMON_H__
48275c96 DN	6	#define __CONFIG_SOCFPGA_COMMON_H__
5095ee08	7
5095ee08 PM	8	/*
	9	* High level configuration
	10	*/
5095ee08 PM	11	#define CONFIG_CLOCKS
5095ee08 PM	12
5095ee08 PM	13	#define CONFIG_SYS_BOOTMAPSZ (64 * 1024 * 1024)
	14
	15	#define CONFIG_TIMESTAMP /* Print image info with timestamp */
	16
dc0a1a08 MV	17	/* add target to build it automatically upon "make" */
	18	#define CONFIG_BUILD_TARGET "u-boot-with-spl.sfp"
	19
5095ee08 PM	20	/*
	21	* Memory configurations
	22	*/
5095ee08	23	#define PHYS_SDRAM_1 0x0
0223a95c	24	#define CONFIG_SYS_MALLOC_LEN (64 * 1024 * 1024)
5095ee08 PM	25	#define CONFIG_SYS_MEMTEST_START PHYS_SDRAM_1
5095ee08 PM	26	#define CONFIG_SYS_MEMTEST_END PHYS_SDRAM_1_SIZE
1b259403	27	#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
5095ee08	28	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFFF0000
7599b53d	29	#define CONFIG_SYS_INIT_RAM_SIZE 0x10000
1b259403 LFT	30	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	31	#define CONFIG_SYS_INIT_RAM_ADDR 0xFFE00000
	32	#define CONFIG_SYS_INIT_RAM_SIZE 0x40000 /* 256KB */
	33	#endif
7599b53d	34	#define CONFIG_SYS_INIT_SP_ADDR \
768f23dc	35	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_RAM_SIZE)
5095ee08 PM	36
5095ee08 PM	37	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
5095ee08 PM	38
	39	/*
	40	* U-Boot general configurations
	41	*/
5095ee08	42	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O buffer size */
5095ee08 PM	43	/* Print buffer size */
	44	#define CONFIG_SYS_MAXARGS 32 /* Max number of command args */
	45	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	46	/* Boot argument buffer size */
5095ee08	47
ea082346 MV	48	#ifndef CONFIG_SYS_HOSTNAME
	49	#define CONFIG_SYS_HOSTNAME CONFIG_SYS_BOARD
	50	#endif
	51
5095ee08 PM	52	/*
	53	* Cache
	54	*/
5095ee08 PM	55	#define CONFIG_SYS_L2_PL310
	56	#define CONFIG_SYS_PL310_BASE SOCFPGA_MPUL2_ADDRESS
	57
8a78ca9e MV	58	/*
	59	* EPCS/EPCQx1 Serial Flash Controller
	60	*/
	61	#ifdef CONFIG_ALTERA_SPI
8a78ca9e	62	#define CONFIG_SF_DEFAULT_SPEED 30000000
8a78ca9e MV	63	/*
	64	* The base address is configurable in QSys, each board must specify the
	65	* base address based on it's particular FPGA configuration. Please note
	66	* that the address here is incremented by 0x400 from the Base address
	67	* selected in QSys, since the SPI registers are at offset +0x400.
	68	* #define CONFIG_SYS_SPI_BASE 0xff240400
	69	*/
	70	#endif
	71
5095ee08 PM	72	/*
	73	* Ethernet on SoC (EMAC)
	74	*/
f7917328	75	#ifdef CONFIG_CMD_NET
5095ee08	76	#define CONFIG_DW_ALTDESCRIPTOR
5095ee08 PM	77	#endif
	78
	79	/*
	80	* FPGA Driver
	81	*/
	82	#ifdef CONFIG_CMD_FPGA
5095ee08 PM	83	#define CONFIG_FPGA_COUNT 1
5095ee08 PM	84	#endif
9af91b7c	85
5095ee08 PM	86	/*
	87	* L4 OSC1 Timer 0
	88	*/
	89	/* This timer uses eosc1, whose clock frequency is fixed at any condition. */
	90	#define CONFIG_SYS_TIMERBASE SOCFPGA_OSC1TIMER0_ADDRESS
	91	#define CONFIG_SYS_TIMER_COUNTS_DOWN
	92	#define CONFIG_SYS_TIMER_COUNTER (CONFIG_SYS_TIMERBASE + 0x4)
5095ee08	93	#define CONFIG_SYS_TIMER_RATE 25000000
5095ee08 PM	94
	95	/*
	96	* L4 Watchdog
	97	*/
	98	#ifdef CONFIG_HW_WATCHDOG
	99	#define CONFIG_DESIGNWARE_WATCHDOG
	100	#define CONFIG_DW_WDT_BASE SOCFPGA_L4WD0_ADDRESS
	101	#define CONFIG_DW_WDT_CLOCK_KHZ 25000
ea926511	102	#define CONFIG_WATCHDOG_TIMEOUT_MSECS 30000
5095ee08 PM	103	#endif
	104
	105	/*
	106	* MMC Driver
	107	*/
	108	#ifdef CONFIG_CMD_MMC
5095ee08	109	#define CONFIG_BOUNCE_BUFFER
5095ee08 PM	110	/* FIXME */
	111	/* using smaller max blk cnt to avoid flooding the limited stack we have */
	112	#define CONFIG_SYS_MMC_MAX_BLK_COUNT 256 /* FIXME -- SPL only? */
	113	#endif
	114
c339ea5b MV	115	/*
	116	* NAND Support
	117	*/
	118	#ifdef CONFIG_NAND_DENALI
	119	#define CONFIG_SYS_MAX_NAND_DEVICE 1
c339ea5b	120	#define CONFIG_SYS_NAND_ONFI_DETECTION
c339ea5b MV	121	#define CONFIG_SYS_NAND_REGS_BASE SOCFPGA_NANDREGS_ADDRESS
c339ea5b MV	122	#define CONFIG_SYS_NAND_DATA_BASE SOCFPGA_NANDDATA_ADDRESS
c339ea5b MV	123	#endif
c339ea5b MV	124
7fb0f596	125	/*
ebcaf966 SR	126	* I2C support
ebcaf966 SR	127	*/
2878942a	128	#ifndef CONFIG_DM_I2C
ebcaf966	129	#define CONFIG_SYS_I2C
ebcaf966 SR	130	#define CONFIG_SYS_I2C_BASE SOCFPGA_I2C0_ADDRESS
	131	#define CONFIG_SYS_I2C_BASE1 SOCFPGA_I2C1_ADDRESS
	132	#define CONFIG_SYS_I2C_BASE2 SOCFPGA_I2C2_ADDRESS
	133	#define CONFIG_SYS_I2C_BASE3 SOCFPGA_I2C3_ADDRESS
	134	/* Using standard mode which the speed up to 100Kb/s */
	135	#define CONFIG_SYS_I2C_SPEED 100000
	136	#define CONFIG_SYS_I2C_SPEED1 100000
	137	#define CONFIG_SYS_I2C_SPEED2 100000
	138	#define CONFIG_SYS_I2C_SPEED3 100000
	139	/* Address of device when used as slave */
	140	#define CONFIG_SYS_I2C_SLAVE 0x02
	141	#define CONFIG_SYS_I2C_SLAVE1 0x02
	142	#define CONFIG_SYS_I2C_SLAVE2 0x02
	143	#define CONFIG_SYS_I2C_SLAVE3 0x02
	144	#ifndef __ASSEMBLY__
	145	/* Clock supplied to I2C controller in unit of MHz */
	146	unsigned int cm_get_l4_sp_clk_hz(void);
	147	#define IC_CLK (cm_get_l4_sp_clk_hz() / 1000000)
	148	#endif
2878942a	149	#endif /* CONFIG_DM_I2C */
ebcaf966	150
7fb0f596 SR	151	/*
	152	* QSPI support
	153	*/
7fb0f596	154	/* Enable multiple SPI NOR flash manufacturers */
cbc9544d	155	#ifndef CONFIG_SPL_BUILD
7fb0f596	156	#define CONFIG_SPI_FLASH_MTD
cbc9544d	157	#endif
7fb0f596 SR	158	/* QSPI reference clock */
	159	#ifndef __ASSEMBLY__
	160	unsigned int cm_get_qspi_controller_clk_hz(void);
	161	#define CONFIG_CQSPI_REF_CLK cm_get_qspi_controller_clk_hz()
	162	#endif
7fb0f596	163
0c745d00 MV	164	/*
	165	* Designware SPI support
	166	*/
a6e73591	167
5095ee08 PM	168	/*
	169	* Serial Driver
	170	*/
5095ee08	171	#define CONFIG_SYS_NS16550_SERIAL
5095ee08	172
20cadbbe MV	173	/*
	174	* USB
	175	*/
20cadbbe	176
0223a95c MV	177	/*
	178	* USB Gadget (DFU, UMS)
	179	*/
	180	#if defined(CONFIG_CMD_DFU) \|\| defined(CONFIG_CMD_USB_MASS_STORAGE)
55ce55fa	181	#define CONFIG_SYS_DFU_DATA_BUF_SIZE (16 * 1024 * 1024)
0223a95c MV	182	#define DFU_DEFAULT_POLL_TIMEOUT 300
	183
	184	/* USB IDs */
e6c0bc06 SP	185	#define CONFIG_G_DNL_UMS_VENDOR_NUM 0x0525
e6c0bc06 SP	186	#define CONFIG_G_DNL_UMS_PRODUCT_NUM 0xA4A5
0223a95c MV	187	#endif
0223a95c MV	188
5095ee08 PM	189	/*
	190	* U-Boot environment
	191	*/
ead2fb29	192	#if !defined(CONFIG_ENV_SIZE)
451e8241	193	#define CONFIG_ENV_SIZE (8 * 1024)
ead2fb29	194	#endif
5095ee08	195
79cc48e7 CLS	196	/* Environment for SDMMC boot */
79cc48e7 CLS	197	#if defined(CONFIG_ENV_IS_IN_MMC) && !defined(CONFIG_ENV_OFFSET)
451e8241 DW	198	#define CONFIG_SYS_MMC_ENV_DEV 0 /* device 0 */
451e8241 DW	199	#define CONFIG_ENV_OFFSET (34 * 512) /* just after the GPT */
79cc48e7 CLS	200	#endif
79cc48e7 CLS	201
ec8b7528 CLS	202	/* Environment for QSPI boot */
	203	#if defined(CONFIG_ENV_IS_IN_SPI_FLASH) && !defined(CONFIG_ENV_OFFSET)
	204	#define CONFIG_ENV_OFFSET 0x00100000
	205	#define CONFIG_ENV_SECT_SIZE (64 * 1024)
	206	#endif
	207
55702fe2 CLS	208	/*
	209	* mtd partitioning for serial NOR flash
	210	*
	211	* device nor0 <ff705000.spi.0>, # parts = 6
	212	* #: name size offset mask_flags
	213	* 0: u-boot 0x00100000 0x00000000 0
	214	* 1: env1 0x00040000 0x00100000 0
	215	* 2: env2 0x00040000 0x00140000 0
	216	* 3: UBI 0x03e80000 0x00180000 0
	217	* 4: boot 0x00e80000 0x00180000 0
	218	* 5: rootfs 0x01000000 0x01000000 0
	219	*
	220	*/
55702fe2	221
5095ee08 PM	222	/*
5095ee08 PM	223	* SPL
34584d19	224	*
421a21c5	225	* SRAM Memory layout for gen 5:
34584d19 MV	226	*
	227	* 0xFFFF_0000 ...... Start of SRAM
	228	* 0xFFFF_xxxx ...... Top of stack (grows down)
	229	* 0xFFFF_yyyy ...... Malloc area
	230	* 0xFFFF_zzzz ...... Global Data
	231	* 0xFFFF_FF00 ...... End of SRAM
421a21c5 TFC	232	*
	233	* SRAM Memory layout for Arria 10:
	234	* 0xFFE0_0000 ...... Start of SRAM (bottom)
	235	* 0xFFEx_xxxx ...... Top of stack (grows down to bottom)
	236	* 0xFFEy_yyyy ...... Global Data
	237	* 0xFFEz_zzzz ...... Malloc area (grows up to top)
	238	* 0xFFE3_FFFF ...... End of SRAM (top)
5095ee08	239	*/
34584d19	240	#define CONFIG_SPL_TEXT_BASE CONFIG_SYS_INIT_RAM_ADDR
1b259403	241	#define CONFIG_SPL_MAX_SIZE CONFIG_SYS_INIT_RAM_SIZE
5095ee08	242
421a21c5 TFC	243	#if defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	244	/* SPL memory allocation configuration, this is for FAT implementation */
	245	#ifndef CONFIG_SYS_SPL_MALLOC_START
	246	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
	247	#define CONFIG_SYS_SPL_MALLOC_START (CONFIG_SYS_INIT_RAM_SIZE - \
	248	CONFIG_SYS_SPL_MALLOC_SIZE + \
	249	CONFIG_SYS_INIT_RAM_ADDR)
	250	#endif
	251	#endif
	252
d3f34e75 MV	253	/* SPL SDMMC boot support */
	254	#ifdef CONFIG_SPL_MMC_SUPPORT
	255	#if defined(CONFIG_SPL_FAT_SUPPORT) \|\| defined(CONFIG_SPL_EXT_SUPPORT)
d3f34e75	256	#define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot-dtb.img"
451e8241 DW	257	#define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1
	258	#endif
	259	#else
	260	#ifndef CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION
	261	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_PARTITION 1
d3f34e75 MV	262	#endif
d3f34e75 MV	263	#endif
5095ee08	264
346d6f56 MV	265	/* SPL QSPI boot support */
346d6f56 MV	266	#ifdef CONFIG_SPL_SPI_SUPPORT
346d6f56 MV	267	#define CONFIG_SYS_SPI_U_BOOT_OFFS 0x40000
	268	#endif
	269
c339ea5b MV	270	/* SPL NAND boot support */
c339ea5b MV	271	#ifdef CONFIG_SPL_NAND_SUPPORT
c339ea5b MV	272	#define CONFIG_SYS_NAND_BAD_BLOCK_POS 0
	273	#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x40000
	274	#endif
	275
a717b811 DN	276	/*
	277	* Stack setup
	278	*/
421a21c5	279	#if defined(CONFIG_TARGET_SOCFPGA_GEN5)
a717b811	280	#define CONFIG_SPL_STACK CONFIG_SYS_INIT_SP_ADDR
421a21c5 TFC	281	#elif defined(CONFIG_TARGET_SOCFPGA_ARRIA10)
	282	#define CONFIG_SPL_STACK CONFIG_SYS_SPL_MALLOC_START
	283	#endif
a717b811	284
451e8241 DW	285	/* Extra Environment */
451e8241 DW	286	#ifndef CONFIG_SPL_BUILD
451e8241	287
1c7fa793 SG	288	#ifdef CONFIG_CMD_DHCP
	289	#define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na)
	290	#else
	291	#define BOOT_TARGET_DEVICES_DHCP(func)
	292	#endif
	293
86271b3f	294	#if defined(CONFIG_CMD_PXE) && defined(CONFIG_CMD_DHCP)
451e8241 DW	295	#define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na)
	296	#else
	297	#define BOOT_TARGET_DEVICES_PXE(func)
	298	#endif
	299
	300	#ifdef CONFIG_CMD_MMC
	301	#define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0)
	302	#else
	303	#define BOOT_TARGET_DEVICES_MMC(func)
	304	#endif
	305
	306	#define BOOT_TARGET_DEVICES(func) \
	307	BOOT_TARGET_DEVICES_MMC(func) \
	308	BOOT_TARGET_DEVICES_PXE(func) \
1c7fa793	309	BOOT_TARGET_DEVICES_DHCP(func)
451e8241 DW	310
	311	#include <config_distro_bootcmd.h>
	312
	313	#ifndef CONFIG_EXTRA_ENV_SETTINGS
	314	#define CONFIG_EXTRA_ENV_SETTINGS \
	315	"fdtfile=" CONFIG_DEFAULT_FDT_FILE "\0" \
	316	"bootm_size=0xa000000\0" \
	317	"kernel_addr_r="__stringify(CONFIG_SYS_LOAD_ADDR)"\0" \
	318	"fdt_addr_r=0x02000000\0" \
	319	"scriptaddr=0x02100000\0" \
	320	"pxefile_addr_r=0x02200000\0" \
	321	"ramdisk_addr_r=0x02300000\0" \
	322	BOOTENV
	323
	324	#endif
	325	#endif
	326
48275c96	327	#endif /* __CONFIG_SOCFPGA_COMMON_H__ */