[people/ms/u-boot.git] / include / configs / socfpga_cyclone5.h

/*
 * Copyright (C) 2014 Marek Vasut <marex@denx.de>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */
#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
#define __CONFIG_SOCFPGA_CYCLONE5_H__

#include <asm/arch/socfpga_base_addrs.h>

/* U-Boot Commands */
#define CONFIG_SYS_NO_FLASH
#define CONFIG_DOS_PARTITION
#define CONFIG_FAT_WRITE
#define CONFIG_HW_WATCHDOG

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_BOOTZ
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_DFU
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EXT4
#define CONFIG_CMD_EXT4_WRITE
#define CONFIG_CMD_FAT
#define CONFIG_CMD_FS_GENERIC
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_GREPENV
#define CONFIG_CMD_MII
#define CONFIG_CMD_MMC
#define CONFIG_CMD_PING
#define CONFIG_CMD_USB
#define CONFIG_CMD_USB_MASS_STORAGE

/* Memory configurations */
#define PHYS_SDRAM_1_SIZE		0x40000000	/* 1GiB on SoCDK */

/* Booting Linux */
#define CONFIG_BOOTDELAY	3
#define CONFIG_BOOTFILE		"zImage"
#define CONFIG_BOOTARGS		"console=ttyS0," __stringify(CONFIG_BAUDRATE)
#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
#define CONFIG_BOOTCOMMAND	"run ramboot"
#else
#define CONFIG_BOOTCOMMAND	"run mmcload; run mmcboot"
#endif
#define CONFIG_LOADADDR		0x01000000
#define CONFIG_SYS_LOAD_ADDR	CONFIG_LOADADDR

/* Ethernet on SoC (EMAC) */
#if defined(CONFIG_CMD_NET)

/* PHY */
#define CONFIG_PHY_MICREL
#define CONFIG_PHY_MICREL_KSZ9021
#define CONFIG_KSZ9021_CLK_SKEW_ENV	"micrel-ksz9021-clk-skew"
#define CONFIG_KSZ9021_CLK_SKEW_VAL	0xf0f0
#define CONFIG_KSZ9021_DATA_SKEW_ENV	"micrel-ksz9021-data-skew"
#define CONFIG_KSZ9021_DATA_SKEW_VAL	0x0

#endif

/* USB */
#ifdef CONFIG_CMD_USB
#define CONFIG_USB_DWC2_REG_ADDR	SOCFPGA_USB1_ADDRESS
#endif
#define CONFIG_G_DNL_MANUFACTURER      "Altera"

/* Extra Environment */
#define CONFIG_HOSTNAME		socfpga_cyclone5

#define CONFIG_EXTRA_ENV_SETTINGS \
	"verify=n\0" \
	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
		"bootm ${loadaddr} - ${fdt_addr}\0" \
	"bootimage=zImage\0" \
	"fdt_addr=100\0" \
	"fdtimage=socfpga.dtb\0" \
		"fsloadcmd=ext2load\0" \
	"bootm ${loadaddr} - ${fdt_addr}\0" \
	"mmcroot=/dev/mmcblk0p2\0" \
	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
		" root=${mmcroot} rw rootwait;" \
		"bootz ${loadaddr} - ${fdt_addr}\0" \
	"mmcload=mmc rescan;" \
		"load mmc 0:1 ${loadaddr} ${bootimage};" \
		"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
	"qspiroot=/dev/mtdblock0\0" \
	"qspirootfstype=jffs2\0" \
	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
		" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
		"bootm ${loadaddr} - ${fdt_addr}\0"

/* The rest of the configuration is shared */
#include <configs/socfpga_common.h>

#endif	/* __CONFIG_SOCFPGA_CYCLONE5_H__ */
Commit	Line	Data
77754408	1	/*
5095ee08	2	* Copyright (C) 2014 Marek Vasut <marex@denx.de>
77754408	3	*
1a459660	4	* SPDX-License-Identifier: GPL-2.0+
77754408	5	*/
5095ee08 PM	6	#ifndef __CONFIG_SOCFPGA_CYCLONE5_H__
5095ee08 PM	7	#define __CONFIG_SOCFPGA_CYCLONE5_H__
77754408 DN	8
	9	#include <asm/arch/socfpga_base_addrs.h>
	10
47f9b4e1 MV	11	/* U-Boot Commands */
47f9b4e1 MV	12	#define CONFIG_SYS_NO_FLASH
47f9b4e1 MV	13	#define CONFIG_DOS_PARTITION
	14	#define CONFIG_FAT_WRITE
	15	#define CONFIG_HW_WATCHDOG
9ca2116c	16
47f9b4e1 MV	17	#define CONFIG_CMD_ASKENV
	18	#define CONFIG_CMD_BOOTZ
	19	#define CONFIG_CMD_CACHE
e5e87179	20	#define CONFIG_CMD_DFU
47f9b4e1 MV	21	#define CONFIG_CMD_DHCP
	22	#define CONFIG_CMD_EXT4
	23	#define CONFIG_CMD_EXT4_WRITE
	24	#define CONFIG_CMD_FAT
2f210639	25	#define CONFIG_CMD_FS_GENERIC
1bd57ff5	26	#define CONFIG_CMD_GPIO
47f9b4e1 MV	27	#define CONFIG_CMD_GREPENV
	28	#define CONFIG_CMD_MII
	29	#define CONFIG_CMD_MMC
47f9b4e1	30	#define CONFIG_CMD_PING
e5e87179 MV	31	#define CONFIG_CMD_USB
e5e87179 MV	32	#define CONFIG_CMD_USB_MASS_STORAGE
77754408	33
5095ee08	34	/* Memory configurations */
47f9b4e1	35	#define PHYS_SDRAM_1_SIZE 0x40000000 /* 1GiB on SoCDK */
77754408	36
47f9b4e1 MV	37	/* Booting Linux */
	38	#define CONFIG_BOOTDELAY 3
	39	#define CONFIG_BOOTFILE "zImage"
116f5d5b	40	#define CONFIG_BOOTARGS "console=ttyS0," __stringify(CONFIG_BAUDRATE)
97ce274d	41	#ifdef CONFIG_SOCFPGA_VIRTUAL_TARGET
47f9b4e1	42	#define CONFIG_BOOTCOMMAND "run ramboot"
97ce274d	43	#else
47f9b4e1	44	#define CONFIG_BOOTCOMMAND "run mmcload; run mmcboot"
97ce274d	45	#endif
4c6d8b91	46	#define CONFIG_LOADADDR 0x01000000
47f9b4e1	47	#define CONFIG_SYS_LOAD_ADDR CONFIG_LOADADDR
77754408	48
5095ee08 PM	49	/* Ethernet on SoC (EMAC) */
5095ee08 PM	50	#if defined(CONFIG_CMD_NET)
47f9b4e1 MV	51
47f9b4e1 MV	52	/* PHY */
47f9b4e1 MV	53	#define CONFIG_PHY_MICREL
	54	#define CONFIG_PHY_MICREL_KSZ9021
	55	#define CONFIG_KSZ9021_CLK_SKEW_ENV "micrel-ksz9021-clk-skew"
	56	#define CONFIG_KSZ9021_CLK_SKEW_VAL 0xf0f0
	57	#define CONFIG_KSZ9021_DATA_SKEW_ENV "micrel-ksz9021-data-skew"
	58	#define CONFIG_KSZ9021_DATA_SKEW_VAL 0x0
77754408	59
31ad864e	60	#endif
77754408	61
e5e87179 MV	62	/* USB */
	63	#ifdef CONFIG_CMD_USB
	64	#define CONFIG_USB_DWC2_REG_ADDR SOCFPGA_USB1_ADDRESS
	65	#endif
	66	#define CONFIG_G_DNL_MANUFACTURER "Altera"
	67
5095ee08 PM	68	/* Extra Environment */
5095ee08 PM	69	#define CONFIG_HOSTNAME socfpga_cyclone5
77754408	70
47f9b4e1 MV	71	#define CONFIG_EXTRA_ENV_SETTINGS \
	72	"verify=n\0" \
	73	"loadaddr= " __stringify(CONFIG_SYS_LOAD_ADDR) "\0" \
	74	"ramboot=setenv bootargs " CONFIG_BOOTARGS ";" \
	75	"bootm ${loadaddr} - ${fdt_addr}\0" \
	76	"bootimage=zImage\0" \
	77	"fdt_addr=100\0" \
	78	"fdtimage=socfpga.dtb\0" \
	79	"fsloadcmd=ext2load\0" \
	80	"bootm ${loadaddr} - ${fdt_addr}\0" \
	81	"mmcroot=/dev/mmcblk0p2\0" \
	82	"mmcboot=setenv bootargs " CONFIG_BOOTARGS \
	83	" root=${mmcroot} rw rootwait;" \
	84	"bootz ${loadaddr} - ${fdt_addr}\0" \
	85	"mmcload=mmc rescan;" \
2f210639 MV	86	"load mmc 0:1 ${loadaddr} ${bootimage};" \
2f210639 MV	87	"load mmc 0:1 ${fdt_addr} ${fdtimage}\0" \
47f9b4e1 MV	88	"qspiroot=/dev/mtdblock0\0" \
	89	"qspirootfstype=jffs2\0" \
	90	"qspiboot=setenv bootargs " CONFIG_BOOTARGS \
	91	" root=${qspiroot} rw rootfstype=${qspirootfstype};"\
	92	"bootm ${loadaddr} - ${fdt_addr}\0"
77754408	93
5095ee08 PM	94	/* The rest of the configuration is shared */
5095ee08 PM	95	#include <configs/socfpga_common.h>
05b884b5	96
5095ee08	97	#endif /* __CONFIG_SOCFPGA_CYCLONE5_H__ */