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5d108ac8 SP |
1 | /* |
2 | * (C) Copyright 2008 | |
3 | * Sergei Poselenov, Emcraft Systems, sposelenov@emcraft.com. | |
4 | * | |
5 | * Wolfgang Denk <wd@denx.de> | |
6 | * Copyright 2004 Freescale Semiconductor. | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* | |
30 | * Socrates | |
31 | */ | |
32 | ||
33 | #ifndef __CONFIG_H | |
34 | #define __CONFIG_H | |
35 | ||
36 | /* High Level Configuration Options */ | |
37 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
38 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
39 | #define CONFIG_MPC85xx 1 /* MPC8540/60/55/41 */ | |
40 | #define CONFIG_MPC8544 1 | |
41 | #define CONFIG_SOCRATES 1 | |
42 | ||
43 | #define CONFIG_PCI | |
44 | ||
45 | #define CONFIG_TSEC_ENET /* tsec ethernet support */ | |
46 | ||
47 | #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ | |
48 | ||
49 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ | |
50 | ||
51 | /* | |
52 | * Only possible on E500 Version 2 or newer cores. | |
53 | */ | |
54 | #define CONFIG_ENABLE_36BIT_PHYS 1 | |
55 | ||
56 | /* | |
57 | * sysclk for MPC85xx | |
58 | * | |
59 | * Two valid values are: | |
60 | * 33000000 | |
61 | * 66000000 | |
62 | * | |
63 | * Most PCI cards are still 33Mhz, so in the presence of PCI, 33MHz | |
64 | * is likely the desired value here, so that is now the default. | |
65 | * The board, however, can run at 66MHz. In any event, this value | |
66 | * must match the settings of some switches. Details can be found | |
67 | * in the README.mpc85xxads. | |
68 | */ | |
69 | ||
70 | #ifndef CONFIG_SYS_CLK_FREQ | |
71 | #define CONFIG_SYS_CLK_FREQ 66666666 | |
72 | #endif | |
73 | ||
74 | /* | |
75 | * These can be toggled for performance analysis, otherwise use default. | |
76 | */ | |
77 | #define CONFIG_L2_CACHE /* toggle L2 cache */ | |
78 | #define CONFIG_BTB /* toggle branch predition */ | |
79 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
80 | ||
81 | #define CFG_INIT_DBCR DBCR_IDM /* Enable Debug Exceptions */ | |
82 | ||
83 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
84 | #define CFG_MEMTEST_START 0x00000000 | |
85 | #define CFG_MEMTEST_END 0x10000000 | |
86 | ||
87 | /* | |
88 | * Base addresses -- Note these are effective addresses where the | |
89 | * actual resources get mapped (not physical addresses) | |
90 | */ | |
91 | #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ | |
92 | #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ | |
93 | #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ | |
94 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ | |
95 | ||
96 | /* | |
97 | * DDR Setup | |
98 | */ | |
99 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ | |
100 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE | |
101 | ||
102 | #define CONFIG_DDR_DEFAULT_CL 30 /* CAS latency 3 */ | |
103 | ||
104 | /* Hardcoded values, to use instead of SPD */ | |
105 | #define CFG_DDR_CS0_BNDS 0x0000000f | |
106 | #define CFG_DDR_CS0_CONFIG 0x80010102 | |
107 | #define CFG_DDR_TIMING_0 0x00260802 | |
108 | #define CFG_DDR_TIMING_1 0x3935D322 | |
109 | #define CFG_DDR_TIMING_2 0x14904CC8 | |
110 | #define CFG_DDR_MODE 0x00480432 | |
111 | #define CFG_DDR_INTERVAL 0x030C0100 | |
112 | #define CFG_DDR_CONFIG_2 0x04400000 | |
113 | #define CFG_DDR_CONFIG 0xC3008000 | |
114 | #define CFG_DDR_CLK_CONTROL 0x03800000 | |
115 | #define CFG_SDRAM_SIZE 256 /* in Megs */ | |
116 | ||
5d108ac8 SP |
117 | #define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for DDR setup*/ |
118 | #define SPD_EEPROM_ADDRESS 0x50 /* DDR DIMM */ | |
119 | #define MPC85xx_DDR_SDRAM_CLK_CNTL /* 85xx has clock control reg */ | |
5d108ac8 SP |
120 | |
121 | /* | |
122 | * Flash on the Local Bus | |
123 | */ | |
124 | /* | |
125 | * Flash on the LocalBus | |
126 | */ | |
127 | #define CFG_LBC_CACHE_BASE 0xf0000000 /* Localbus cacheable */ | |
128 | ||
129 | #define CFG_FLASH0 0xFE000000 | |
130 | #define CFG_FLASH1 0xFC000000 | |
131 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH1, CFG_FLASH0 } | |
132 | ||
133 | #define CFG_LBC_FLASH_BASE CFG_FLASH1 /* Localbus flash start */ | |
134 | #define CFG_FLASH_BASE CFG_LBC_FLASH_BASE /* start of FLASH */ | |
135 | ||
136 | #define CFG_BR0_PRELIM 0xfe001001 /* port size 16bit */ | |
137 | #define CFG_OR0_PRELIM 0xfe000ff7 /* 32MB Flash */ | |
138 | #define CFG_BR1_PRELIM 0xfc001001 /* port size 16bit */ | |
139 | #define CFG_OR1_PRELIM 0xfe000ff7 /* 32MB Flash */ | |
140 | ||
141 | #define CFG_FLASH_CFI /* flash is CFI compat. */ | |
142 | #define CFG_FLASH_CFI_DRIVER /* Use common CFI driver*/ | |
143 | #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector */ | |
144 | ||
145 | #define CFG_MAX_FLASH_BANKS 2 /* number of banks */ | |
e18575d5 | 146 | #define CFG_MAX_FLASH_SECT 256 /* sectors per device */ |
5d108ac8 SP |
147 | #undef CFG_FLASH_CHECKSUM |
148 | #define CFG_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */ | |
149 | #define CFG_FLASH_WRITE_TOUT 500 /* Flash Write Timeout (ms) */ | |
150 | ||
151 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ | |
152 | ||
153 | #define CFG_LBC_LCRR 0x00030008 /* LB clock ratio reg */ | |
154 | #define CFG_LBC_LBCR 0x00000000 /* LB config reg */ | |
155 | #define CFG_LBC_LSRT 0x20000000 /* LB sdram refresh timer */ | |
156 | #define CFG_LBC_MRTPR 0x20000000 /* LB refresh timer presc.*/ | |
157 | ||
158 | #define CONFIG_L1_INIT_RAM | |
159 | #define CFG_INIT_RAM_LOCK 1 | |
160 | #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ | |
161 | #define CFG_INIT_RAM_END 0x4000 /* End used area in RAM */ | |
162 | ||
163 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data*/ | |
164 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
165 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
166 | ||
167 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256kB for Mon*/ | |
fd51b0e0 | 168 | #define CFG_MALLOC_LEN (256 * 1024) /* Reserved for malloc */ |
5d108ac8 SP |
169 | |
170 | /* Serial Port */ | |
171 | ||
172 | #define CONFIG_CONS_INDEX 1 | |
173 | #undef CONFIG_SERIAL_SOFTWARE_FIFO | |
174 | #define CFG_NS16550 | |
175 | #define CFG_NS16550_SERIAL | |
176 | #define CFG_NS16550_REG_SIZE 1 | |
177 | #define CFG_NS16550_CLK get_bus_freq(0) | |
178 | ||
179 | #define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500) | |
180 | #define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600) | |
181 | ||
182 | #define CONFIG_BAUDRATE 115200 | |
183 | ||
184 | #define CFG_BAUDRATE_TABLE \ | |
185 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400,115200} | |
186 | ||
187 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ | |
188 | #define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ | |
189 | #ifdef CFG_HUSH_PARSER | |
190 | #define CFG_PROMPT_HUSH_PS2 "> " | |
191 | #endif | |
192 | ||
193 | ||
194 | /* | |
195 | * I2C | |
196 | */ | |
197 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
198 | #define CONFIG_HARD_I2C /* I2C with hardware support */ | |
199 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ | |
200 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
201 | #define CFG_I2C_SLAVE 0x7F | |
202 | #define CFG_I2C_NOPROBES {0x48} /* Don't probe these addrs */ | |
203 | #define CFG_I2C_OFFSET 0x3000 | |
204 | ||
205 | /* I2C RTC */ | |
e18575d5 SP |
206 | #define CONFIG_RTC_RX8025 /* Use Epson rx8025 rtc via i2c */ |
207 | #define CFG_I2C_RTC_ADDR 0x32 /* at address 0x32 */ | |
5d108ac8 | 208 | |
2f7468ae SP |
209 | /* I2C temp sensor */ |
210 | /* Socrates uses Maxim's DS75, which is compatible with LM75 */ | |
211 | #define CONFIG_DTT_LM75 1 | |
212 | #define CONFIG_DTT_SENSORS {4} /* Sensor addresses */ | |
213 | #define CFG_DTT_MAX_TEMP 125 | |
214 | #define CFG_DTT_LOW_TEMP -55 | |
215 | #define CFG_DTT_HYSTERESIS 3 | |
216 | #define CFG_EEPROM_PAGE_WRITE_ENABLE /* necessary for the LM75 chip */ | |
217 | #define CFG_EEPROM_PAGE_WRITE_BITS 4 | |
218 | ||
5d108ac8 SP |
219 | /* |
220 | * General PCI | |
221 | * Memory space is mapped 1-1. | |
222 | */ | |
223 | #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ | |
224 | ||
5e1882df SP |
225 | /* PCI is clocked by the external source at 33 MHz */ |
226 | #define CONFIG_PCI_CLK_FREQ 33000000 | |
5d108ac8 SP |
227 | #define CFG_PCI1_MEM_BASE 0x80000000 |
228 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
229 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
230 | #define CFG_PCI1_IO_BASE 0xE2000000 | |
231 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE | |
232 | #define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
233 | ||
234 | #if defined(CONFIG_PCI) | |
5d108ac8 | 235 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
d39e6851 | 236 | #undef CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ |
5d108ac8 SP |
237 | #endif /* CONFIG_PCI */ |
238 | ||
239 | ||
240 | #define CONFIG_NET_MULTI 1 | |
241 | #define CONFIG_MII 1 /* MII PHY management */ | |
242 | #define CONFIG_TSEC1 1 | |
243 | #define CONFIG_TSEC1_NAME "TSEC0" | |
2f845dc2 SP |
244 | #define CONFIG_TSEC3 1 |
245 | #define CONFIG_TSEC3_NAME "TSEC1" | |
5d108ac8 SP |
246 | #undef CONFIG_MPC85XX_FEC |
247 | ||
248 | #define TSEC1_PHY_ADDR 0 | |
2f845dc2 | 249 | #define TSEC3_PHY_ADDR 1 |
5d108ac8 SP |
250 | |
251 | #define TSEC1_PHYIDX 0 | |
2f845dc2 | 252 | #define TSEC3_PHYIDX 0 |
5d108ac8 | 253 | #define TSEC1_FLAGS TSEC_GIGABIT |
2f845dc2 | 254 | #define TSEC3_FLAGS TSEC_GIGABIT |
5d108ac8 | 255 | |
2f845dc2 | 256 | /* Options are: TSEC[0,1] */ |
5d108ac8 SP |
257 | #define CONFIG_ETHPRIME "TSEC0" |
258 | #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ | |
259 | ||
e18575d5 SP |
260 | #define CONFIG_HAS_ETH0 |
261 | #define CONFIG_HAS_ETH1 | |
262 | ||
5d108ac8 SP |
263 | /* |
264 | * Environment | |
265 | */ | |
266 | #define CFG_ENV_IS_IN_FLASH 1 | |
267 | #define CFG_ENV_SECT_SIZE 0x20000 /* 128K(one sector) for env */ | |
268 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE) | |
269 | #define CFG_ENV_SIZE 0x4000 | |
270 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) | |
271 | #define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) | |
272 | ||
273 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
274 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
275 | ||
276 | #define CONFIG_TIMESTAMP /* Print image info with ts */ | |
277 | ||
278 | ||
279 | /* | |
280 | * BOOTP options | |
281 | */ | |
282 | #define CONFIG_BOOTP_BOOTFILESIZE | |
283 | #define CONFIG_BOOTP_BOOTPATH | |
284 | #define CONFIG_BOOTP_GATEWAY | |
285 | #define CONFIG_BOOTP_HOSTNAME | |
286 | ||
287 | ||
288 | /* | |
289 | * Command line configuration. | |
290 | */ | |
291 | #include <config_cmd_default.h> | |
292 | ||
293 | #define CONFIG_CMD_DATE | |
294 | #define CONFIG_CMD_DHCP | |
2f7468ae | 295 | #define CONFIG_CMD_DTT |
5d108ac8 SP |
296 | #undef CONFIG_CMD_EEPROM |
297 | #define CONFIG_CMD_I2C | |
298 | #define CONFIG_CMD_MII | |
299 | #define CONFIG_CMD_NFS | |
300 | #define CONFIG_CMD_PING | |
5d108ac8 | 301 | #define CONFIG_CMD_SNTP |
791e1dba | 302 | #define CONFIG_CMD_USB |
5d108ac8 SP |
303 | |
304 | ||
305 | #if defined(CONFIG_PCI) | |
306 | #define CONFIG_CMD_PCI | |
307 | #endif | |
308 | ||
309 | ||
310 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
311 | ||
312 | /* | |
313 | * Miscellaneous configurable options | |
314 | */ | |
315 | #define CFG_LONGHELP /* undef to save memory */ | |
316 | #define CFG_LOAD_ADDR 0x2000000 /* default load address */ | |
317 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
318 | ||
319 | #if defined(CONFIG_CMD_KGDB) | |
320 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ | |
321 | #else | |
322 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
323 | #endif | |
324 | ||
325 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buf Size */ | |
326 | #define CFG_MAXARGS 16 /* max number of command args */ | |
327 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
328 | #define CFG_HZ 1000 /* decrementer freq: 1ms ticks */ | |
329 | ||
330 | /* | |
331 | * For booting Linux, the board info and command line data | |
332 | * have to be in the first 8 MB of memory, since this is | |
333 | * the maximum mapped by the Linux kernel during initialization. | |
334 | */ | |
335 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
336 | ||
337 | /* | |
338 | * Internal Definitions | |
339 | * | |
340 | * Boot Flags | |
341 | */ | |
342 | #define BOOTFLAG_COLD 0x01 /* Power-On: Boot from FLASH */ | |
343 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
344 | ||
345 | #if defined(CONFIG_CMD_KGDB) | |
346 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port*/ | |
347 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
348 | #endif | |
349 | ||
350 | ||
351 | #define CONFIG_LOADADDR 200000 /* default addr for tftp & bootm*/ | |
352 | ||
353 | #define CONFIG_BOOTDELAY 5 /* -1 disables auto-boot */ | |
354 | ||
355 | #define CONFIG_PREBOOT "echo;" \ | |
356 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
357 | "echo" | |
358 | ||
359 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
360 | ||
361 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
83e9d7a2 | 362 | "bootfile=$hostname/uImage\0" \ |
5d108ac8 SP |
363 | "netdev=eth0\0" \ |
364 | "consdev=ttyS0\0" \ | |
83e9d7a2 | 365 | "hostname=socrates\0" \ |
5d108ac8 SP |
366 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
367 | "nfsroot=$serverip:$rootpath\0" \ | |
368 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
369 | "addip=setenv bootargs $bootargs " \ | |
370 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
371 | ":$hostname:$netdev:off panic=1\0" \ | |
372 | "addcons=setenv bootargs $bootargs " \ | |
373 | "console=$consdev,$baudrate\0" \ | |
5d108ac8 | 374 | "flash_self=run ramargs addip addcons;" \ |
e18575d5 SP |
375 | "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ |
376 | "flash_nfs=run nfsargs addip addcons;" \ | |
377 | "bootm ${kernel_addr} - ${fdt_addr}\0" \ | |
378 | "net_nfs=tftp ${kernel_addr_r} ${bootfile}; " \ | |
379 | "tftp ${fdt_addr_r} ${fdt_file}; " \ | |
380 | "run nfsargs addip addcons;" \ | |
381 | "bootm ${kernel_addr_r} - ${fdt_addr_r}\0" \ | |
d39e6851 | 382 | "fdt_file=$hostname/socrates.dtb\0" \ |
e18575d5 SP |
383 | "fdt_addr_r=B00000\0" \ |
384 | "fdt_addr=FC1E0000\0" \ | |
d39e6851 | 385 | "rootpath=/opt/eldk/ppc_85xxDP\0" \ |
e18575d5 SP |
386 | "kernel_addr=FC000000\0" \ |
387 | "kernel_addr_r=200000\0" \ | |
388 | "ramdisk_addr=FC200000\0" \ | |
389 | "ramdisk_addr_r=400000\0" \ | |
83e9d7a2 | 390 | "load=tftp 100000 $hostname/u-boot.bin\0" \ |
5d108ac8 SP |
391 | "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ |
392 | "cp.b 100000 fffc0000 40000;" \ | |
393 | "setenv filesize;saveenv\0" \ | |
394 | "upd=run load update\0" \ | |
395 | "" | |
396 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
397 | ||
e18575d5 SP |
398 | /* pass open firmware flat tree */ |
399 | #define CONFIG_OF_LIBFDT 1 | |
400 | #define CONFIG_OF_BOARD_SETUP 1 | |
401 | ||
791e1dba SP |
402 | /* USB support */ |
403 | #define CONFIG_USB_OHCI_NEW 1 | |
404 | #define CONFIG_PCI_OHCI 1 | |
405 | #define CONFIG_PCI_OHCI_DEVNO 3 /* Number in PCI list */ | |
406 | #define CFG_USB_OHCI_MAX_ROOT_PORTS 15 | |
407 | #define CFG_USB_OHCI_SLOT_NAME "ohci_pci" | |
408 | #define CFG_OHCI_SWAP_REG_ACCESS 1 | |
409 | #define CONFIG_DOS_PARTITION 1 | |
410 | #define CONFIG_USB_STORAGE 1 | |
411 | ||
59abd15b SP |
412 | /* FPGA and NAND */ |
413 | #define CFG_FPGA_BASE 0xc0000000 | |
414 | #define CFG_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */ | |
415 | #define CFG_OR3_PRELIM 0xfff00000 /* 1 MB */ | |
fd51b0e0 SP |
416 | |
417 | #define CFG_NAND_BASE (CFG_FPGA_BASE + 0x70) | |
418 | #define CFG_MAX_NAND_DEVICE 1 | |
419 | #define NAND_MAX_CHIPS 1 | |
420 | #define CONFIG_CMD_NAND | |
421 | ||
5d108ac8 | 422 | #endif /* __CONFIG_H */ |