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12b43d51 WD |
1 | /* |
2 | * (C) Copyright 2004 | |
3 | * TsiChung Liew, Freescale Software Engineering, Tsi-Chung.Liew@freescale. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | #ifndef __CONFIG_H | |
25 | #define __CONFIG_H | |
26 | ||
27 | /* | |
28 | * High Level Configuration Options | |
29 | * (easy to change) | |
30 | */ | |
31 | #define CONFIG_MPC8220 1 | |
32 | #define CONFIG_SORCERY 1 /* Sorcery board */ | |
33 | ||
31d82672 BB |
34 | #define CONFIG_HIGH_BATS 1 /* High BATs supported */ |
35 | ||
12b43d51 WD |
36 | /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to |
37 | determine the CPU speed. */ | |
38 | #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ | |
39 | #define CFG_MPC8220_SYSPLL_VCO_MULTIPLIER 8 /* VCO multiplier can't be read from any register */ | |
40 | ||
41 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
42 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
43 | ||
12b43d51 WD |
44 | /* |
45 | * Serial console configuration | |
46 | */ | |
47 | #define CONFIG_PSC_CONSOLE 1 /* console is on PSC */ | |
48 | ||
49 | #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ | |
50 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } | |
51 | ||
7680c140 WD |
52 | /* PCI */ |
53 | #define CONFIG_PCI 1 | |
54 | #define CONFIG_PCI_PNP 1 | |
55 | ||
56 | #define CONFIG_PCI_MEM_BUS 0x80000000 | |
57 | #define CONFIG_PCI_MEM_PHYS CONFIG_PCI_MEM_BUS | |
58 | #define CONFIG_PCI_MEM_SIZE 0x10000000 | |
59 | ||
60 | #define CONFIG_PCI_IO_BUS 0x71000000 | |
61 | #define CONFIG_PCI_IO_PHYS CONFIG_PCI_IO_BUS | |
62 | #define CONFIG_PCI_IO_SIZE 0x01000000 | |
63 | ||
64 | #define CONFIG_PCI_CFG_BUS 0x70000000 | |
65 | #define CONFIG_PCI_CFG_PHYS CONFIG_PCI_CFG_BUS | |
66 | #define CONFIG_PCI_CFG_SIZE 0x01000000 | |
67 | ||
46da1e96 | 68 | |
079a136c JL |
69 | /* |
70 | * BOOTP options | |
71 | */ | |
72 | #define CONFIG_BOOTP_BOOTFILESIZE | |
73 | #define CONFIG_BOOTP_BOOTPATH | |
74 | #define CONFIG_BOOTP_GATEWAY | |
75 | #define CONFIG_BOOTP_HOSTNAME | |
76 | ||
77 | ||
12b43d51 | 78 | /* |
46da1e96 | 79 | * Command line configuration. |
12b43d51 | 80 | */ |
46da1e96 JL |
81 | #include <config_cmd_default.h> |
82 | ||
83 | #define CONFIG_CMD_BOOTD | |
84 | #define CONFIG_CMD_CACHE | |
85 | #define CONFIG_CMD_DHCP | |
86 | #define CONFIG_CMD_DIAG | |
87 | #define CONFIG_CMD_ELF | |
88 | #define CONFIG_CMD_I2C | |
89 | #define CONFIG_CMD_NET | |
90 | #define CONFIG_CMD_NFS | |
91 | #define CONFIG_CMD_PCI | |
92 | #define CONFIG_CMD_PING | |
93 | #define CONFIG_CMD_REGINFO | |
94 | #define CONFIG_CMD_SDRAM | |
95 | #define CONFIG_CMD_SNTP | |
96 | ||
12b43d51 WD |
97 | |
98 | /* | |
99 | * Default Environment | |
100 | */ | |
101 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
102 | #define CONFIG_HOSTNAME sorcery | |
103 | ||
104 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 | 105 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ |
12b43d51 WD |
106 | "echo" |
107 | ||
108 | #undef CONFIG_BOOTARGS | |
109 | ||
110 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
111 | "netdev=eth0\0" \ | |
112 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
113 | "nfsroot=$serverip:$rootpath\0" \ | |
114 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
115 | "addip=setenv bootargs $bootargs " \ | |
116 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
117 | ":$hostname:$netdev:off panic=1\0" \ | |
118 | "flash_nfs=run nfsargs addip;" \ | |
119 | "bootm $kernel_addr\0" \ | |
120 | "flash_self=run ramargs addip;" \ | |
121 | "bootm $kernel_addr $ramdisk_addr\0" \ | |
122 | "net_nfs=tftp 200000 $bootfile;run nfsargs addip;bootm\0" \ | |
123 | "rootpath=/opt/eldk/ppc_82xx\0" \ | |
124 | "bootfile=/tftpboot/sorcery/uImage\0" \ | |
125 | "kernel_addr=FFE00000\0" \ | |
126 | "ramdisk_addr=FFB00000\0" \ | |
127 | "" | |
128 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
129 | ||
130 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ | |
131 | ||
132 | #define CONFIG_NET_MULTI | |
7680c140 | 133 | #define CONFIG_EEPRO100 |
12b43d51 WD |
134 | |
135 | /* | |
136 | * I2C configuration | |
137 | */ | |
138 | #define CONFIG_HARD_I2C 1 | |
139 | #define CFG_I2C_MODULE 1 | |
140 | #define CFG_I2C_SPEED 100000 /* 100 kHz */ | |
141 | #define CFG_I2C_SLAVE 0x7F | |
142 | ||
143 | /* Use the HUSH parser */ | |
144 | #define CFG_HUSH_PARSER | |
145 | #ifdef CFG_HUSH_PARSER | |
146 | #define CFG_PROMPT_HUSH_PS2 "> " | |
147 | #endif | |
148 | ||
149 | /* | |
150 | * Flexbus Chipselect configuration | |
3c2b3d45 WD |
151 | * Beware: Some CS# seem to be mandatory (if these CS# are not set, |
152 | * board can hang-up in unpredictable place). | |
12b43d51 WD |
153 | * Sorcery_Memory_Map v0.3 is possibly wrong with CPLD CS# |
154 | */ | |
155 | ||
156 | /* Flash */ | |
157 | #define CFG_CS0_BASE 0xf800 | |
158 | #define CFG_CS0_MASK 0x08000000 /* 128 MB (two chips) */ | |
7680c140 | 159 | #define CFG_CS0_CTRL 0x001019c0 |
12b43d51 WD |
160 | |
161 | /* NVM */ | |
7680c140 WD |
162 | #define CFG_CS1_BASE 0xf7e8 |
163 | #define CFG_CS1_MASK 0x00040000 /* 256K */ | |
164 | #define CFG_CS1_CTRL 0x00101940 /* 8bit port size */ | |
12b43d51 WD |
165 | |
166 | /* Atlas2 + Gemini */ | |
7680c140 WD |
167 | #define CFG_CS2_BASE 0xf7e7 |
168 | #define CFG_CS2_MASK 0x00010000 /* 64K*/ | |
169 | #define CFG_CS2_CTRL 0x001011c0 /* 16bit port size */ | |
12b43d51 WD |
170 | |
171 | /* CAN Controller */ | |
7680c140 | 172 | #define CFG_CS3_BASE 0xf7e6 |
12b43d51 | 173 | #define CFG_CS3_MASK 0x00010000 /* 64K */ |
7680c140 | 174 | #define CFG_CS3_CTRL 0x00102140 /* 8Bit port size */ |
12b43d51 WD |
175 | |
176 | /* Foreign interface */ | |
7680c140 | 177 | #define CFG_CS4_BASE 0xf7e5 |
12b43d51 | 178 | #define CFG_CS4_MASK 0x00010000 /* 64K */ |
7680c140 | 179 | #define CFG_CS4_CTRL 0x00101dc0 /* 16bit port size */ |
12b43d51 | 180 | |
7680c140 WD |
181 | /* CPLD */ |
182 | #define CFG_CS5_BASE 0xf7e4 | |
183 | #define CFG_CS5_MASK 0x00010000 /* 64K */ | |
184 | #define CFG_CS5_CTRL 0x001000c0 /* 16bit port size */ | |
12b43d51 WD |
185 | |
186 | #define CFG_FLASH0_BASE (CFG_CS0_BASE << 16) | |
7680c140 | 187 | #define CFG_FLASH_BASE (CFG_FLASH0_BASE) |
12b43d51 | 188 | |
7680c140 WD |
189 | #define CFG_MAX_FLASH_BANKS 2 /* max num of flash banks */ |
190 | #define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ | |
12b43d51 | 191 | |
00b1883a | 192 | #define CONFIG_FLASH_CFI_DRIVER |
12b43d51 | 193 | #define CFG_FLASH_CFI |
53677ef1 | 194 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, \ |
12b43d51 WD |
195 | CFG_FLASH_BASE+0x04000000 } /* two banks */ |
196 | ||
197 | /* | |
198 | * Environment settings | |
199 | */ | |
200 | #define CFG_ENV_IS_IN_FLASH 1 | |
7680c140 WD |
201 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x8000000 - 0x40000) |
202 | #define CFG_ENV_SIZE 0x4000 /* 16K */ | |
203 | #define CFG_ENV_SECT_SIZE 0x20000 | |
204 | #define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR + 0x20000) | |
205 | #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE | |
12b43d51 WD |
206 | |
207 | #define CONFIG_ENV_OVERWRITE 1 | |
208 | ||
209 | #if defined CFG_ENV_IS_IN_FLASH | |
210 | #undef CFG_ENV_IS_IN_NVRAM | |
bb1f8b4f | 211 | #undef CONFIG_ENV_IS_IN_EEPROM |
12b43d51 WD |
212 | #elif defined CFG_ENV_IS_IN_NVRAM |
213 | #undef CFG_ENV_IS_IN_FLASH | |
bb1f8b4f JCPV |
214 | #undef CONFIG_ENV_IS_IN_EEPROM |
215 | #elif defined CONFIG_ENV_IS_IN_EEPROM | |
12b43d51 WD |
216 | #undef CFG_ENV_IS_IN_NVRAM |
217 | #undef CFG_ENV_IS_IN_FLASH | |
218 | #endif | |
219 | ||
220 | /* | |
221 | * Memory map | |
222 | */ | |
223 | #define CFG_MBAR 0xF0000000 | |
224 | #define CFG_SDRAM_BASE 0x00000000 | |
225 | #define CFG_DEFAULT_MBAR 0x80000000 | |
226 | #define CFG_SRAM_BASE (CFG_MBAR + 0x20000) | |
227 | #define CFG_SRAM_SIZE 0x8000 | |
228 | ||
229 | /* Use SRAM until RAM will be available */ | |
230 | #define CFG_INIT_RAM_ADDR (CFG_MBAR + 0x20000) | |
231 | #define CFG_INIT_RAM_END 0x8000 /* End of used area in DPRAM */ | |
232 | ||
233 | #define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ | |
234 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
235 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
236 | ||
237 | #define CFG_MONITOR_BASE TEXT_BASE | |
238 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
239 | # define CFG_RAMBOOT 1 | |
240 | #endif | |
241 | ||
242 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
243 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
244 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
245 | ||
246 | /* SDRAM configuration (for SPD) */ | |
247 | #define CFG_SDRAM_TOTAL_BANKS 1 | |
53677ef1 | 248 | #define CFG_SDRAM_SPD_I2C_ADDR 0x50 /* 7bit */ |
12b43d51 | 249 | #define CFG_SDRAM_SPD_SIZE 0x100 |
53677ef1 | 250 | #define CFG_SDRAM_CAS_LATENCY 5 /* (CL=2.5)x2 */ |
12b43d51 | 251 | |
7680c140 | 252 | /* SDRAM drive strength register (for SSTL_2 class II)*/ |
53677ef1 | 253 | #define CFG_SDRAM_DRIVE_STRENGTH ((DRIVE_STRENGTH_HIGH << SDRAMDS_SBE_SHIFT) | \ |
7680c140 WD |
254 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBC_SHIFT) | \ |
255 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBA_SHIFT) | \ | |
256 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBS_SHIFT) | \ | |
257 | (DRIVE_STRENGTH_HIGH << SDRAMDS_SBD_SHIFT)) | |
258 | ||
12b43d51 WD |
259 | /* |
260 | * Ethernet configuration | |
261 | */ | |
262 | #define CONFIG_MPC8220_FEC 1 | |
263 | #define CONFIG_FEC_10MBIT 1 /* Workaround for FEC 100Mbit problem */ | |
264 | #define CONFIG_PHY_ADDR 0x1F | |
f60ba0d3 | 265 | #define CONFIG_MII 1 |
12b43d51 WD |
266 | |
267 | /* | |
268 | * Miscellaneous configurable options | |
269 | */ | |
270 | #define CFG_LONGHELP /* undef to save memory */ | |
271 | #define CFG_PROMPT "=> " /* Monitor Command Prompt */ | |
46da1e96 | 272 | #if defined(CONFIG_CMD_KGDB) |
12b43d51 WD |
273 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
274 | #else | |
275 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
276 | #endif | |
277 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
278 | #define CFG_MAXARGS 16 /* max number of command args */ | |
279 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
280 | ||
281 | #define CFG_MEMTEST_START 0x00100000 /* memtest works on */ | |
282 | #define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ | |
283 | ||
284 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
285 | ||
286 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
287 | ||
46da1e96 JL |
288 | #define CFG_CACHELINE_SIZE 32 /* For MPC8220 CPUs */ |
289 | #if defined(CONFIG_CMD_KGDB) | |
53677ef1 | 290 | # define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ |
46da1e96 JL |
291 | #endif |
292 | ||
12b43d51 WD |
293 | /* |
294 | * Various low-level settings | |
295 | */ | |
3c2b3d45 WD |
296 | #define CFG_HID0_INIT 0 |
297 | #define CFG_HID0_FINAL 0 | |
12b43d51 | 298 | |
7680c140 WD |
299 | /* |
300 | #define CFG_HID0_INIT HID0_ICE | HID0_ICFI | |
301 | #define CFG_HID0_FINAL HID0_ICE | |
302 | */ | |
303 | ||
12b43d51 | 304 | #endif /* __CONFIG_H */ |