[people/ms/u-boot.git] / include / configs / spc1920.h

/*
 * (C) Copyright 2006
 * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
 *
 * Configuation settings for the SPC1920 board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __H
#define __CONFIG_H

#define CONFIG_SPC1920			1	/* SPC1920 board */
#define CONFIG_MPC885			1	/* MPC885 CPU */

#define	CONFIG_SYS_TEXT_BASE	0xFFF00000

#define	CONFIG_8xx_CONS_SMC1		/* Console is on SMC1 */
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE

#define CONFIG_MII
#define CONFIG_MII_INIT		1
#undef CONFIG_ETHER_ON_FEC1
#define CONFIG_ETHER_ON_FEC2
#define FEC_ENET
#define CONFIG_FEC2_PHY		1

#define CONFIG_BAUDRATE		19200

/* use PLD CLK4 instead of brg */
#define CONFIG_SYS_SPC1920_SMC1_CLK4

#define CONFIG_8xx_OSCLK		10000000 /* 10 MHz oscillator on EXTCLK  */
#define CONFIG_8xx_CPUCLK_DEFAULT	50000000
#define CONFIG_SYS_8xx_CPUCLK_MIN		40000000
#define CONFIG_SYS_8xx_CPUCLK_MAX		133000000

#define CONFIG_SYS_RESET_ADDRESS		0xC0000000

#define CONFIG_BOARD_EARLY_INIT_F
#define CONFIG_LAST_STAGE_INIT

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#define CONFIG_ENV_OVERWRITE

#define CONFIG_NFSBOOTCOMMAND							\
    "dhcp;"									\
    "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath "			\
    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
    "bootm"

#define CONFIG_BOOTCOMMAND							\
    "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
    "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;"		\
    "bootm fe080000"

#undef CONFIG_BOOTARGS

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define CONFIG_BZIP2	 /* include support for bzip2 compressed images */


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DATE
#define CONFIG_CMD_ECHO
#define CONFIG_CMD_IMMAP
#define CONFIG_CMD_JFFS2
#define CONFIG_CMD_NET
#define CONFIG_CMD_PING
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_I2C
#define CONFIG_CMD_MII

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP				/* undef to save memory		*/
#define CONFIG_SYS_HUSH_PARSER

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE		1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE		256		/* Console I/O Buffer Size	*/
#endif

#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size	*/
#define	CONFIG_SYS_MAXARGS		16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_LOAD_ADDR		0x00100000

#define CONFIG_SYS_BAUDRATE_TABLE	{ 2400, 4800, 9600, 19200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */

/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xF0000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_SIZE	0x2F00	/* Size of used area in DPRAM	*/
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 KB for monitor	*/

#ifdef CONFIG_BZIP2
#define	CONFIG_SYS_MALLOC_LEN		(2500 << 10)	/* Reserve ~2.5 MB for malloc()	*/
#else
#define	CONFIG_SYS_MALLOC_LEN		(384 << 10)	/* Reserve 384 kB for malloc()	*/
#endif /* CONFIG_BZIP2 */

#define	CONFIG_SYS_ALLOC_DPRAM		1	/* use allocation routines	*/

/*
 * Flash
 */
/*-----------------------------------------------------------------------
 * Flash organisation
 */
#define CONFIG_SYS_FLASH_BASE          0xFE000000
#define CONFIG_SYS_FLASH_CFI                           /* The flash is CFI compatible  */
#define CONFIG_FLASH_CFI_DRIVER                    /* Use common CFI driver        */
#define CONFIG_SYS_MAX_FLASH_BANKS     1               /* Max number of flash banks    */
#define CONFIG_SYS_MAX_FLASH_SECT      128             /* Max num of sects on one chip */

/* Environment is in flash */
#define CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE       0x40000         /* We use one complete sector   */
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)

#define CONFIG_ENV_OVERWRITE

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/

#ifdef CONFIG_CMD_DATE
# define CONFIG_RTC_DS3231
# define CONFIG_SYS_I2C_RTC_ADDR      0x68
#endif

/*-----------------------------------------------------------------------
 * I2C configuration
 */
#if defined(CONFIG_CMD_I2C)
/* enable I2C and select the hardware/software driver */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	93000	/* 93 kHz is supposed to work */
#define CONFIG_SYS_I2C_SOFT_SLAVE	0xFE
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PB_SCL         0x00000020      /* PB 26 */
#define PB_SDA         0x00000010      /* PB 27 */

#define I2C_INIT       (immr->im_cpm.cp_pbdir |=  PB_SCL)
#define I2C_ACTIVE     (immr->im_cpm.cp_pbdir |=  PB_SDA)
#define I2C_TRISTATE   (immr->im_cpm.cp_pbdir &= ~PB_SDA)
#define I2C_READ       ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
#define I2C_SDA(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SDA; \
		       else    immr->im_cpm.cp_pbdat &= ~PB_SDA
#define I2C_SCL(bit)   if(bit) immr->im_cpm.cp_pbdat |=  PB_SCL; \
		       else    immr->im_cpm.cp_pbdat &= ~PB_SCL
#define I2C_DELAY      udelay(2)       /* 1/4 I2C clock duration */
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR      (SIUMCR_FRC)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
/* #define CONFIG_SYS_SCCR	SCCR_TBS */
#define CONFIG_SYS_SCCR	(SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)

/*-----------------------------------------------------------------------
 * DER - Debug Enable Register
 *-----------------------------------------------------------------------
 * Set to zero to prevent the processor from entering debug mode
 */
#define CONFIG_SYS_DER		 0


/* Because of the way the 860 starts up and assigns CS0 the entire
 * address space, we have to set the memory controller differently.
 * Normally, you write the option register first, and then enable the
 * chip select by writing the base register.  For CS0, you must write
 * the base register first, followed by the option register.
 */


/*
 * Init Memory Controller:
 */

/* BR0 and OR0 (FLASH) */
#define FLASH_BASE0_PRELIM	CONFIG_SYS_FLASH_BASE	/* FLASH bank #0 */


/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
				 OR_SCY_6_CLK | OR_EHTR | OR_BI)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )


/*
 * SDRAM CS1 UPMB
 */
#define	CONFIG_SYS_SDRAM_BASE	0x00000000
#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
#define SDRAM_MAX_SIZE	0x4000000 /* max 64 MB */

#define CONFIG_SYS_PRELIM_OR1_AM	0xF0000000
/* #define CONFIG_SYS_OR1_TIMING  OR_CSNT_SAM/\*  | OR_G5LS /\\* *\\/ *\/ */
#define SDRAM_TIMING	OR_SCY_0_CLK	/* SDRAM-Timing */

#define CONFIG_SYS_OR1_PRELIM	(CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING)
#define CONFIG_SYS_BR1_PRELIM  ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V)

/* #define CONFIG_SYS_OR1_FINAL   ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */
/* #define CONFIG_SYS_BR1_FINAL   ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */

#define CONFIG_SYS_PTB_PER_CLK	((4096 * 16 * 1000) / (4 * 64))
#define CONFIG_SYS_PTA_PER_CLK 195
#define CONFIG_SYS_MBMR_PTB	195
#define CONFIG_SYS_MPTPR	MPTPR_PTP_DIV16
#define CONFIG_SYS_MAR		0x88

#define CONFIG_SYS_MBMR_8COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
			MBMR_AMB_TYPE_0 | \
			MBMR_G0CLB_A10 | \
			MBMR_DSB_1_CYCL | \
			MBMR_RLFB_1X | \
			MBMR_WLFB_1X | \
			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */

#define CONFIG_SYS_MBMR_9COL  ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \
			MBMR_AMB_TYPE_1 | \
			MBMR_G0CLB_A10 | \
			MBMR_DSB_1_CYCL | \
			MBMR_RLFB_1X | \
			MBMR_WLFB_1X | \
			MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */


/*
 * DSP Host Port Interface CS3
 */
#define CONFIG_SYS_SPC1920_HPI_BASE   0x90000000
#define CONFIG_SYS_PRELIM_OR3_AM      0xF8000000

#define CONFIG_SYS_OR3         (CONFIG_SYS_PRELIM_OR3_AM | \
				       OR_G5LS | \
				       OR_SCY_0_CLK | \
				       OR_BI)

#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \
					       BR_MS_UPMA | \
					       BR_PS_16 | \
					       BR_V)

#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \
		MAMR_RLFA_5X | \
		MAMR_WLFA_5X)

#define CONFIG_SPC1920_HPI_TEST

#ifdef CONFIG_SPC1920_HPI_TEST
#define HPI_REG(x)             (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
#define HPI_HPIC_1             HPI_REG(0)
#define HPI_HPIC_2             HPI_REG(2)
#define HPI_HPIA_1             HPI_REG(0x2000008)
#define HPI_HPIA_2             HPI_REG(0x2000008 + 2)
#define HPI_HPID_INC_1         HPI_REG(0x1000004)
#define HPI_HPID_INC_2         HPI_REG(0x1000004 + 2)
#define HPI_HPID_NOINC_1       HPI_REG(0x300000c)
#define HPI_HPID_NOINC_2       HPI_REG(0x300000c + 2)
#endif /* CONFIG_SPC1920_HPI_TEST */

/*
 * Ramtron FM18L08 FRAM 32KB on CS4
 */
#define CONFIG_SYS_SPC1920_FRAM_BASE	0x80100000
#define CONFIG_SYS_PRELIM_OR4_AM	0xffff8000
#define CONFIG_SYS_OR4		(CONFIG_SYS_PRELIM_OR4_AM | \
					OR_ACS_DIV2 | \
					OR_BI | \
					OR_SCY_4_CLK | \
					OR_TRLX)

#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)

/*
 * PLD CS5
 */
#define CONFIG_SYS_SPC1920_PLD_BASE	0x80000000
#define CONFIG_SYS_PRELIM_OR5_AM	0xffff8000

#define CONFIG_SYS_OR5_PRELIM		(CONFIG_SYS_PRELIM_OR5_AM | \
					OR_CSNT_SAM | \
					OR_ACS_DIV1 | \
					OR_BI | \
					OR_SCY_0_CLK | \
					OR_TRLX)

#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V)

#endif	/* __CONFIG_H */
Commit	Line	Data
b02d0177 MK	1	/*
	2	* (C) Copyright 2006
	3	* Markus Klotzbuecher, DENX Software Engineering, mk@denx.de
	4	*
	5	* Configuation settings for the SPC1920 board.
	6	*
3765b3e7	7	* SPDX-License-Identifier: GPL-2.0+
b02d0177 MK	8	*/
	9
	10	#ifndef __H
	11	#define __CONFIG_H
	12
	13	#define CONFIG_SPC1920 1 /* SPC1920 board */
	14	#define CONFIG_MPC885 1 /* MPC885 CPU */
	15
2ae18241 WD	16	#define CONFIG_SYS_TEXT_BASE 0xFFF00000
2ae18241 WD	17
b02d0177 MK	18	#define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */
	19	#undef CONFIG_8xx_CONS_SMC2
	20	#undef CONFIG_8xx_CONS_NONE
	21
	22	#define CONFIG_MII
0f3ba7e9	23	#define CONFIG_MII_INIT 1
b02d0177 MK	24	#undef CONFIG_ETHER_ON_FEC1
	25	#define CONFIG_ETHER_ON_FEC2
	26	#define FEC_ENET
b02d0177 MK	27	#define CONFIG_FEC2_PHY 1
	28
	29	#define CONFIG_BAUDRATE 19200
	30
	31	/* use PLD CLK4 instead of brg */
6d0f6bcf	32	#define CONFIG_SYS_SPC1920_SMC1_CLK4
b02d0177 MK	33
	34	#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */
	35	#define CONFIG_8xx_CPUCLK_DEFAULT 50000000
6d0f6bcf JCPV	36	#define CONFIG_SYS_8xx_CPUCLK_MIN 40000000
6d0f6bcf JCPV	37	#define CONFIG_SYS_8xx_CPUCLK_MAX 133000000
b02d0177	38
6d0f6bcf	39	#define CONFIG_SYS_RESET_ADDRESS 0xC0000000
b02d0177 MK	40
b02d0177 MK	41	#define CONFIG_BOARD_EARLY_INIT_F
5921e531	42	#define CONFIG_LAST_STAGE_INIT
b02d0177	43
5921e531	44	#if 0
b02d0177 MK	45	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	46	#else
	47	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	48	#endif
	49
	50	#define CONFIG_ENV_OVERWRITE
	51
	52	#define CONFIG_NFSBOOTCOMMAND \
	53	"dhcp;" \
	54	"setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \
	55	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
	56	"bootm"
	57
	58	#define CONFIG_BOOTCOMMAND \
	59	"setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\
	60	"ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \
	61	"bootm fe080000"
	62
	63	#undef CONFIG_BOOTARGS
	64
	65	#undef CONFIG_WATCHDOG /* watchdog disabled */
	66	#define CONFIG_BZIP2 /* include support for bzip2 compressed images */
	67
b02d0177	68
079a136c JL	69	/*
	70	* BOOTP options
	71	*/
	72	#define CONFIG_BOOTP_BOOTFILESIZE
	73	#define CONFIG_BOOTP_BOOTPATH
	74	#define CONFIG_BOOTP_GATEWAY
	75	#define CONFIG_BOOTP_HOSTNAME
	76
	77
46da1e96 JL	78	/*
	79	* Command line configuration.
	80	*/
	81	#include <config_cmd_default.h>
	82
	83	#define CONFIG_CMD_ASKENV
	84	#define CONFIG_CMD_DATE
	85	#define CONFIG_CMD_ECHO
	86	#define CONFIG_CMD_IMMAP
	87	#define CONFIG_CMD_JFFS2
1d9e31e0	88	#define CONFIG_CMD_NET
46da1e96 JL	89	#define CONFIG_CMD_PING
	90	#define CONFIG_CMD_DHCP
	91	#define CONFIG_CMD_I2C
	92	#define CONFIG_CMD_MII
b02d0177	93
b02d0177 MK	94	/*
	95	* Miscellaneous configurable options
	96	*/
6d0f6bcf	97	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf	98	#define CONFIG_SYS_HUSH_PARSER
b02d0177	99
46da1e96	100	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	101	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
b02d0177	102	#else
6d0f6bcf	103	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
b02d0177 MK	104	#endif
b02d0177 MK	105
6d0f6bcf JCPV	106	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */
	107	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	108	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
b02d0177	109
6d0f6bcf	110	#define CONFIG_SYS_LOAD_ADDR 0x00100000
b02d0177	111
6d0f6bcf	112	#define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 }
b02d0177 MK	113
	114	/*
	115	* Low Level Configuration Settings
	116	* (address mappings, register initial values, etc.)
	117	* You should know what you are doing if you make changes here.
	118	*/
	119
	120	/*-----------------------------------------------------------------------
	121	* Internal Memory Mapped Register
	122	*/
6d0f6bcf	123	#define CONFIG_SYS_IMMR 0xF0000000
b02d0177 MK	124
	125	/*-----------------------------------------------------------------------
	126	* Definitions for initial stack pointer and data area (in DPRAM)
	127	*/
6d0f6bcf	128	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
553f0982	129	#define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */
25ddd1fb	130	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	131	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
b02d0177 MK	132
	133	/*-----------------------------------------------------------------------
	134	* Start addresses for the final memory configuration
	135	* (Set up by the startup code)
6d0f6bcf	136	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
b02d0177	137	*/
6d0f6bcf JCPV	138	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	139	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
b02d0177 MK	140
	141	/*
	142	* For booting Linux, the board info and command line data
	143	* have to be in the first 8 MB of memory, since this is
	144	* the maximum mapped by the Linux kernel during initialization.
	145	*/
6d0f6bcf	146	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
b02d0177	147
14d0a02a	148	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE
6d0f6bcf	149	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */
b02d0177 MK	150
b02d0177 MK	151	#ifdef CONFIG_BZIP2
6d0f6bcf	152	#define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */
b02d0177	153	#else
6d0f6bcf	154	#define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */
b02d0177 MK	155	#endif /* CONFIG_BZIP2 */
b02d0177 MK	156
6d0f6bcf	157	#define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */
b02d0177 MK	158
	159	/*
	160	* Flash
	161	*/
	162	/*-----------------------------------------------------------------------
	163	* Flash organisation
	164	*/
6d0f6bcf JCPV	165	#define CONFIG_SYS_FLASH_BASE 0xFE000000
6d0f6bcf JCPV	166	#define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */
00b1883a	167	#define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */
6d0f6bcf JCPV	168	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */
6d0f6bcf JCPV	169	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */
b02d0177 MK	170
b02d0177 MK	171	/* Environment is in flash */
5a1aceb0	172	#define CONFIG_ENV_IS_IN_FLASH
0e8d1586	173	#define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */
6d0f6bcf	174	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN)
b02d0177 MK	175
	176	#define CONFIG_ENV_OVERWRITE
	177
	178	/*-----------------------------------------------------------------------
	179	* Cache Configuration
	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
6d0f6bcf JCPV	182	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
b02d0177	183
079a136c	184	#ifdef CONFIG_CMD_DATE
0be62728	185	# define CONFIG_RTC_DS3231
6d0f6bcf	186	# define CONFIG_SYS_I2C_RTC_ADDR 0x68
0be62728 MK	187	#endif
0be62728 MK	188
b02d0177 MK	189	/*-----------------------------------------------------------------------
	190	* I2C configuration
	191	*/
46da1e96	192	#if defined(CONFIG_CMD_I2C)
3f34f869	193	/* enable I2C and select the hardware/software driver */
ea818dbb HS	194	#define CONFIG_SYS_I2C
	195	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
	196	#define CONFIG_SYS_I2C_SOFT_SPEED 93000 /* 93 kHz is supposed to work */
	197	#define CONFIG_SYS_I2C_SOFT_SLAVE 0xFE
3f34f869 MK	198	/*
	199	* Software (bit-bang) I2C driver configuration
	200	*/
	201	#define PB_SCL 0x00000020 /* PB 26 */
	202	#define PB_SDA 0x00000010 /* PB 27 */
	203
	204	#define I2C_INIT (immr->im_cpm.cp_pbdir \|= PB_SCL)
	205	#define I2C_ACTIVE (immr->im_cpm.cp_pbdir \|= PB_SDA)
	206	#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA)
	207	#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0)
	208	#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SDA; \
d8d9de1a	209	else immr->im_cpm.cp_pbdat &= ~PB_SDA
3f34f869	210	#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat \|= PB_SCL; \
d8d9de1a	211	else immr->im_cpm.cp_pbdat &= ~PB_SCL
3f34f869	212	#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */
b02d0177 MK	213	#endif
	214
	215	/*-----------------------------------------------------------------------
	216	* SYPCR - System Protection Control 11-9
	217	* SYPCR can only be written once after reset!
	218	*-----------------------------------------------------------------------
	219	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	220	*/
	221	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	222	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
b02d0177 MK	223	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
b02d0177 MK	224	#else
6d0f6bcf	225	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
b02d0177 MK	226	#endif
	227
	228	/*-----------------------------------------------------------------------
	229	* SIUMCR - SIU Module Configuration 11-6
	230	*-----------------------------------------------------------------------
	231	* PCMCIA config., multi-function pin tri-state
	232	*/
6d0f6bcf	233	#define CONFIG_SYS_SIUMCR (SIUMCR_FRC)
b02d0177 MK	234
	235	/*-----------------------------------------------------------------------
	236	* TBSCR - Time Base Status and Control 11-26
	237	*-----------------------------------------------------------------------
	238	* Clear Reference Interrupt Status, Timebase freezing enabled
	239	*/
6d0f6bcf	240	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBE)
b02d0177 MK	241
	242	/*-----------------------------------------------------------------------
	243	* PISCR - Periodic Interrupt Status and Control 11-31
	244	*-----------------------------------------------------------------------
	245	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	246	*/
6d0f6bcf	247	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
b02d0177 MK	248
	249	/*-----------------------------------------------------------------------
	250	* SCCR - System Clock and reset Control Register 15-27
	251	*-----------------------------------------------------------------------
	252	* Set clock output, timebase and RTC source and divider,
	253	* power management and some other internal clocks
	254	*/
	255	#define SCCR_MASK SCCR_EBDF11
6d0f6bcf JCPV	256	/* #define CONFIG_SYS_SCCR SCCR_TBS */
6d0f6bcf JCPV	257	#define CONFIG_SYS_SCCR (SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
b02d0177 MK	258	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	259	SCCR_DFALCD00)
	260
	261	/*-----------------------------------------------------------------------
	262	* DER - Debug Enable Register
	263	*-----------------------------------------------------------------------
	264	* Set to zero to prevent the processor from entering debug mode
	265	*/
6d0f6bcf	266	#define CONFIG_SYS_DER 0
b02d0177 MK	267
	268
	269	/* Because of the way the 860 starts up and assigns CS0 the entire
	270	* address space, we have to set the memory controller differently.
	271	* Normally, you write the option register first, and then enable the
	272	* chip select by writing the base register. For CS0, you must write
	273	* the base register first, followed by the option register.
	274	*/
	275
	276
	277	/*
	278	* Init Memory Controller:
	279	*/
	280
	281	/* BR0 and OR0 (FLASH) */
6d0f6bcf	282	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
b02d0177 MK	283
	284
	285	/* used to re-map FLASH both when starting from SRAM or FLASH:
	286	* restrict access enough to keep SRAM working (if any)
	287	* but not too much to meddle with FLASH accesses
	288	*/
6d0f6bcf JCPV	289	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	290	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
b02d0177 MK	291
	292	/*
	293	* FLASH timing:
	294	*/
6d0f6bcf	295	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
8fc2102f	296	OR_SCY_6_CLK \| OR_EHTR \| OR_BI)
b02d0177	297
6d0f6bcf JCPV	298	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	299	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	300	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
b02d0177 MK	301
	302
	303	/*
	304	* SDRAM CS1 UPMB
	305	*/
6d0f6bcf JCPV	306	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	307	#define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE
b02d0177 MK	308	#define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */
b02d0177 MK	309
6d0f6bcf JCPV	310	#define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000
6d0f6bcf JCPV	311	/* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* \| OR_G5LS /\\* \\/ \/ */
b02d0177 MK	312	#define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */
b02d0177 MK	313
6d0f6bcf JCPV	314	#define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM \| OR_CSNT_SAM \| OR_G5LS \| SDRAM_TIMING)
6d0f6bcf JCPV	315	#define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) \| BR_MS_UPMB \| BR_V)
b02d0177	316
6d0f6bcf JCPV	317	/* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) \| CONFIG_SYS_OR1_TIMING) */
6d0f6bcf JCPV	318	/* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) \| BR_MS_UPMB \| BR_V) */
b02d0177	319
6d0f6bcf JCPV	320	#define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64))
	321	#define CONFIG_SYS_PTA_PER_CLK 195
	322	#define CONFIG_SYS_MBMR_PTB 195
	323	#define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16
	324	#define CONFIG_SYS_MAR 0x88
b02d0177	325
6d0f6bcf	326	#define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) \| \
b02d0177 MK	327	MBMR_AMB_TYPE_0 \| \
	328	MBMR_G0CLB_A10 \| \
	329	MBMR_DSB_1_CYCL \| \
	330	MBMR_RLFB_1X \| \
	331	MBMR_WLFB_1X \| \
	332	MBMR_TLFB_4X) /* 0x04804114 / / 0x10802114 */
	333
6d0f6bcf	334	#define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) \| \
b02d0177 MK	335	MBMR_AMB_TYPE_1 \| \
	336	MBMR_G0CLB_A10 \| \
	337	MBMR_DSB_1_CYCL \| \
	338	MBMR_RLFB_1X \| \
	339	MBMR_WLFB_1X \| \
	340	MBMR_TLFB_4X) /* 0x04804114 / / 0x10802114 */
	341
	342
d28707db MK	343	/*
	344	* DSP Host Port Interface CS3
	345	*/
6d0f6bcf JCPV	346	#define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000
6d0f6bcf JCPV	347	#define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000
d28707db	348
6d0f6bcf	349	#define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM \| \
d28707db MK	350	OR_G5LS \| \
	351	OR_SCY_0_CLK \| \
	352	OR_BI)
	353
6d0f6bcf	354	#define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) \| \
d28707db MK	355	BR_MS_UPMA \| \
d28707db MK	356	BR_PS_16 \| \
03e2dbb1	357	BR_V)
d28707db	358
6d0f6bcf	359	#define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS \| \
d28707db MK	360	MAMR_RLFA_5X \| \
	361	MAMR_WLFA_5X)
	362
	363	#define CONFIG_SPC1920_HPI_TEST
	364
	365	#ifdef CONFIG_SPC1920_HPI_TEST
6d0f6bcf	366	#define HPI_REG(x) (((volatile u16 ) (CONFIG_SYS_SPC1920_HPI_BASE + x)))
d28707db MK	367	#define HPI_HPIC_1 HPI_REG(0)
d28707db MK	368	#define HPI_HPIC_2 HPI_REG(2)
38ccd2fd MK	369	#define HPI_HPIA_1 HPI_REG(0x2000008)
	370	#define HPI_HPIA_2 HPI_REG(0x2000008 + 2)
	371	#define HPI_HPID_INC_1 HPI_REG(0x1000004)
	372	#define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2)
	373	#define HPI_HPID_NOINC_1 HPI_REG(0x300000c)
	374	#define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2)
d28707db MK	375	#endif /* CONFIG_SPC1920_HPI_TEST */
d28707db MK	376
9295acb7 MK	377	/*
	378	* Ramtron FM18L08 FRAM 32KB on CS4
	379	*/
6d0f6bcf JCPV	380	#define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000
	381	#define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000
	382	#define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM \| \
9295acb7 MK	383	OR_ACS_DIV2 \| \
	384	OR_BI \| \
	385	OR_SCY_4_CLK \| \
	386	OR_TRLX)
	387
6d0f6bcf	388	#define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V)
9295acb7	389
d8d9de1a	390	/*
5921e531	391	* PLD CS5
d8d9de1a	392	*/
6d0f6bcf JCPV	393	#define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000
6d0f6bcf JCPV	394	#define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000
b02d0177	395
6d0f6bcf	396	#define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM \| \
b02d0177 MK	397	OR_CSNT_SAM \| \
	398	OR_ACS_DIV1 \| \
	399	OR_BI \| \
	400	OR_SCY_0_CLK \| \
	401	OR_TRLX)
	402
6d0f6bcf	403	#define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) \| BR_PS_8 \| BR_V)
b02d0177	404
b02d0177	405	#endif /* __CONFIG_H */