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b02d0177 MK |
1 | /* |
2 | * (C) Copyright 2006 | |
3 | * Markus Klotzbuecher, DENX Software Engineering, mk@denx.de | |
4 | * | |
5 | * Configuation settings for the SPC1920 board. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or | |
8 | * modify it under the terms of the GNU General Public License as | |
9 | * published by the Free Software Foundation; either version 2 of | |
10 | * the License, or (at your option) any later version. | |
11 | * | |
12 | * This program is distributed in the hope that it will be useful, | |
13 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
14 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
15 | * GNU General Public License for more details. | |
16 | * | |
17 | * You should have received a copy of the GNU General Public License | |
18 | * along with this program; if not, write to the Free Software | |
19 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
20 | * MA 02111-1307 USA | |
21 | */ | |
22 | ||
23 | #ifndef __H | |
24 | #define __CONFIG_H | |
25 | ||
26 | #define CONFIG_SPC1920 1 /* SPC1920 board */ | |
27 | #define CONFIG_MPC885 1 /* MPC885 CPU */ | |
28 | ||
2ae18241 WD |
29 | #define CONFIG_SYS_TEXT_BASE 0xFFF00000 |
30 | ||
b02d0177 MK |
31 | #define CONFIG_8xx_CONS_SMC1 /* Console is on SMC1 */ |
32 | #undef CONFIG_8xx_CONS_SMC2 | |
33 | #undef CONFIG_8xx_CONS_NONE | |
34 | ||
35 | #define CONFIG_MII | |
0f3ba7e9 | 36 | #define CONFIG_MII_INIT 1 |
b02d0177 MK |
37 | #undef CONFIG_ETHER_ON_FEC1 |
38 | #define CONFIG_ETHER_ON_FEC2 | |
39 | #define FEC_ENET | |
b02d0177 MK |
40 | #define CONFIG_FEC2_PHY 1 |
41 | ||
42 | #define CONFIG_BAUDRATE 19200 | |
43 | ||
44 | /* use PLD CLK4 instead of brg */ | |
6d0f6bcf | 45 | #define CONFIG_SYS_SPC1920_SMC1_CLK4 |
b02d0177 MK |
46 | |
47 | #define CONFIG_8xx_OSCLK 10000000 /* 10 MHz oscillator on EXTCLK */ | |
48 | #define CONFIG_8xx_CPUCLK_DEFAULT 50000000 | |
6d0f6bcf JCPV |
49 | #define CONFIG_SYS_8xx_CPUCLK_MIN 40000000 |
50 | #define CONFIG_SYS_8xx_CPUCLK_MAX 133000000 | |
b02d0177 | 51 | |
6d0f6bcf | 52 | #define CONFIG_SYS_RESET_ADDRESS 0xC0000000 |
b02d0177 MK |
53 | |
54 | #define CONFIG_BOARD_EARLY_INIT_F | |
5921e531 | 55 | #define CONFIG_LAST_STAGE_INIT |
b02d0177 | 56 | |
5921e531 | 57 | #if 0 |
b02d0177 MK |
58 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ |
59 | #else | |
60 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
61 | #endif | |
62 | ||
63 | #define CONFIG_ENV_OVERWRITE | |
64 | ||
65 | #define CONFIG_NFSBOOTCOMMAND \ | |
66 | "dhcp;" \ | |
67 | "setenv bootargs root=/dev/nfs rw nfsroot=$rootpath " \ | |
68 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ | |
69 | "bootm" | |
70 | ||
71 | #define CONFIG_BOOTCOMMAND \ | |
72 | "setenv bootargs root=/dev/mtdblock2 rw mtdparts=phys:1280K(ROM)ro,-(root) "\ | |
73 | "ip=$ipaddr:$serverip:$gatewayip:$netmask:$hostname:eth0:off;" \ | |
74 | "bootm fe080000" | |
75 | ||
76 | #undef CONFIG_BOOTARGS | |
77 | ||
78 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
79 | #define CONFIG_BZIP2 /* include support for bzip2 compressed images */ | |
80 | ||
b02d0177 | 81 | |
079a136c JL |
82 | /* |
83 | * BOOTP options | |
84 | */ | |
85 | #define CONFIG_BOOTP_BOOTFILESIZE | |
86 | #define CONFIG_BOOTP_BOOTPATH | |
87 | #define CONFIG_BOOTP_GATEWAY | |
88 | #define CONFIG_BOOTP_HOSTNAME | |
89 | ||
90 | ||
46da1e96 JL |
91 | /* |
92 | * Command line configuration. | |
93 | */ | |
94 | #include <config_cmd_default.h> | |
95 | ||
96 | #define CONFIG_CMD_ASKENV | |
97 | #define CONFIG_CMD_DATE | |
98 | #define CONFIG_CMD_ECHO | |
99 | #define CONFIG_CMD_IMMAP | |
100 | #define CONFIG_CMD_JFFS2 | |
1d9e31e0 | 101 | #define CONFIG_CMD_NET |
46da1e96 JL |
102 | #define CONFIG_CMD_PING |
103 | #define CONFIG_CMD_DHCP | |
104 | #define CONFIG_CMD_I2C | |
105 | #define CONFIG_CMD_MII | |
b02d0177 | 106 | |
b02d0177 MK |
107 | /* |
108 | * Miscellaneous configurable options | |
109 | */ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
111 | #define CONFIG_SYS_PROMPT "=>" /* Monitor Command Prompt */ | |
112 | #define CONFIG_SYS_HUSH_PARSER | |
113 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
b02d0177 | 114 | |
46da1e96 | 115 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 116 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
b02d0177 | 117 | #else |
6d0f6bcf | 118 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
b02d0177 MK |
119 | #endif |
120 | ||
6d0f6bcf JCPV |
121 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + sizeof(CONFIG_SYS_PROMPT) + 16) /* Print Buffer Size */ |
122 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
123 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
b02d0177 | 124 | |
6d0f6bcf | 125 | #define CONFIG_SYS_LOAD_ADDR 0x00100000 |
b02d0177 | 126 | |
6d0f6bcf | 127 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
b02d0177 | 128 | |
6d0f6bcf | 129 | #define CONFIG_SYS_BAUDRATE_TABLE { 2400, 4800, 9600, 19200 } |
b02d0177 MK |
130 | |
131 | /* | |
132 | * Low Level Configuration Settings | |
133 | * (address mappings, register initial values, etc.) | |
134 | * You should know what you are doing if you make changes here. | |
135 | */ | |
136 | ||
137 | /*----------------------------------------------------------------------- | |
138 | * Internal Memory Mapped Register | |
139 | */ | |
6d0f6bcf | 140 | #define CONFIG_SYS_IMMR 0xF0000000 |
b02d0177 MK |
141 | |
142 | /*----------------------------------------------------------------------- | |
143 | * Definitions for initial stack pointer and data area (in DPRAM) | |
144 | */ | |
6d0f6bcf | 145 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 146 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 147 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 148 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
b02d0177 MK |
149 | |
150 | /*----------------------------------------------------------------------- | |
151 | * Start addresses for the final memory configuration | |
152 | * (Set up by the startup code) | |
6d0f6bcf | 153 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
b02d0177 | 154 | */ |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
156 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
b02d0177 MK |
157 | |
158 | /* | |
159 | * For booting Linux, the board info and command line data | |
160 | * have to be in the first 8 MB of memory, since this is | |
161 | * the maximum mapped by the Linux kernel during initialization. | |
162 | */ | |
6d0f6bcf | 163 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
b02d0177 | 164 | |
14d0a02a | 165 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 166 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 KB for monitor */ |
b02d0177 MK |
167 | |
168 | #ifdef CONFIG_BZIP2 | |
6d0f6bcf | 169 | #define CONFIG_SYS_MALLOC_LEN (2500 << 10) /* Reserve ~2.5 MB for malloc() */ |
b02d0177 | 170 | #else |
6d0f6bcf | 171 | #define CONFIG_SYS_MALLOC_LEN (384 << 10) /* Reserve 384 kB for malloc() */ |
b02d0177 MK |
172 | #endif /* CONFIG_BZIP2 */ |
173 | ||
6d0f6bcf | 174 | #define CONFIG_SYS_ALLOC_DPRAM 1 /* use allocation routines */ |
b02d0177 MK |
175 | |
176 | /* | |
177 | * Flash | |
178 | */ | |
179 | /*----------------------------------------------------------------------- | |
180 | * Flash organisation | |
181 | */ | |
6d0f6bcf JCPV |
182 | #define CONFIG_SYS_FLASH_BASE 0xFE000000 |
183 | #define CONFIG_SYS_FLASH_CFI /* The flash is CFI compatible */ | |
00b1883a | 184 | #define CONFIG_FLASH_CFI_DRIVER /* Use common CFI driver */ |
6d0f6bcf JCPV |
185 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* Max number of flash banks */ |
186 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* Max num of sects on one chip */ | |
b02d0177 MK |
187 | |
188 | /* Environment is in flash */ | |
5a1aceb0 | 189 | #define CONFIG_ENV_IS_IN_FLASH |
0e8d1586 | 190 | #define CONFIG_ENV_SECT_SIZE 0x40000 /* We use one complete sector */ |
6d0f6bcf | 191 | #define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + CONFIG_SYS_MONITOR_LEN) |
b02d0177 MK |
192 | |
193 | #define CONFIG_ENV_OVERWRITE | |
194 | ||
195 | /*----------------------------------------------------------------------- | |
196 | * Cache Configuration | |
197 | */ | |
6d0f6bcf JCPV |
198 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
199 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ | |
b02d0177 | 200 | |
079a136c | 201 | #ifdef CONFIG_CMD_DATE |
0be62728 | 202 | # define CONFIG_RTC_DS3231 |
6d0f6bcf | 203 | # define CONFIG_SYS_I2C_RTC_ADDR 0x68 |
0be62728 MK |
204 | #endif |
205 | ||
b02d0177 MK |
206 | /*----------------------------------------------------------------------- |
207 | * I2C configuration | |
208 | */ | |
46da1e96 | 209 | #if defined(CONFIG_CMD_I2C) |
3f34f869 MK |
210 | /* enable I2C and select the hardware/software driver */ |
211 | #undef CONFIG_HARD_I2C /* I2C with hardware support */ | |
212 | #define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ | |
213 | ||
6d0f6bcf JCPV |
214 | #define CONFIG_SYS_I2C_SPEED 93000 /* 93 kHz is supposed to work */ |
215 | #define CONFIG_SYS_I2C_SLAVE 0xFE | |
3f34f869 MK |
216 | |
217 | #ifdef CONFIG_SOFT_I2C | |
218 | /* | |
219 | * Software (bit-bang) I2C driver configuration | |
220 | */ | |
221 | #define PB_SCL 0x00000020 /* PB 26 */ | |
222 | #define PB_SDA 0x00000010 /* PB 27 */ | |
223 | ||
224 | #define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) | |
225 | #define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) | |
226 | #define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) | |
227 | #define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) | |
228 | #define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ | |
d8d9de1a | 229 | else immr->im_cpm.cp_pbdat &= ~PB_SDA |
3f34f869 | 230 | #define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ |
d8d9de1a | 231 | else immr->im_cpm.cp_pbdat &= ~PB_SCL |
3f34f869 MK |
232 | #define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ |
233 | #endif /* CONFIG_SOFT_I2C */ | |
b02d0177 MK |
234 | #endif |
235 | ||
236 | /*----------------------------------------------------------------------- | |
237 | * SYPCR - System Protection Control 11-9 | |
238 | * SYPCR can only be written once after reset! | |
239 | *----------------------------------------------------------------------- | |
240 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
241 | */ | |
242 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 243 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
b02d0177 MK |
244 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
245 | #else | |
6d0f6bcf | 246 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
b02d0177 MK |
247 | #endif |
248 | ||
249 | /*----------------------------------------------------------------------- | |
250 | * SIUMCR - SIU Module Configuration 11-6 | |
251 | *----------------------------------------------------------------------- | |
252 | * PCMCIA config., multi-function pin tri-state | |
253 | */ | |
6d0f6bcf | 254 | #define CONFIG_SYS_SIUMCR (SIUMCR_FRC) |
b02d0177 MK |
255 | |
256 | /*----------------------------------------------------------------------- | |
257 | * TBSCR - Time Base Status and Control 11-26 | |
258 | *----------------------------------------------------------------------- | |
259 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
260 | */ | |
6d0f6bcf | 261 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBE) |
b02d0177 MK |
262 | |
263 | /*----------------------------------------------------------------------- | |
264 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
265 | *----------------------------------------------------------------------- | |
266 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
267 | */ | |
6d0f6bcf | 268 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
b02d0177 MK |
269 | |
270 | /*----------------------------------------------------------------------- | |
271 | * SCCR - System Clock and reset Control Register 15-27 | |
272 | *----------------------------------------------------------------------- | |
273 | * Set clock output, timebase and RTC source and divider, | |
274 | * power management and some other internal clocks | |
275 | */ | |
276 | #define SCCR_MASK SCCR_EBDF11 | |
6d0f6bcf JCPV |
277 | /* #define CONFIG_SYS_SCCR SCCR_TBS */ |
278 | #define CONFIG_SYS_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
b02d0177 MK |
279 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ |
280 | SCCR_DFALCD00) | |
281 | ||
282 | /*----------------------------------------------------------------------- | |
283 | * DER - Debug Enable Register | |
284 | *----------------------------------------------------------------------- | |
285 | * Set to zero to prevent the processor from entering debug mode | |
286 | */ | |
6d0f6bcf | 287 | #define CONFIG_SYS_DER 0 |
b02d0177 MK |
288 | |
289 | ||
290 | /* Because of the way the 860 starts up and assigns CS0 the entire | |
291 | * address space, we have to set the memory controller differently. | |
292 | * Normally, you write the option register first, and then enable the | |
293 | * chip select by writing the base register. For CS0, you must write | |
294 | * the base register first, followed by the option register. | |
295 | */ | |
296 | ||
297 | ||
298 | /* | |
299 | * Init Memory Controller: | |
300 | */ | |
301 | ||
302 | /* BR0 and OR0 (FLASH) */ | |
6d0f6bcf | 303 | #define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */ |
b02d0177 MK |
304 | |
305 | ||
306 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
307 | * restrict access enough to keep SRAM working (if any) | |
308 | * but not too much to meddle with FLASH accesses | |
309 | */ | |
6d0f6bcf JCPV |
310 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
311 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
b02d0177 MK |
312 | |
313 | /* | |
314 | * FLASH timing: | |
315 | */ | |
6d0f6bcf | 316 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
8fc2102f | 317 | OR_SCY_6_CLK | OR_EHTR | OR_BI) |
b02d0177 | 318 | |
6d0f6bcf JCPV |
319 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
320 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
321 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
b02d0177 MK |
322 | |
323 | ||
324 | /* | |
325 | * SDRAM CS1 UPMB | |
326 | */ | |
6d0f6bcf JCPV |
327 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
328 | #define CONFIG_SYS_SDRAM_BASE_PRELIM CONFIG_SYS_SDRAM_BASE | |
b02d0177 MK |
329 | #define SDRAM_MAX_SIZE 0x4000000 /* max 64 MB */ |
330 | ||
6d0f6bcf JCPV |
331 | #define CONFIG_SYS_PRELIM_OR1_AM 0xF0000000 |
332 | /* #define CONFIG_SYS_OR1_TIMING OR_CSNT_SAM/\* | OR_G5LS /\\* *\\/ *\/ */ | |
b02d0177 MK |
333 | #define SDRAM_TIMING OR_SCY_0_CLK /* SDRAM-Timing */ |
334 | ||
6d0f6bcf JCPV |
335 | #define CONFIG_SYS_OR1_PRELIM (CONFIG_SYS_PRELIM_OR1_AM | OR_CSNT_SAM | OR_G5LS | SDRAM_TIMING) |
336 | #define CONFIG_SYS_BR1_PRELIM ((CONFIG_SYS_SDRAM_BASE_PRELIM & BR_BA_MSK) | BR_MS_UPMB | BR_V) | |
b02d0177 | 337 | |
6d0f6bcf JCPV |
338 | /* #define CONFIG_SYS_OR1_FINAL ((CONFIG_SYS_OR1_AM & OR_AM_MSK) | CONFIG_SYS_OR1_TIMING) */ |
339 | /* #define CONFIG_SYS_BR1_FINAL ((CONFIG_SYS_SDRAM_BASE & BR_BA_MSK) | BR_MS_UPMB | BR_V) */ | |
b02d0177 | 340 | |
6d0f6bcf JCPV |
341 | #define CONFIG_SYS_PTB_PER_CLK ((4096 * 16 * 1000) / (4 * 64)) |
342 | #define CONFIG_SYS_PTA_PER_CLK 195 | |
343 | #define CONFIG_SYS_MBMR_PTB 195 | |
344 | #define CONFIG_SYS_MPTPR MPTPR_PTP_DIV16 | |
345 | #define CONFIG_SYS_MAR 0x88 | |
b02d0177 | 346 | |
6d0f6bcf | 347 | #define CONFIG_SYS_MBMR_8COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
b02d0177 MK |
348 | MBMR_AMB_TYPE_0 | \ |
349 | MBMR_G0CLB_A10 | \ | |
350 | MBMR_DSB_1_CYCL | \ | |
351 | MBMR_RLFB_1X | \ | |
352 | MBMR_WLFB_1X | \ | |
353 | MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ | |
354 | ||
6d0f6bcf | 355 | #define CONFIG_SYS_MBMR_9COL ((CONFIG_SYS_MBMR_PTB << MBMR_PTB_SHIFT) | \ |
b02d0177 MK |
356 | MBMR_AMB_TYPE_1 | \ |
357 | MBMR_G0CLB_A10 | \ | |
358 | MBMR_DSB_1_CYCL | \ | |
359 | MBMR_RLFB_1X | \ | |
360 | MBMR_WLFB_1X | \ | |
361 | MBMR_TLFB_4X) /* 0x04804114 */ /* 0x10802114 */ | |
362 | ||
363 | ||
d28707db MK |
364 | /* |
365 | * DSP Host Port Interface CS3 | |
366 | */ | |
6d0f6bcf JCPV |
367 | #define CONFIG_SYS_SPC1920_HPI_BASE 0x90000000 |
368 | #define CONFIG_SYS_PRELIM_OR3_AM 0xF8000000 | |
d28707db | 369 | |
6d0f6bcf | 370 | #define CONFIG_SYS_OR3 (CONFIG_SYS_PRELIM_OR3_AM | \ |
d28707db MK |
371 | OR_G5LS | \ |
372 | OR_SCY_0_CLK | \ | |
373 | OR_BI) | |
374 | ||
6d0f6bcf | 375 | #define CONFIG_SYS_BR3 ((CONFIG_SYS_SPC1920_HPI_BASE & BR_BA_MSK) | \ |
d28707db MK |
376 | BR_MS_UPMA | \ |
377 | BR_PS_16 | \ | |
03e2dbb1 | 378 | BR_V) |
d28707db | 379 | |
6d0f6bcf | 380 | #define CONFIG_SYS_MAMR (MAMR_GPL_A4DIS | \ |
d28707db MK |
381 | MAMR_RLFA_5X | \ |
382 | MAMR_WLFA_5X) | |
383 | ||
384 | #define CONFIG_SPC1920_HPI_TEST | |
385 | ||
386 | #ifdef CONFIG_SPC1920_HPI_TEST | |
6d0f6bcf | 387 | #define HPI_REG(x) (*((volatile u16 *) (CONFIG_SYS_SPC1920_HPI_BASE + x))) |
d28707db MK |
388 | #define HPI_HPIC_1 HPI_REG(0) |
389 | #define HPI_HPIC_2 HPI_REG(2) | |
38ccd2fd MK |
390 | #define HPI_HPIA_1 HPI_REG(0x2000008) |
391 | #define HPI_HPIA_2 HPI_REG(0x2000008 + 2) | |
392 | #define HPI_HPID_INC_1 HPI_REG(0x1000004) | |
393 | #define HPI_HPID_INC_2 HPI_REG(0x1000004 + 2) | |
394 | #define HPI_HPID_NOINC_1 HPI_REG(0x300000c) | |
395 | #define HPI_HPID_NOINC_2 HPI_REG(0x300000c + 2) | |
d28707db MK |
396 | #endif /* CONFIG_SPC1920_HPI_TEST */ |
397 | ||
9295acb7 MK |
398 | /* |
399 | * Ramtron FM18L08 FRAM 32KB on CS4 | |
400 | */ | |
6d0f6bcf JCPV |
401 | #define CONFIG_SYS_SPC1920_FRAM_BASE 0x80100000 |
402 | #define CONFIG_SYS_PRELIM_OR4_AM 0xffff8000 | |
403 | #define CONFIG_SYS_OR4 (CONFIG_SYS_PRELIM_OR4_AM | \ | |
9295acb7 MK |
404 | OR_ACS_DIV2 | \ |
405 | OR_BI | \ | |
406 | OR_SCY_4_CLK | \ | |
407 | OR_TRLX) | |
408 | ||
6d0f6bcf | 409 | #define CONFIG_SYS_BR4 ((CONFIG_SYS_SPC1920_FRAM_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
9295acb7 | 410 | |
d8d9de1a | 411 | /* |
5921e531 | 412 | * PLD CS5 |
d8d9de1a | 413 | */ |
6d0f6bcf JCPV |
414 | #define CONFIG_SYS_SPC1920_PLD_BASE 0x80000000 |
415 | #define CONFIG_SYS_PRELIM_OR5_AM 0xffff8000 | |
b02d0177 | 416 | |
6d0f6bcf | 417 | #define CONFIG_SYS_OR5_PRELIM (CONFIG_SYS_PRELIM_OR5_AM | \ |
b02d0177 MK |
418 | OR_CSNT_SAM | \ |
419 | OR_ACS_DIV1 | \ | |
420 | OR_BI | \ | |
421 | OR_SCY_0_CLK | \ | |
422 | OR_TRLX) | |
423 | ||
6d0f6bcf | 424 | #define CONFIG_SYS_BR5_PRELIM ((CONFIG_SYS_SPC1920_PLD_BASE & BR_BA_MSK) | BR_PS_8 | BR_V) |
b02d0177 | 425 | |
b02d0177 | 426 | #endif /* __CONFIG_H */ |