[people/ms/u-boot.git] / include / configs / stamp.h

/*
 * U-boot - stamp.h  Configuration file for STAMP board
 *			having BF533 processor
 *
 * Copyright (c) 2005 blackfin.uclinux.org
 *
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_STAMP_H__
#define __CONFIG_STAMP_H__

/*
 * Board settings
 *
 */

#define __ADSPLPBLACKFIN__		1
#define __ADSPBF533__			1
#define CONFIG_STAMP			1
#define CONFIG_RTC_BF533		1

/* FLASH/ETHERNET uses the same address range */
#define SHARED_RESOURCES		1

#define CONFIG_VDSP			1

/*
 * Clock settings
 *
 */

/* CONFIG_CLKIN_HZ is any value in Hz				 */
#define CONFIG_CLKIN_HZ			11059200
/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN	 */
/*						    1=CLKIN/2	 */
#define CONFIG_CLKIN_HALF		0
/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass	 */
/*						 1=bypass PLL	 */
#define CONFIG_PLL_BYPASS		0
/* CONFIG_VCO_MULT controls what the multiplier of the PLL is.	 */
/* Values can range from 1-64					 */
#define CONFIG_VCO_MULT			45
/* CONFIG_CCLK_DIV controls what the core clock divider is	 */
/* Values can be 1, 2, 4, or 8 ONLY				 */
#define CONFIG_CCLK_DIV			1
/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
/* Values can range from 1-15					 */
#define CONFIG_SCLK_DIV			6

/*
 * Network Settings
 */
/* network support */
#define CONFIG_IPADDR		192.168.0.15
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_GATEWAYIP	192.168.0.1
#define CONFIG_SERVERIP		192.168.0.2
#define CONFIG_HOSTNAME		STAMP
#define CONFIG_ROOTPATH			/checkout/uClinux-dist/romfs

/* To remove hardcoding and enable MAC storage in EEPROM  */
/* #define CONFIG_ETHADDR		02:80:ad:20:31:b8 */

/*
 * Command settings
 *
 */

#define CFG_LONGHELP			1

#define CONFIG_BOOTDELAY		5
#define CONFIG_BOOT_RETRY_TIME		-1	/* Enable this if bootretry required, currently its disabled */
#define CONFIG_BOOTCOMMAND		"run ramboot"
#define CONFIG_AUTOBOOT_PROMPT		"autoboot in %d seconds\n"

#define CONFIG_COMMANDS			(CONFIG_CMD_DFL | \
					 CFG_CMD_PING	| \
					 CFG_CMD_ELF	| \
					 CFG_CMD_I2C	| \
					 CFG_CMD_CACHE	| \
					 CFG_CMD_JFFS2	| \
					 CFG_CMD_DATE)
#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"

#define CONFIG_EXTRA_ENV_SETTINGS												\
	"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0"							\
	"nfsargs=setenv bootargs root=/dev/nfs rw "									\
	"nfsroot=$(serverip):$(rootpath)\0"											\
	"addip=setenv bootargs $(bootargs) "										\
	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)"							\
	":$(hostname):eth0:off\0"													\
    "ramboot=tftpboot 0x1000000 linux;"											\
	"run ramargs;run addip;bootelf\0"											\
	"nfsboot=tftpboot 0x1000000 linux;"											\
	"run nfsargs;run addip;bootelf\0"											\
	"flashboot=bootm 0x20100000\0"												\
	""

/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
#include <cmd_confdefs.h>

/*
 * Console settings
 *
 */

#define CONFIG_BAUDRATE			57600
#define CFG_BAUDRATE_TABLE		{ 9600, 19200, 38400, 57600, 115200 }

#define CFG_PROMPT			"stamp>"	/* Monitor Command Prompt */
#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
#define CFG_CBSIZE			1024	/* Console I/O Buffer Size */
#else
#define CFG_CBSIZE			256	/* Console I/O Buffer Size */
#endif
#define CFG_PBSIZE			(CFG_CBSIZE+sizeof(CFG_PROMPT)+16)	/* Print Buffer Size */
#define CFG_MAXARGS			16	/* max number of command args */
#define CFG_BARGSIZE			CFG_CBSIZE	/* Boot Argument Buffer Size */

#define CONFIG_LOADS_ECHO		1

/*
 * Network settings
 *
 */

#define CONFIG_DRIVER_SMC91111		1
#define CONFIG_SMC91111_BASE		0x20300300
/* To remove hardcoding and enable MAC storage in EEPROM */
/* #define HARDCODE_MAC			1 */

/*
 * Flash settings
 *
 */

#define CFG_FLASH_CFI				/* The flash is CFI compatible	*/
#define CFG_FLASH_CFI_DRIVER			/* Use common CFI driver	*/
#define CFG_FLASH_CFI_AMD_RESET

#define CFG_ENV_IS_IN_FLASH		1

#define CFG_FLASH_BASE			0x20000000
#define CFG_MAX_FLASH_BANKS		1		/* max number of memory banks */
#define CFG_MAX_FLASH_SECT		67		/* max number of sectors on one chip */

#define CFG_ENV_ADDR			0x20020000
#define CFG_ENV_SIZE			0x10000
#define CFG_ENV_SECT_SIZE		0x10000 /* Total Size of Environment Sector */

#define CFG_FLASH_ERASE_TOUT		30000	/* Timeout for Chip Erase (in ms) */
#define CFG_FLASH_ERASEBLOCK_TOUT	5000	/* Timeout for Block Erase (in ms) */
#define CFG_FLASH_WRITE_TOUT		1	/* Timeout for Flash Write (in ms) */

/* JFFS Partition offset set  */
#define CFG_JFFS2_FIRST_BANK 0
#define CFG_JFFS2_NUM_BANKS  1
/* 512k reserved for u-boot */
#define CFG_JFFS2_FIRST_SECTOR		11

/*
 * following timeouts shall be used once the
 * Flash real protection is enabled
 */
#define CFG_FLASH_LOCK_TOUT		5	/* Timeout for Flash Set Lock Bit (in ms) */
#define CFG_FLASH_UNLOCK_TOUT		10000	/* Timeout for Flash Clear Lock Bits (in ms) */

/*
 * I2C settings
 * By default PF2 is used as SDA and PF3 as SCL on the Stamp board
 */
#define CONFIG_SOFT_I2C			1	/* I2C bit-banged		*/
/*
 * Software (bit-bang) I2C driver configuration
 */
#define PF_SCL				PF3
#define PF_SDA				PF2

#define I2C_INIT			(*pFIO_DIR |=  PF_SCL); asm("ssync;")
#define I2C_ACTIVE			(*pFIO_DIR |=  PF_SDA); *pFIO_INEN &= ~PF_SDA; asm("ssync;")
#define I2C_TRISTATE			(*pFIO_DIR &= ~PF_SDA); *pFIO_INEN |= PF_SDA; asm("ssync;")
#define I2C_READ			((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
#define I2C_SDA(bit)			if(bit) { \
							*pFIO_FLAG_S = PF_SDA; \
							asm("ssync;"); \
						} \
					else	{ \
							*pFIO_FLAG_C = PF_SDA; \
							asm("ssync;"); \
						}
#define I2C_SCL(bit)			if(bit) { \
							*pFIO_FLAG_S = PF_SCL; \
							asm("ssync;"); \
						} \
					else	{ \
							*pFIO_FLAG_C = PF_SCL; \
							asm("ssync;"); \
						}
#define I2C_DELAY			udelay(5)	/* 1/4 I2C clock duration */

#define CFG_I2C_SPEED			50000
#define CFG_I2C_SLAVE			0xFE

/*
 * Compact Flash settings
 */

/* Enabled below option for CF support */
/* #define CONFIG_STAMP_CF		1 */

#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)

#define CONFIG_MISC_INIT_R		1
#define CONFIG_DOS_PARTITION		1

/*
 * IDE/ATA stuff
 */
#undef	CONFIG_IDE_8xx_DIRECT		/* no pcmcia interface required */
#undef	CONFIG_IDE_LED			/* no led for ide supported */
#undef	CONFIG_IDE_RESET		/* no reset for ide supported */

#define CFG_IDE_MAXBUS	1		/* max. 1 IDE busses */
#define CFG_IDE_MAXDEVICE		(CFG_IDE_MAXBUS*1) /* max. 1 drives per IDE bus */

#define CFG_ATA_BASE_ADDR		0x20200000
#define CFG_ATA_IDE0_OFFSET		0x0000

#define CFG_ATA_DATA_OFFSET		0x0020	/* Offset for data I/O */
#define CFG_ATA_REG_OFFSET		0x0020	/* Offset for normal register accesses */
#define CFG_ATA_ALT_OFFSET		0x0007	/* Offset for alternate registers */

#define CFG_ATA_STRIDE			2
#endif

/*
 * SDRAM settings
 *
 */

#define CONFIG_MEM_SIZE			128		/* 128, 64, 32, 16 */
#define CONFIG_MEM_ADD_WDTH		11	       /* 8, 9, 10, 11	  */
#define CONFIG_MEM_MT48LC64M4A2FB_7E	1

#define CFG_MEMTEST_START		0x00100000	/* memtest works on */
#define CFG_MEMTEST_END			0x07EFFFFF	/* 1 ... 127 MB in DRAM */
#define CFG_LOAD_ADDR			0x01000000	/* default load address */

#define CFG_SDRAM_BASE			0x00000000
#define CFG_MAX_RAM_SIZE		0x08000000

#define CFG_MONITOR_LEN			(256 << 10)	/* Reserve 256 kB for Monitor	*/
#define CFG_MONITOR_BASE		(CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)

#if ( CONFIG_CLKIN_HALF == 0 )
#define CONFIG_VCO_HZ			( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
#else
#define CONFIG_VCO_HZ			(( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
#endif

#if (CONFIG_PLL_BYPASS == 0)
#define CONFIG_CCLK_HZ			( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
#define CONFIG_SCLK_HZ			( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
#else
#define CONFIG_CCLK_HZ			CONFIG_CLKIN_HZ
#define CONFIG_SCLK_HZ			CONFIG_CLKIN_HZ
#endif

/*
 * Miscellaneous configurable options
 */
#define CFG_HZ				1000		/* 1ms time tick */

#define CFG_MALLOC_LEN			(128 << 10)	/* Reserve 128 kB for malloc()	*/
#define CFG_MALLOC_BASE			(CFG_MONITOR_BASE - CFG_MALLOC_LEN)
#define CFG_GBL_DATA_SIZE		0x4000
#define CFG_GBL_DATA_ADDR		(CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
#define CONFIG_STACKBASE		(CFG_GBL_DATA_ADDR  - 4)

#define CFG_LARGE_IMAGE_LEN	0x4000000	/* Large Image Length, set to 64 Meg */

#define CONFIG_SHOW_BOOT_PROGRESS	1	/* Show boot progress on LEDs */

/*
 * Stack sizes
 */
#define CONFIG_STACKSIZE		(128*1024)	/* regular stack */

/*
 * FLASH organization and environment definitions
 */
#define CFG_BOOTMAPSZ			(8 << 20)	/* Initial Memory map for Linux */

/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
/*#define AMGCTLVAL		(AMBEN_P0 | AMBEN_P1 | AMBEN_P2 | AMCKEN)
#define AMBCTL0VAL		(B1WAT_11 | B1RAT_11 | B1HT_3 | B1ST_4 | B1TT_4 | B1RDYPOL |	\
				B1RDYEN | B0WAT_11 | B0RAT_11 | B0HT_3 | B0ST_4 | B0TT_4 | B0RDYPOL | B0RDYEN)
#define AMBCTL1VAL		(B3WAT_9 | B3RAT_9 | B3HT_2 | B3ST_3 | B3TT_4 | B3RDYPOL |	\
				B3RDYEN | B2WAT_9 | B2RAT_9 | B2HT_2 | B2ST_4 | B2TT_4 | B2RDYPOL | B2RDYEN)
*/
#define AMGCTLVAL		0xFF
#define AMBCTL0VAL		0xBBC3BBC3
#define AMBCTL1VAL		0x99B39983
#define CF_AMBCTL1VAL		0x99B3ffc2

#ifdef CONFIG_VDSP
#define ET_EXEC_VDSP		0x8
#define SHT_STRTAB_VDSP		0x1
#define ELFSHDRSIZE_VDSP	0x2C
#define VDSP_ENTRY_ADDR		0xFFA00000
#endif

#endif
Commit	Line	Data
6cb142fa WD	1	/*
	2	* U-boot - stamp.h Configuration file for STAMP board
	3	* having BF533 processor
	4	*
	5	* Copyright (c) 2005 blackfin.uclinux.org
	6	*
	7	* (C) Copyright 2000-2004
	8	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
8e7b703a	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
6cb142fa WD	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	#ifndef __CONFIG_STAMP_H__
	30	#define __CONFIG_STAMP_H__
	31
	32	/*
	33	* Board settings
	34	*
	35	*/
	36
	37	#define __ADSPLPBLACKFIN__ 1
	38	#define __ADSPBF533__ 1
	39	#define CONFIG_STAMP 1
	40	#define CONFIG_RTC_BF533 1
	41
	42	/* FLASH/ETHERNET uses the same address range */
8e7b703a	43	#define SHARED_RESOURCES 1
6cb142fa WD	44
	45	#define CONFIG_VDSP 1
	46
	47	/*
	48	* Clock settings
	49	*
	50	*/
	51
8e7b703a	52	/* CONFIG_CLKIN_HZ is any value in Hz */
6cb142fa	53	#define CONFIG_CLKIN_HZ 11059200
8e7b703a WD	54	/* CONFIG_CLKIN_HALF controls what is passed to PLL 0=CLKIN */
8e7b703a WD	55	/* 1=CLKIN/2 */
6cb142fa	56	#define CONFIG_CLKIN_HALF 0
8e7b703a WD	57	/* CONFIG_PLL_BYPASS controls if the PLL is used 0=don't bypass */
	58	/* 1=bypass PLL */
	59	#define CONFIG_PLL_BYPASS 0
	60	/* CONFIG_VCO_MULT controls what the multiplier of the PLL is. */
	61	/* Values can range from 1-64 */
6cb142fa	62	#define CONFIG_VCO_MULT 45
8e7b703a WD	63	/* CONFIG_CCLK_DIV controls what the core clock divider is */
8e7b703a WD	64	/* Values can be 1, 2, 4, or 8 ONLY */
6cb142fa WD	65	#define CONFIG_CCLK_DIV 1
6cb142fa WD	66	/* CONFIG_SCLK_DIV controls what the peripheral clock divider is */
8e7b703a	67	/* Values can range from 1-15 */
6cb142fa WD	68	#define CONFIG_SCLK_DIV 6
	69
	70	/*
	71	* Network Settings
	72	*/
	73	/* network support */
8e7b703a WD	74	#define CONFIG_IPADDR 192.168.0.15
	75	#define CONFIG_NETMASK 255.255.255.0
	76	#define CONFIG_GATEWAYIP 192.168.0.1
	77	#define CONFIG_SERVERIP 192.168.0.2
	78	#define CONFIG_HOSTNAME STAMP
6cb142fa WD	79	#define CONFIG_ROOTPATH /checkout/uClinux-dist/romfs
	80
	81	/* To remove hardcoding and enable MAC storage in EEPROM */
8e7b703a	82	/* #define CONFIG_ETHADDR 02:80:ad:20:31:b8 */
6cb142fa WD	83
	84	/*
	85	* Command settings
	86	*
	87	*/
	88
	89	#define CFG_LONGHELP 1
	90
	91	#define CONFIG_BOOTDELAY 5
	92	#define CONFIG_BOOT_RETRY_TIME -1 /* Enable this if bootretry required, currently its disabled */
8e7b703a	93	#define CONFIG_BOOTCOMMAND "run ramboot"
6cb142fa WD	94	#define CONFIG_AUTOBOOT_PROMPT "autoboot in %d seconds\n"
6cb142fa WD	95
8e7b703a	96	#define CONFIG_COMMANDS (CONFIG_CMD_DFL \| \
6cb142fa WD	97	CFG_CMD_PING \| \
	98	CFG_CMD_ELF \| \
	99	CFG_CMD_I2C \| \
	100	CFG_CMD_CACHE \| \
8e7b703a	101	CFG_CMD_JFFS2 \| \
6cb142fa	102	CFG_CMD_DATE)
8e7b703a	103	#define CONFIG_BOOTARGS "root=/dev/mtdblock0 rw"
6cb142fa WD	104
	105	#define CONFIG_EXTRA_ENV_SETTINGS \
	106	"ramargs=setenv bootargs root=/dev/mtdblock0 rw\0" \
	107	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	108	"nfsroot=$(serverip):$(rootpath)\0" \
	109	"addip=setenv bootargs $(bootargs) " \
	110	"ip=$(ipaddr):$(serverip):$(gatewayip):$(netmask)" \
	111	":$(hostname):eth0:off\0" \
	112	"ramboot=tftpboot 0x1000000 linux;" \
	113	"run ramargs;run addip;bootelf\0" \
	114	"nfsboot=tftpboot 0x1000000 linux;" \
	115	"run nfsargs;run addip;bootelf\0" \
	116	"flashboot=bootm 0x20100000\0" \
	117	""
	118
	119	/* This must be included AFTER the definition of CONFIG_COMMANDS (if any) */
	120	#include <cmd_confdefs.h>
	121
	122	/*
	123	* Console settings
	124	*
	125	*/
	126
	127	#define CONFIG_BAUDRATE 57600
	128	#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
	129
8e7b703a	130	#define CFG_PROMPT "stamp>" /* Monitor Command Prompt */
6cb142fa	131	#if (CONFIG_COMMANDS & CFG_CMD_KGDB)
8e7b703a	132	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
6cb142fa	133	#else
8e7b703a	134	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
6cb142fa	135	#endif
8e7b703a WD	136	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
8e7b703a WD	137	#define CFG_MAXARGS 16 /* max number of command args */
6cb142fa WD	138	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	139
	140	#define CONFIG_LOADS_ECHO 1
	141
	142	/*
	143	* Network settings
	144	*
	145	*/
	146
	147	#define CONFIG_DRIVER_SMC91111 1
	148	#define CONFIG_SMC91111_BASE 0x20300300
	149	/* To remove hardcoding and enable MAC storage in EEPROM */
	150	/* #define HARDCODE_MAC 1 */
	151
	152	/*
	153	* Flash settings
	154	*
	155	*/
	156
8e7b703a WD	157	#define CFG_FLASH_CFI /* The flash is CFI compatible */
	158	#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */
	159	#define CFG_FLASH_CFI_AMD_RESET
6cb142fa WD	160
	161	#define CFG_ENV_IS_IN_FLASH 1
	162
	163	#define CFG_FLASH_BASE 0x20000000
	164	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	165	#define CFG_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
	166
	167	#define CFG_ENV_ADDR 0x20020000
8e7b703a WD	168	#define CFG_ENV_SIZE 0x10000
8e7b703a WD	169	#define CFG_ENV_SECT_SIZE 0x10000 /* Total Size of Environment Sector */
6cb142fa WD	170
	171	#define CFG_FLASH_ERASE_TOUT 30000 /* Timeout for Chip Erase (in ms) */
	172	#define CFG_FLASH_ERASEBLOCK_TOUT 5000 /* Timeout for Block Erase (in ms) */
	173	#define CFG_FLASH_WRITE_TOUT 1 /* Timeout for Flash Write (in ms) */
	174
	175	/* JFFS Partition offset set */
	176	#define CFG_JFFS2_FIRST_BANK 0
	177	#define CFG_JFFS2_NUM_BANKS 1
	178	/* 512k reserved for u-boot */
8e7b703a	179	#define CFG_JFFS2_FIRST_SECTOR 11
6cb142fa	180
8e7b703a WD	181	/*
8e7b703a WD	182	* following timeouts shall be used once the
6cb142fa WD	183	* Flash real protection is enabled
	184	*/
	185	#define CFG_FLASH_LOCK_TOUT 5 /* Timeout for Flash Set Lock Bit (in ms) */
	186	#define CFG_FLASH_UNLOCK_TOUT 10000 /* Timeout for Flash Clear Lock Bits (in ms) */
	187
	188	/*
	189	* I2C settings
	190	* By default PF2 is used as SDA and PF3 as SCL on the Stamp board
	191	*/
	192	#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */
	193	/*
	194	* Software (bit-bang) I2C driver configuration
	195	*/
	196	#define PF_SCL PF3
	197	#define PF_SDA PF2
	198
	199	#define I2C_INIT (*pFIO_DIR \|= PF_SCL); asm("ssync;")
	200	#define I2C_ACTIVE (pFIO_DIR \|= PF_SDA); pFIO_INEN &= ~PF_SDA; asm("ssync;")
	201	#define I2C_TRISTATE (pFIO_DIR &= ~PF_SDA); pFIO_INEN \|= PF_SDA; asm("ssync;")
	202	#define I2C_READ ((volatile)(*pFIO_FLAG_D & PF_SDA) != 0); asm("ssync;")
	203	#define I2C_SDA(bit) if(bit) { \
	204	*pFIO_FLAG_S = PF_SDA; \
	205	asm("ssync;"); \
	206	} \
8e7b703a	207	else { \
6cb142fa WD	208	*pFIO_FLAG_C = PF_SDA; \
	209	asm("ssync;"); \
	210	}
	211	#define I2C_SCL(bit) if(bit) { \
	212	*pFIO_FLAG_S = PF_SCL; \
	213	asm("ssync;"); \
	214	} \
8e7b703a	215	else { \
6cb142fa WD	216	*pFIO_FLAG_C = PF_SCL; \
	217	asm("ssync;"); \
	218	}
	219	#define I2C_DELAY udelay(5) /* 1/4 I2C clock duration */
	220
	221	#define CFG_I2C_SPEED 50000
	222	#define CFG_I2C_SLAVE 0xFE
	223
	224	/*
	225	* Compact Flash settings
	226	*/
	227
	228	/* Enabled below option for CF support */
	229	/* #define CONFIG_STAMP_CF 1 */
	230
	231	#if defined(CONFIG_STAMP_CF) && (CONFIG_COMMANDS & CFG_CMD_IDE)
	232
	233	#define CONFIG_MISC_INIT_R 1
	234	#define CONFIG_DOS_PARTITION 1
	235
	236	/*
	237	* IDE/ATA stuff
	238	*/
8e7b703a WD	239	#undef CONFIG_IDE_8xx_DIRECT /* no pcmcia interface required */
	240	#undef CONFIG_IDE_LED /* no led for ide supported */
	241	#undef CONFIG_IDE_RESET /* no reset for ide supported */
6cb142fa WD	242
	243	#define CFG_IDE_MAXBUS 1 /* max. 1 IDE busses */
	244	#define CFG_IDE_MAXDEVICE (CFG_IDE_MAXBUS1) / max. 1 drives per IDE bus */
	245
	246	#define CFG_ATA_BASE_ADDR 0x20200000
	247	#define CFG_ATA_IDE0_OFFSET 0x0000
	248
8e7b703a WD	249	#define CFG_ATA_DATA_OFFSET 0x0020 /* Offset for data I/O */
	250	#define CFG_ATA_REG_OFFSET 0x0020 /* Offset for normal register accesses */
	251	#define CFG_ATA_ALT_OFFSET 0x0007 /* Offset for alternate registers */
6cb142fa WD	252
	253	#define CFG_ATA_STRIDE 2
	254	#endif
	255
	256	/*
	257	* SDRAM settings
	258	*
	259	*/
	260
8e7b703a WD	261	#define CONFIG_MEM_SIZE 128 /* 128, 64, 32, 16 */
8e7b703a WD	262	#define CONFIG_MEM_ADD_WDTH 11 /* 8, 9, 10, 11 */
6cb142fa WD	263	#define CONFIG_MEM_MT48LC64M4A2FB_7E 1
	264
	265	#define CFG_MEMTEST_START 0x00100000 /* memtest works on */
	266	#define CFG_MEMTEST_END 0x07EFFFFF /* 1 ... 127 MB in DRAM */
8e7b703a	267	#define CFG_LOAD_ADDR 0x01000000 /* default load address */
6cb142fa	268
8e7b703a	269	#define CFG_SDRAM_BASE 0x00000000
6cb142fa WD	270	#define CFG_MAX_RAM_SIZE 0x08000000
6cb142fa WD	271
8e7b703a	272	#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6cb142fa WD	273	#define CFG_MONITOR_BASE (CFG_MAX_RAM_SIZE - CFG_MONITOR_LEN)
6cb142fa WD	274
6cb142fa WD	275	#if ( CONFIG_CLKIN_HALF == 0 )
	276	#define CONFIG_VCO_HZ ( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT )
	277	#else
	278	#define CONFIG_VCO_HZ (( CONFIG_CLKIN_HZ * CONFIG_VCO_MULT ) / 2 )
	279	#endif
	280
	281	#if (CONFIG_PLL_BYPASS == 0)
	282	#define CONFIG_CCLK_HZ ( CONFIG_VCO_HZ / CONFIG_CCLK_DIV )
	283	#define CONFIG_SCLK_HZ ( CONFIG_VCO_HZ / CONFIG_SCLK_DIV )
	284	#else
	285	#define CONFIG_CCLK_HZ CONFIG_CLKIN_HZ
	286	#define CONFIG_SCLK_HZ CONFIG_CLKIN_HZ
	287	#endif
	288
6cb142fa WD	289	/*
	290	* Miscellaneous configurable options
	291	*/
8e7b703a	292	#define CFG_HZ 1000 /* 1ms time tick */
6cb142fa	293
8e7b703a	294	#define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
6cb142fa WD	295	#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN)
	296	#define CFG_GBL_DATA_SIZE 0x4000
	297	#define CFG_GBL_DATA_ADDR (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE)
	298	#define CONFIG_STACKBASE (CFG_GBL_DATA_ADDR - 4)
	299
	300	#define CFG_LARGE_IMAGE_LEN 0x4000000 /* Large Image Length, set to 64 Meg */
	301
	302	#define CONFIG_SHOW_BOOT_PROGRESS 1 /* Show boot progress on LEDs */
	303
	304	/*
	305	* Stack sizes
	306	*/
8e7b703a	307	#define CONFIG_STACKSIZE (1281024) / regular stack */
6cb142fa WD	308
	309	/*
	310	* FLASH organization and environment definitions
	311	*/
8e7b703a	312	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6cb142fa WD	313
6cb142fa WD	314	/* 0xFF, 0xBBC3BBc3, 0x99B39983 */
8e7b703a WD	315	/*#define AMGCTLVAL (AMBEN_P0 \| AMBEN_P1 \| AMBEN_P2 \| AMCKEN)
	316	#define AMBCTL0VAL (B1WAT_11 \| B1RAT_11 \| B1HT_3 \| B1ST_4 \| B1TT_4 \| B1RDYPOL \| \
	317	B1RDYEN \| B0WAT_11 \| B0RAT_11 \| B0HT_3 \| B0ST_4 \| B0TT_4 \| B0RDYPOL \| B0RDYEN)
	318	#define AMBCTL1VAL (B3WAT_9 \| B3RAT_9 \| B3HT_2 \| B3ST_3 \| B3TT_4 \| B3RDYPOL \| \
	319	B3RDYEN \| B2WAT_9 \| B2RAT_9 \| B2HT_2 \| B2ST_4 \| B2TT_4 \| B2RDYPOL \| B2RDYEN)
6cb142fa	320	*/
8e7b703a WD	321	#define AMGCTLVAL 0xFF
	322	#define AMBCTL0VAL 0xBBC3BBC3
	323	#define AMBCTL1VAL 0x99B39983
	324	#define CF_AMBCTL1VAL 0x99B3ffc2
6cb142fa WD	325
	326	#ifdef CONFIG_VDSP
	327	#define ET_EXEC_VDSP 0x8
	328	#define SHT_STRTAB_VDSP 0x1
	329	#define ELFSHDRSIZE_VDSP 0x2C
	330	#define VDSP_ENTRY_ADDR 0xFFA00000
	331	#endif
	332
6cb142fa	333	#endif