[people/ms/u-boot.git] / include / configs / stxgp3.h

/*
 * (C) Copyright 2003 Embedded Edge, LLC
 * Dan Malek <dan@embeddededge.com>
 * Copied from ADS85xx.
 * Updates for Silicon Tx GP3 8560 board.
 *
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* mpc8560ads board configuration file */
/* please refer to doc/README.mpc85xx for more info */
/* make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE		*/
#define CONFIG_E500		1	/* BOOKE e500 family	*/
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_STXGP3		1	/* Silicon Tx GPPP board specific*/
#define CONFIG_MPC8560		1

#undef  CONFIG_PCI			/* pci ethernet support	*/
#define CONFIG_TSEC_ENET		/* tsec ethernet support*/
#undef  CONFIG_ETHER_ON_FCC             /* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/* sysclk for MPC85xx
 */

#define CONFIG_SYS_CLK_FREQ     33333333 /* most pci cards are 33Mhz */

/* Blinkin' LEDs for Robert :-)
*/
#define CONFIG_SHOW_ACTIVITY 1

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE                     /* toggle L2 cache         */
#define  CONFIG_BTB                          /* toggle branch predition */

#define CONFIG_BOARD_EARLY_INIT_F   1        /* Call board_pre_init      */
#define CONFIG_RESET_PHY_R	1	/* Call reset_phy()		*/

#undef  CONFIG_SYS_DRAM_TEST                       /* memory test, takes time  */
#define CONFIG_SYS_MEMTEST_START       0x00200000  /* memtest region */
#define CONFIG_SYS_MEMTEST_END         0x00400000


/* Localbus SDRAM is an option, not all boards have it.
 * This address, however, is used to configure a 256M local bus
 * window that includes the Config latch below.
 */
#define CONFIG_SYS_LBC_SDRAM_BASE      0xf0000000      /* Localbus SDRAM */
#define CONFIG_SYS_LBC_SDRAM_SIZE	256		/* LBC SDRAM is 64MB	*/

#define CONFIG_SYS_FLASH_BASE        0xff000000      /* start of FLASH 16M    */
#define CONFIG_SYS_BR0_PRELIM        0xff001801      /* port size 32bit      */

#define CONFIG_SYS_OR0_PRELIM          0xff000ff7      /* 16 MB Flash           */
#define CONFIG_SYS_MAX_FLASH_BANKS	1		/* number of banks	*/
#define CONFIG_SYS_MAX_FLASH_SECT	136		/* sectors per device   */
#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	60000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

/* The configuration latch is Chip Select 1.
 * It's an 8-bit latch in the lower 8 bits of the word.
 */
#define CONFIG_SYS_BR1_PRELIM		0xfc001801	/* 32-bit port */
#define CONFIG_SYS_OR1_PRELIM		0xffff0ff7      /* 64K is enough */
#define CONFIG_SYS_LBC_LCLDEVS_BASE	0xfc000000	/* Base of localbus devices */

#define CONFIG_SYS_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef  CONFIG_SYS_RAMBOOT
#endif

#ifdef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
#else
#define CONFIG_SYS_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
#endif
#define CONFIG_SYS_CCSRBAR             0xfdf00000      /* relocated CCSRBAR    */
#define CONFIG_SYS_CCSRBAR_PHYS	CONFIG_SYS_CCSRBAR	/* physical addr of CCSRBAR */
#define CONFIG_SYS_IMMR		CONFIG_SYS_CCSRBAR	/* PQII uses CONFIG_SYS_IMMR	*/

/* DDR Setup */
#define CONFIG_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#undef  CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_DLL                  /* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */

#undef CONFIG_CLOCKS_IN_MHZ

/* local bus definitions */
#define CONFIG_SYS_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM  */
#define CONFIG_SYS_OR2_PRELIM		0xfc006901
#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq	*/
#define CONFIG_SYS_LBC_LBCR		0x00000000
#define CONFIG_SYS_LBC_LSRT		0x20000000
#define CONFIG_SYS_LBC_MRTPR		0x20000000
#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR       0x60000000      /* Initial RAM address  */
#define CONFIG_SYS_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CONFIG_SYS_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)    /* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(128 * 1024)    /* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_ON_SCC		/* define if console on SCC */
#undef  CONFIG_CONS_NONE		/* define if console on something else */
#define CONFIG_CONS_INDEX       2	/* which serial channel for console */

#define CONFIG_BAUDRATE		38400

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

/* Use the HUSH parser */
#define CONFIG_SYS_HUSH_PARSER
#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
#endif

/*
 * I2C
 */
#define CONFIG_FSL_I2C		/* Use FSL common I2C driver */
#define CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CONFIG_SYS_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CONFIG_SYS_I2C_SLAVE		0x7F
#if 0
#define CONFIG_SYS_I2C_NOPROBES        {0x00}  /* Don't probe these addrs */
#else
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CONFIG_SYS_I2C_NOPROBES
#endif
#define CONFIG_SYS_I2C_OFFSET		0x3000

/* RapdIO Map configuration, mapped 1:1.
*/
#define CONFIG_SYS_RIO_MEM_BASE	0xc0000000
#define CONFIG_SYS_RIO_MEM_PHYS	CONFIG_SYS_RIO_MEM_BASE
#define CONFIG_SYS_RIO_MEM_SIZE	0x200000000	/* 512 M */

/* Standard 8560 PCI addressing, mapped 1:1.
*/
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_BASE	0xe2000000
#define CONFIG_SYS_PCI1_IO_PHYS	CONFIG_SYS_PCI1_IO_BASE
#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16 M */

#if defined(CONFIG_PCI)			/* PCI Ethernet card */

#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#undef CONFIG_EEPRO100
#undef CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
  #define PCI_ENET0_IOADDR	0xe0000000
  #define PCI_ENET0_MEMADDR     0xe0000000
  #define PCI_IDSEL_NUMBER      0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#undef CONFIG_PCI_SCAN_SHOW
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057  /* Motorola */

#endif /* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management		*/

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"

#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		4
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define CONFIG_ETHPRIME		"TSEC0"

#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

#define CONFIG_ETHER_ON_FCC2             /* define if ether on FCC   */
#undef  CONFIG_ETHER_NONE               /* define if ether on something else */
#define CONFIG_ETHER_INDEX      2       /* which channel for ether  */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CONFIG_SYS_CMXFCR_MASK       (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CONFIG_SYS_CMXFCR_VALUE      (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CONFIG_SYS_CPMFCR_RAMTYPE    0
#if 0
  #define CONFIG_SYS_FCC_PSMR          (FCC_PSMR_FDE)
#else
  #define CONFIG_SYS_FCC_PSMR          0
#endif
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif	/* CONFIG_ETHER_INDEX */

/* MDIO is done through the TSEC0 control.
*/
#define CONFIG_MII			/* MII PHY management */
#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/

#endif

/* Environment */
/* We use the top boot sector flash, so we have some 16K sectors for env
 */
#ifndef CONFIG_SYS_RAMBOOT
  #define CONFIG_ENV_IS_IN_FLASH	1
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE + 0x60000)
  #define CONFIG_ENV_SECT_SIZE	0x4000	/* 16K (one top sector) for env */
  #define CONFIG_ENV_SIZE		0x2000
#else
  #define CONFIG_SYS_NO_FLASH		1	/* Flash is not usable now	*/
  #define CONFIG_ENV_IS_NOWHERE	1	/* Store ENV in memory only	*/
  #define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - 0x1000)
  #define CONFIG_ENV_SIZE		0x2000
#endif

#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
#define CONFIG_BOOTCOMMAND	"bootm 0xff000000 0xff100000"
#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_SYS_RAMBOOT)
    #undef CONFIG_CMD_SAVEENV
    #undef CONFIG_CMD_LOADS
#else
    #define CONFIG_CMD_ELF
#endif

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"GPPP=> "	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */
#define CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR		 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR		 00:e0:0c:07:9b:8b
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR		 00:e0:0c:07:9b:8c
#endif

#define CONFIG_SERVERIP		192.168.85.1
#define CONFIG_IPADDR		192.168.85.60
#define CONFIG_GATEWAYIP	192.168.85.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_HOSTNAME		STX_GP3
#define CONFIG_ROOTPATH		/gppproot
#define CONFIG_BOOTFILE		uImage
#define CONFIG_LOADADDR		0x1000000

#endif	/* __CONFIG_H */
Commit	Line	Data
7abf0c58 WD	1	/*
	2	* (C) Copyright 2003 Embedded Edge, LLC
	3	* Dan Malek <dan@embeddededge.com>
	4	* Copied from ADS85xx.
	5	* Updates for Silicon Tx GP3 8560 board.
	6	*
	7	* (C) Copyright 2002,2003 Motorola,Inc.
	8	* Xianghua Xiao <X.Xiao@motorola.com>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	/* mpc8560ads board configuration file */
	30	/* please refer to doc/README.mpc85xx for more info */
	31	/* make sure you change the MAC address and other network params first,
	32	* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
	33	*/
	34
	35	#ifndef __CONFIG_H
	36	#define __CONFIG_H
	37
	38	/* High Level Configuration Options */
	39	#define CONFIG_BOOKE 1 /* BOOKE */
	40	#define CONFIG_E500 1 /* BOOKE e500 family */
	41	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
9c4c5ae3	42	#define CONFIG_CPM2 1 /* has CPM2 */
7abf0c58	43	#define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/
f060054d	44	#define CONFIG_MPC8560 1
7abf0c58	45
53677ef1 WD	46	#undef CONFIG_PCI /* pci ethernet support */
53677ef1 WD	47	#define CONFIG_TSEC_ENET /* tsec ethernet support*/
7abf0c58 WD	48	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
7abf0c58 WD	49	#define CONFIG_ENV_OVERWRITE
9aea9530	50
572b13af	51	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
7abf0c58	52
9aea9530	53	/* sysclk for MPC85xx
7abf0c58	54	*/
7abf0c58 WD	55
	56	#define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */
	57
	58	/* Blinkin' LEDs for Robert :-)
	59	*/
	60	#define CONFIG_SHOW_ACTIVITY 1
	61
9aea9530 WD	62	/*
	63	* These can be toggled for performance analysis, otherwise use default.
	64	*/
7abf0c58	65	#define CONFIG_L2_CACHE /* toggle L2 cache */
9aea9530	66	#define CONFIG_BTB /* toggle branch predition */
7abf0c58	67
9aea9530	68	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
004eca0c	69	#define CONFIG_RESET_PHY_R 1 /* Call reset_phy() */
7abf0c58	70
6d0f6bcf JCPV	71	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	72	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
	73	#define CONFIG_SYS_MEMTEST_END 0x00400000
7abf0c58	74
7abf0c58 WD	75
7abf0c58 WD	76	/* Localbus SDRAM is an option, not all boards have it.
9aea9530 WD	77	* This address, however, is used to configure a 256M local bus
	78	* window that includes the Config latch below.
	79	*/
6d0f6bcf JCPV	80	#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */
6d0f6bcf JCPV	81	#define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
7abf0c58	82
6d0f6bcf JCPV	83	#define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */
6d0f6bcf JCPV	84	#define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
7abf0c58	85
6d0f6bcf JCPV	86	#define CONFIG_SYS_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */
	87	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	88	#define CONFIG_SYS_MAX_FLASH_SECT 136 /* sectors per device */
	89	#undef CONFIG_SYS_FLASH_CHECKSUM
	90	#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */
	91	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
7abf0c58 WD	92
7abf0c58 WD	93	/* The configuration latch is Chip Select 1.
9aea9530	94	* It's an 8-bit latch in the lower 8 bits of the word.
7abf0c58	95	*/
6d0f6bcf JCPV	96	#define CONFIG_SYS_BR1_PRELIM 0xfc001801 /* 32-bit port */
	97	#define CONFIG_SYS_OR1_PRELIM 0xffff0ff7 /* 64K is enough */
	98	#define CONFIG_SYS_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */
7abf0c58	99
6d0f6bcf	100	#define CONFIG_SYS_MONITOR_BASE TEXT_BASE /* start of monitor */
7abf0c58	101
6d0f6bcf JCPV	102	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	103	#define CONFIG_SYS_RAMBOOT
7abf0c58	104	#else
6d0f6bcf	105	#undef CONFIG_SYS_RAMBOOT
7abf0c58 WD	106	#endif
7abf0c58 WD	107
6d0f6bcf JCPV	108	#ifdef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	109	#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
7abf0c58	110	#else
6d0f6bcf	111	#define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
7abf0c58	112	#endif
6d0f6bcf JCPV	113	#define CONFIG_SYS_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */
	114	#define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */
	115	#define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */
7abf0c58	116
c360d9b9 KG	117	/* DDR Setup */
	118	#define CONFIG_FSL_DDR1
	119	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	120	#define CONFIG_DDR_SPD
	121	#undef CONFIG_FSL_DDR_INTERACTIVE
7abf0c58	122
c360d9b9 KG	123	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	124	#define CONFIG_DDR_DLL /* possible DLL fix needed */
	125	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
7abf0c58	126
c360d9b9 KG	127	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
c360d9b9 KG	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	130	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
9aea9530	131
c360d9b9 KG	132	#define CONFIG_NUM_DDR_CONTROLLERS 1
	133	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	134	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	135
	136	/* I2C addresses of SPD EEPROMs */
	137	#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
7abf0c58 WD	138
	139	#undef CONFIG_CLOCKS_IN_MHZ
	140
	141	/* local bus definitions */
6d0f6bcf JCPV	142	#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
	143	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
	144	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
	145	#define CONFIG_SYS_LBC_LBCR 0x00000000
	146	#define CONFIG_SYS_LBC_LSRT 0x20000000
	147	#define CONFIG_SYS_LBC_MRTPR 0x20000000
	148	#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
	149	#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
	150	#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
	151	#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
	152	#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
7abf0c58	153
6d0f6bcf JCPV	154	#define CONFIG_SYS_INIT_RAM_LOCK 1
	155	#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
	156	#define CONFIG_SYS_INIT_RAM_END 0x4000 /* End of used area in RAM */
7abf0c58	157
6d0f6bcf JCPV	158	#define CONFIG_SYS_GBL_DATA_SIZE 128 /* num bytes initial data */
	159	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	160	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
7abf0c58	161
6d0f6bcf JCPV	162	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	163	#define CONFIG_SYS_MALLOC_LEN (128 * 1024) /* Reserved for malloc */
7abf0c58 WD	164
7abf0c58 WD	165	/* Serial Port */
53677ef1 WD	166	#define CONFIG_CONS_ON_SCC /* define if console on SCC */
	167	#undef CONFIG_CONS_NONE /* define if console on something else */
	168	#define CONFIG_CONS_INDEX 2 /* which serial channel for console */
7abf0c58	169
53677ef1	170	#define CONFIG_BAUDRATE 38400
7abf0c58	171
6d0f6bcf	172	#define CONFIG_SYS_BAUDRATE_TABLE \
7abf0c58 WD	173	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	174
	175	/* Use the HUSH parser */
6d0f6bcf JCPV	176	#define CONFIG_SYS_HUSH_PARSER
	177	#ifdef CONFIG_SYS_HUSH_PARSER
	178	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
7abf0c58 WD	179	#endif
7abf0c58 WD	180
20476726 JL	181	/*
	182	* I2C
	183	*/
	184	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
	185	#define CONFIG_HARD_I2C /* I2C with hardware support*/
7abf0c58	186	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
6d0f6bcf JCPV	187	#define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */
6d0f6bcf JCPV	188	#define CONFIG_SYS_I2C_SLAVE 0x7F
7abf0c58	189	#if 0
6d0f6bcf	190	#define CONFIG_SYS_I2C_NOPROBES {0x00} /* Don't probe these addrs */
7abf0c58 WD	191	#else
7abf0c58 WD	192	/* I did the 'if 0' so we could keep the syntax above if ever needed. */
6d0f6bcf	193	#undef CONFIG_SYS_I2C_NOPROBES
7abf0c58	194	#endif
6d0f6bcf	195	#define CONFIG_SYS_I2C_OFFSET 0x3000
7abf0c58	196
9aea9530 WD	197	/* RapdIO Map configuration, mapped 1:1.
9aea9530 WD	198	*/
6d0f6bcf JCPV	199	#define CONFIG_SYS_RIO_MEM_BASE 0xc0000000
	200	#define CONFIG_SYS_RIO_MEM_PHYS CONFIG_SYS_RIO_MEM_BASE
	201	#define CONFIG_SYS_RIO_MEM_SIZE 0x200000000 /* 512 M */
9aea9530 WD	202
	203	/* Standard 8560 PCI addressing, mapped 1:1.
	204	*/
6d0f6bcf JCPV	205	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	206	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	207	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
	208	#define CONFIG_SYS_PCI1_IO_BASE 0xe2000000
	209	#define CONFIG_SYS_PCI1_IO_PHYS CONFIG_SYS_PCI1_IO_BASE
	210	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16 M */
7abf0c58	211
53677ef1	212	#if defined(CONFIG_PCI) /* PCI Ethernet card */
9aea9530	213
7abf0c58	214	#define CONFIG_NET_MULTI
53677ef1	215	#define CONFIG_PCI_PNP /* do pci plug-and-play */
9aea9530 WD	216
	217	#undef CONFIG_EEPRO100
	218	#undef CONFIG_TULIP
	219
	220	#if !defined(CONFIG_PCI_PNP)
53677ef1	221	#define PCI_ENET0_IOADDR 0xe0000000
7abf0c58	222	#define PCI_ENET0_MEMADDR 0xe0000000
53677ef1	223	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
7abf0c58	224	#endif
9aea9530 WD	225
9aea9530 WD	226	#undef CONFIG_PCI_SCAN_SHOW
6d0f6bcf	227	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
9aea9530 WD	228
	229	#endif /* CONFIG_PCI */
	230
	231	#if defined(CONFIG_TSEC_ENET)
	232
	233	#ifndef CONFIG_NET_MULTI
53677ef1	234	#define CONFIG_NET_MULTI 1
9aea9530 WD	235	#endif
9aea9530 WD	236
7abf0c58	237	#define CONFIG_MII 1 /* MII PHY management */
9aea9530	238
255a3577 KP	239	#define CONFIG_TSEC1 1
	240	#define CONFIG_TSEC1_NAME "TSEC0"
	241	#define CONFIG_TSEC2 1
	242	#define CONFIG_TSEC2_NAME "TSEC1"
9aea9530 WD	243
	244	#define TSEC1_PHY_ADDR 2
	245	#define TSEC2_PHY_ADDR 4
	246	#define TSEC1_PHYIDX 0
	247	#define TSEC2_PHYIDX 0
3a79013e AF	248	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	249	#define TSEC2_FLAGS TSEC_GIGABIT
d9b94f28	250	#define CONFIG_ETHPRIME "TSEC0"
9aea9530	251
7abf0c58	252	#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
9aea9530	253
7abf0c58 WD	254	#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
	255	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	256	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
9aea9530 WD	257
9aea9530 WD	258	#if (CONFIG_ETHER_INDEX == 2)
7abf0c58 WD	259	/*
	260	* - Rx-CLK is CLK13
	261	* - Tx-CLK is CLK14
	262	* - Select bus for bd/buffers
	263	* - Full duplex
	264	*/
6d0f6bcf JCPV	265	#define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	266	#define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	267	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
7abf0c58	268	#if 0
6d0f6bcf	269	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
7abf0c58	270	#else
6d0f6bcf	271	#define CONFIG_SYS_FCC_PSMR 0
7abf0c58 WD	272	#endif
7abf0c58 WD	273	#define FETH2_RST 0x01
9aea9530	274	#elif (CONFIG_ETHER_INDEX == 3)
7abf0c58 WD	275	/* need more definitions here for FE3 */
7abf0c58 WD	276	#define FETH3_RST 0x80
53677ef1	277	#endif /* CONFIG_ETHER_INDEX */
9aea9530 WD	278
	279	/* MDIO is done through the TSEC0 control.
	280	*/
7abf0c58 WD	281	#define CONFIG_MII /* MII PHY management */
7abf0c58 WD	282	#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
7abf0c58	283
7abf0c58 WD	284	#endif
	285
	286	/* Environment */
	287	/* We use the top boot sector flash, so we have some 16K sectors for env
7abf0c58	288	*/
6d0f6bcf	289	#ifndef CONFIG_SYS_RAMBOOT
5a1aceb0	290	#define CONFIG_ENV_IS_IN_FLASH 1
6d0f6bcf	291	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE + 0x60000)
0e8d1586 JCPV	292	#define CONFIG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */
0e8d1586 JCPV	293	#define CONFIG_ENV_SIZE 0x2000
7abf0c58	294	#else
6d0f6bcf	295	#define CONFIG_SYS_NO_FLASH 1 /* Flash is not usable now */
93f6d725	296	#define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */
6d0f6bcf	297	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - 0x1000)
0e8d1586	298	#define CONFIG_ENV_SIZE 0x2000
7abf0c58 WD	299	#endif
	300
	301	#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400"
9aea9530	302	#define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000"
7abf0c58 WD	303	#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
	304
	305	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	306	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
7abf0c58	307
079a136c JL	308	/*
	309	* BOOTP options
	310	*/
	311	#define CONFIG_BOOTP_BOOTFILESIZE
	312	#define CONFIG_BOOTP_BOOTPATH
	313	#define CONFIG_BOOTP_GATEWAY
	314	#define CONFIG_BOOTP_HOSTNAME
	315
	316
2835e518 JL	317	/*
	318	* Command line configuration.
	319	*/
	320	#include <config_cmd_default.h>
	321
	322	#define CONFIG_CMD_PING
	323	#define CONFIG_CMD_I2C
199e262e	324	#define CONFIG_CMD_REGINFO
2835e518	325
6d0f6bcf	326	#if defined(CONFIG_SYS_RAMBOOT)
bdab39d3	327	#undef CONFIG_CMD_SAVEENV
2835e518	328	#undef CONFIG_CMD_LOADS
7abf0c58	329	#else
2835e518 JL	330	#define CONFIG_CMD_ELF
	331	#endif
	332
	333	#if defined(CONFIG_PCI)
	334	#define CONFIG_CMD_PCI
7abf0c58	335	#endif
2835e518 JL	336
	337	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
	338	#define CONFIG_CMD_MII
	339	#endif
	340
7abf0c58 WD	341
	342	#undef CONFIG_WATCHDOG /* watchdog disabled */
	343
	344	/*
	345	* Miscellaneous configurable options
	346	*/
6d0f6bcf JCPV	347	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	348	#define CONFIG_SYS_PROMPT "GPPP=> " /* Monitor Command Prompt */
2835e518	349	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	350	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
7abf0c58	351	#else
6d0f6bcf	352	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
7abf0c58	353	#endif
6d0f6bcf JCPV	354	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	355	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	356	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	357	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
	358	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
7abf0c58 WD	359
	360	/*
	361	* For booting Linux, the board info and command line data
	362	* have to be in the first 8 MB of memory, since this is
	363	* the maximum mapped by the Linux kernel during initialization.
	364	*/
6d0f6bcf	365	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
7abf0c58	366
7abf0c58 WD	367	/*
	368	* Internal Definitions
	369	*
	370	* Boot Flags
	371	*/
	372	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	373	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	374
2835e518	375	#if defined(CONFIG_CMD_KGDB)
7abf0c58 WD	376	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	377	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	378	#endif
	379
	380	/Note: change below for your network setting!!! /
	381	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	382	#define CONFIG_HAS_ETH0
53677ef1	383	#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
e2ffd59b	384	#define CONFIG_HAS_ETH1
53677ef1	385	#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
e2ffd59b	386	#define CONFIG_HAS_ETH2
53677ef1	387	#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
7abf0c58 WD	388	#endif
7abf0c58 WD	389
53677ef1 WD	390	#define CONFIG_SERVERIP 192.168.85.1
53677ef1 WD	391	#define CONFIG_IPADDR 192.168.85.60
7abf0c58 WD	392	#define CONFIG_GATEWAYIP 192.168.85.1
7abf0c58 WD	393	#define CONFIG_NETMASK 255.255.255.0
53677ef1 WD	394	#define CONFIG_HOSTNAME STX_GP3
	395	#define CONFIG_ROOTPATH /gppproot
	396	#define CONFIG_BOOTFILE uImage
9aea9530	397	#define CONFIG_LOADADDR 0x1000000
7abf0c58 WD	398
7abf0c58 WD	399	#endif /* __CONFIG_H */