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7abf0c58 WD |
1 | /* |
2 | * (C) Copyright 2003 Embedded Edge, LLC | |
3 | * Dan Malek <dan@embeddededge.com> | |
4 | * Copied from ADS85xx. | |
5 | * Updates for Silicon Tx GP3 8560 board. | |
6 | * | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* mpc8560ads board configuration file */ | |
30 | /* please refer to doc/README.mpc85xx for more info */ | |
31 | /* make sure you change the MAC address and other network params first, | |
32 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
38 | /* High Level Configuration Options */ | |
39 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
40 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
41 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
9c4c5ae3 | 42 | #define CONFIG_CPM2 1 /* has CPM2 */ |
7abf0c58 | 43 | #define CONFIG_STXGP3 1 /* Silicon Tx GPPP board specific*/ |
f060054d | 44 | #define CONFIG_MPC8560 1 |
7abf0c58 | 45 | |
53677ef1 WD |
46 | #undef CONFIG_PCI /* pci ethernet support */ |
47 | #define CONFIG_TSEC_ENET /* tsec ethernet support*/ | |
7abf0c58 WD |
48 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ |
49 | #define CONFIG_ENV_OVERWRITE | |
9aea9530 | 50 | |
572b13af | 51 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
7abf0c58 | 52 | |
9aea9530 | 53 | /* sysclk for MPC85xx |
7abf0c58 | 54 | */ |
7abf0c58 WD |
55 | |
56 | #define CONFIG_SYS_CLK_FREQ 33333333 /* most pci cards are 33Mhz */ | |
57 | ||
58 | /* Blinkin' LEDs for Robert :-) | |
59 | */ | |
60 | #define CONFIG_SHOW_ACTIVITY 1 | |
61 | ||
9aea9530 WD |
62 | /* |
63 | * These can be toggled for performance analysis, otherwise use default. | |
64 | */ | |
7abf0c58 | 65 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
9aea9530 WD |
66 | #define CONFIG_BTB /* toggle branch predition */ |
67 | #define CONFIG_ADDR_STREAMING /* toggle addr streaming */ | |
7abf0c58 | 68 | |
9aea9530 | 69 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
7abf0c58 WD |
70 | |
71 | #undef CFG_DRAM_TEST /* memory test, takes time */ | |
72 | #define CFG_MEMTEST_START 0x00200000 /* memtest region */ | |
73 | #define CFG_MEMTEST_END 0x00400000 | |
74 | ||
7abf0c58 WD |
75 | |
76 | /* Localbus SDRAM is an option, not all boards have it. | |
9aea9530 WD |
77 | * This address, however, is used to configure a 256M local bus |
78 | * window that includes the Config latch below. | |
79 | */ | |
80 | #define CFG_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ | |
81 | #define CFG_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */ | |
7abf0c58 | 82 | |
7abf0c58 WD |
83 | #define CFG_FLASH_BASE 0xff000000 /* start of FLASH 16M */ |
84 | #define CFG_BR0_PRELIM 0xff001801 /* port size 32bit */ | |
7abf0c58 WD |
85 | |
86 | #define CFG_OR0_PRELIM 0xff000ff7 /* 16 MB Flash */ | |
87 | #define CFG_MAX_FLASH_BANKS 1 /* number of banks */ | |
88 | #define CFG_MAX_FLASH_SECT 136 /* sectors per device */ | |
89 | #undef CFG_FLASH_CHECKSUM | |
90 | #define CFG_FLASH_ERASE_TOUT 60000 /* Timeout for Flash Erase (in ms) */ | |
91 | #define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
92 | ||
93 | /* The configuration latch is Chip Select 1. | |
9aea9530 | 94 | * It's an 8-bit latch in the lower 8 bits of the word. |
7abf0c58 WD |
95 | */ |
96 | #define CFG_BR1_PRELIM 0xfc001801 /* 32-bit port */ | |
97 | #define CFG_OR1_PRELIM 0xffff0ff7 /* 64K is enough */ | |
98 | #define CFG_LBC_LCLDEVS_BASE 0xfc000000 /* Base of localbus devices */ | |
99 | ||
53677ef1 | 100 | #define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */ |
7abf0c58 WD |
101 | |
102 | #if (CFG_MONITOR_BASE < CFG_FLASH_BASE) | |
103 | #define CFG_RAMBOOT | |
104 | #else | |
105 | #undef CFG_RAMBOOT | |
106 | #endif | |
107 | ||
108 | #ifdef CFG_RAMBOOT | |
53677ef1 | 109 | #define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ |
7abf0c58 | 110 | #else |
53677ef1 | 111 | #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
7abf0c58 WD |
112 | #endif |
113 | #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ | |
f69766e4 | 114 | #define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ |
7abf0c58 WD |
115 | #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ |
116 | ||
c360d9b9 KG |
117 | /* DDR Setup */ |
118 | #define CONFIG_FSL_DDR1 | |
119 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
120 | #define CONFIG_DDR_SPD | |
121 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
7abf0c58 | 122 | |
c360d9b9 KG |
123 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
124 | #define CONFIG_DDR_DLL /* possible DLL fix needed */ | |
125 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ | |
7abf0c58 | 126 | |
c360d9b9 KG |
127 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
128 | ||
129 | #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ | |
9aea9530 WD |
130 | #define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE |
131 | ||
c360d9b9 KG |
132 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
133 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
134 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
135 | ||
136 | /* I2C addresses of SPD EEPROMs */ | |
137 | #define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ | |
7abf0c58 WD |
138 | |
139 | #undef CONFIG_CLOCKS_IN_MHZ | |
140 | ||
141 | /* local bus definitions */ | |
142 | #define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ | |
143 | #define CFG_OR2_PRELIM 0xfc006901 | |
53677ef1 | 144 | #define CFG_LBC_LCRR 0x00030004 /* local bus freq */ |
7abf0c58 WD |
145 | #define CFG_LBC_LBCR 0x00000000 |
146 | #define CFG_LBC_LSRT 0x20000000 | |
147 | #define CFG_LBC_MRTPR 0x20000000 | |
148 | #define CFG_LBC_LSDMR_1 0x2861b723 | |
149 | #define CFG_LBC_LSDMR_2 0x0861b723 | |
150 | #define CFG_LBC_LSDMR_3 0x0861b723 | |
151 | #define CFG_LBC_LSDMR_4 0x1861b723 | |
152 | #define CFG_LBC_LSDMR_5 0x4061b723 | |
153 | ||
154 | #define CONFIG_L1_INIT_RAM | |
53677ef1 | 155 | #define CFG_INIT_RAM_LOCK 1 |
7abf0c58 | 156 | #define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ |
53677ef1 | 157 | #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ |
7abf0c58 | 158 | |
53677ef1 | 159 | #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ |
7abf0c58 WD |
160 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) |
161 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
162 | ||
53677ef1 WD |
163 | #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
164 | #define CFG_MALLOC_LEN (128 * 1024) /* Reserved for malloc */ | |
7abf0c58 WD |
165 | |
166 | /* Serial Port */ | |
53677ef1 WD |
167 | #define CONFIG_CONS_ON_SCC /* define if console on SCC */ |
168 | #undef CONFIG_CONS_NONE /* define if console on something else */ | |
169 | #define CONFIG_CONS_INDEX 2 /* which serial channel for console */ | |
7abf0c58 | 170 | |
53677ef1 | 171 | #define CONFIG_BAUDRATE 38400 |
7abf0c58 WD |
172 | |
173 | #define CFG_BAUDRATE_TABLE \ | |
174 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} | |
175 | ||
176 | /* Use the HUSH parser */ | |
177 | #define CFG_HUSH_PARSER | |
178 | #ifdef CFG_HUSH_PARSER | |
179 | #define CFG_PROMPT_HUSH_PS2 "> " | |
180 | #endif | |
181 | ||
20476726 JL |
182 | /* |
183 | * I2C | |
184 | */ | |
185 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ | |
186 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ | |
7abf0c58 WD |
187 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
188 | #define CFG_I2C_SPEED 400000 /* I2C speed and slave address */ | |
189 | #define CFG_I2C_SLAVE 0x7F | |
190 | #if 0 | |
191 | #define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */ | |
192 | #else | |
193 | /* I did the 'if 0' so we could keep the syntax above if ever needed. */ | |
194 | #undef CFG_I2C_NOPROBES | |
195 | #endif | |
20476726 | 196 | #define CFG_I2C_OFFSET 0x3000 |
7abf0c58 | 197 | |
9aea9530 WD |
198 | /* RapdIO Map configuration, mapped 1:1. |
199 | */ | |
200 | #define CFG_RIO_MEM_BASE 0xc0000000 | |
201 | #define CFG_RIO_MEM_PHYS CFG_RIO_MEM_BASE | |
202 | #define CFG_RIO_MEM_SIZE 0x200000000 /* 512 M */ | |
203 | ||
204 | /* Standard 8560 PCI addressing, mapped 1:1. | |
205 | */ | |
206 | #define CFG_PCI1_MEM_BASE 0x80000000 | |
207 | #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE | |
208 | #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
209 | #define CFG_PCI1_IO_BASE 0xe2000000 | |
210 | #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE | |
211 | #define CFG_PCI1_IO_SIZE 0x01000000 /* 16 M */ | |
7abf0c58 | 212 | |
53677ef1 | 213 | #if defined(CONFIG_PCI) /* PCI Ethernet card */ |
9aea9530 | 214 | |
7abf0c58 | 215 | #define CONFIG_NET_MULTI |
53677ef1 | 216 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
9aea9530 WD |
217 | |
218 | #undef CONFIG_EEPRO100 | |
219 | #undef CONFIG_TULIP | |
220 | ||
221 | #if !defined(CONFIG_PCI_PNP) | |
53677ef1 | 222 | #define PCI_ENET0_IOADDR 0xe0000000 |
7abf0c58 | 223 | #define PCI_ENET0_MEMADDR 0xe0000000 |
53677ef1 | 224 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ |
7abf0c58 | 225 | #endif |
9aea9530 WD |
226 | |
227 | #undef CONFIG_PCI_SCAN_SHOW | |
228 | #define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ | |
229 | ||
230 | #endif /* CONFIG_PCI */ | |
231 | ||
232 | #if defined(CONFIG_TSEC_ENET) | |
233 | ||
234 | #ifndef CONFIG_NET_MULTI | |
53677ef1 | 235 | #define CONFIG_NET_MULTI 1 |
9aea9530 WD |
236 | #endif |
237 | ||
7abf0c58 | 238 | #define CONFIG_MII 1 /* MII PHY management */ |
9aea9530 | 239 | |
255a3577 KP |
240 | #define CONFIG_TSEC1 1 |
241 | #define CONFIG_TSEC1_NAME "TSEC0" | |
242 | #define CONFIG_TSEC2 1 | |
243 | #define CONFIG_TSEC2_NAME "TSEC1" | |
9aea9530 WD |
244 | |
245 | #define TSEC1_PHY_ADDR 2 | |
246 | #define TSEC2_PHY_ADDR 4 | |
247 | #define TSEC1_PHYIDX 0 | |
248 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
249 | #define TSEC1_FLAGS TSEC_GIGABIT |
250 | #define TSEC2_FLAGS TSEC_GIGABIT | |
d9b94f28 | 251 | #define CONFIG_ETHPRIME "TSEC0" |
9aea9530 | 252 | |
7abf0c58 | 253 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ |
9aea9530 | 254 | |
7abf0c58 WD |
255 | #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ |
256 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
257 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
9aea9530 WD |
258 | |
259 | #if (CONFIG_ETHER_INDEX == 2) | |
7abf0c58 WD |
260 | /* |
261 | * - Rx-CLK is CLK13 | |
262 | * - Tx-CLK is CLK14 | |
263 | * - Select bus for bd/buffers | |
264 | * - Full duplex | |
265 | */ | |
266 | #define CFG_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) | |
267 | #define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
268 | #define CFG_CPMFCR_RAMTYPE 0 | |
269 | #if 0 | |
270 | #define CFG_FCC_PSMR (FCC_PSMR_FDE) | |
271 | #else | |
272 | #define CFG_FCC_PSMR 0 | |
273 | #endif | |
274 | #define FETH2_RST 0x01 | |
9aea9530 | 275 | #elif (CONFIG_ETHER_INDEX == 3) |
7abf0c58 WD |
276 | /* need more definitions here for FE3 */ |
277 | #define FETH3_RST 0x80 | |
53677ef1 | 278 | #endif /* CONFIG_ETHER_INDEX */ |
9aea9530 WD |
279 | |
280 | /* MDIO is done through the TSEC0 control. | |
281 | */ | |
7abf0c58 WD |
282 | #define CONFIG_MII /* MII PHY management */ |
283 | #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
7abf0c58 | 284 | |
7abf0c58 WD |
285 | #endif |
286 | ||
287 | /* Environment */ | |
288 | /* We use the top boot sector flash, so we have some 16K sectors for env | |
7abf0c58 WD |
289 | */ |
290 | #ifndef CFG_RAMBOOT | |
5a1aceb0 | 291 | #define CONFIG_ENV_IS_IN_FLASH 1 |
7abf0c58 WD |
292 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE + 0x60000) |
293 | #define CFG_ENV_SECT_SIZE 0x4000 /* 16K (one top sector) for env */ | |
7abf0c58 WD |
294 | #define CFG_ENV_SIZE 0x2000 |
295 | #else | |
9aea9530 | 296 | #define CFG_NO_FLASH 1 /* Flash is not usable now */ |
93f6d725 | 297 | #define CONFIG_ENV_IS_NOWHERE 1 /* Store ENV in memory only */ |
9aea9530 WD |
298 | #define CFG_ENV_ADDR (CFG_MONITOR_BASE - 0x1000) |
299 | #define CFG_ENV_SIZE 0x2000 | |
7abf0c58 WD |
300 | #endif |
301 | ||
302 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,38400" | |
9aea9530 | 303 | #define CONFIG_BOOTCOMMAND "bootm 0xff000000 0xff100000" |
7abf0c58 WD |
304 | #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ |
305 | ||
306 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
307 | #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ | |
308 | ||
079a136c JL |
309 | /* |
310 | * BOOTP options | |
311 | */ | |
312 | #define CONFIG_BOOTP_BOOTFILESIZE | |
313 | #define CONFIG_BOOTP_BOOTPATH | |
314 | #define CONFIG_BOOTP_GATEWAY | |
315 | #define CONFIG_BOOTP_HOSTNAME | |
316 | ||
317 | ||
2835e518 JL |
318 | /* |
319 | * Command line configuration. | |
320 | */ | |
321 | #include <config_cmd_default.h> | |
322 | ||
323 | #define CONFIG_CMD_PING | |
324 | #define CONFIG_CMD_I2C | |
325 | ||
9aea9530 | 326 | #if defined(CFG_RAMBOOT) |
2835e518 JL |
327 | #undef CONFIG_CMD_ENV |
328 | #undef CONFIG_CMD_LOADS | |
7abf0c58 | 329 | #else |
2835e518 JL |
330 | #define CONFIG_CMD_ELF |
331 | #endif | |
332 | ||
333 | #if defined(CONFIG_PCI) | |
334 | #define CONFIG_CMD_PCI | |
7abf0c58 | 335 | #endif |
2835e518 JL |
336 | |
337 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
338 | #define CONFIG_CMD_MII | |
339 | #endif | |
340 | ||
7abf0c58 WD |
341 | |
342 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
343 | ||
344 | /* | |
345 | * Miscellaneous configurable options | |
346 | */ | |
347 | #define CFG_LONGHELP /* undef to save memory */ | |
348 | #define CFG_PROMPT "GPPP=> " /* Monitor Command Prompt */ | |
2835e518 | 349 | #if defined(CONFIG_CMD_KGDB) |
7abf0c58 WD |
350 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
351 | #else | |
352 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
353 | #endif | |
354 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
355 | #define CFG_MAXARGS 16 /* max number of command args */ | |
356 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
357 | #define CFG_LOAD_ADDR 0x1000000 /* default load address */ | |
358 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
359 | ||
360 | /* | |
361 | * For booting Linux, the board info and command line data | |
362 | * have to be in the first 8 MB of memory, since this is | |
363 | * the maximum mapped by the Linux kernel during initialization. | |
364 | */ | |
365 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
366 | ||
7abf0c58 WD |
367 | /* |
368 | * Internal Definitions | |
369 | * | |
370 | * Boot Flags | |
371 | */ | |
372 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
373 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
374 | ||
2835e518 | 375 | #if defined(CONFIG_CMD_KGDB) |
7abf0c58 WD |
376 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
377 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
378 | #endif | |
379 | ||
380 | /*Note: change below for your network setting!!! */ | |
381 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
10327dc5 | 382 | #define CONFIG_HAS_ETH0 |
53677ef1 | 383 | #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a |
e2ffd59b | 384 | #define CONFIG_HAS_ETH1 |
53677ef1 | 385 | #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b |
e2ffd59b | 386 | #define CONFIG_HAS_ETH2 |
53677ef1 | 387 | #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c |
7abf0c58 WD |
388 | #endif |
389 | ||
53677ef1 WD |
390 | #define CONFIG_SERVERIP 192.168.85.1 |
391 | #define CONFIG_IPADDR 192.168.85.60 | |
7abf0c58 WD |
392 | #define CONFIG_GATEWAYIP 192.168.85.1 |
393 | #define CONFIG_NETMASK 255.255.255.0 | |
53677ef1 WD |
394 | #define CONFIG_HOSTNAME STX_GP3 |
395 | #define CONFIG_ROOTPATH /gppproot | |
396 | #define CONFIG_BOOTFILE uImage | |
9aea9530 | 397 | #define CONFIG_LOADADDR 0x1000000 |
7abf0c58 WD |
398 | |
399 | #endif /* __CONFIG_H */ |