[people/ms/u-boot.git] / include / configs / stxssa.h

/*
 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
 * Dan Malek <dan@embeddedalley.com>
 * Copied from STx GP3.
 * Updates for Silicon Tx GP3 SSA board.
 *
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/* mpc8560ads board configuration file */
/* please refer to doc/README.mpc85xx for more info */
/* make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE		*/
#define CONFIG_E500		1	/* BOOKE e500 family	*/
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_STXSSA		1	/* Silicon Tx GPPP SSA board specific*/
#define CONFIG_MPC8560		1

#define	CONFIG_SYS_TEXT_BASE	0xFFF80000

#define CONFIG_PCI			/* PCI ethernet support	*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_TSEC_ENET		/* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE

#define CONFIG_FSL_LAW		1	/* Use common FSL init code */

/* sysclk for MPC85xx
 */

#define CONFIG_SYS_CLK_FREQ	33000000 /* most pci cards are 33Mhz */

/* Blinkin' LEDs for Robert :-)
*/
#define CONFIG_SHOW_ACTIVITY 1

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE				/* toggle L2 cache	       */
#define  CONFIG_BTB				/* toggle branch predition */

#define CONFIG_BOARD_EARLY_INIT_F   1		/* Call board_pre_init	 */

#undef	CONFIG_SYS_DRAM_TEST				/* memory test, takes time	*/
#define CONFIG_SYS_MEMTEST_START	0x00200000	/* memtest region */
#define CONFIG_SYS_MEMTEST_END		0x00400000


/* Localbus connector.	There are many options that can be
 * connected here, including sdram or lots of flash.
 * This address, however, is used to configure a 256M local bus
 * window that includes the Config latch below.
 */
#define CONFIG_SYS_LBC_OPTION_BASE	0xF0000000	/* Localbus Extension */
#define CONFIG_SYS_LBC_OPTION_SIZE	256		/* 256MB */

/* There are various flash options used, we configure for the largest,
 * which is 64Mbytes.  The CFI works fine and will discover the proper
 * sizes.
 */
#ifdef CONFIG_STXSSA_4M
#define CONFIG_SYS_FLASH_BASE		0xFFC00000	/* start of  4 MiB flash */
#else
#define CONFIG_SYS_FLASH_BASE		0xFC000000	/* start of 64 MiB flash */
#endif
#define CONFIG_SYS_BR0_PRELIM	(CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit	 */
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_FLASH_BASE | 0x0FF7)

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	1	/* max number of memory banks	*/

#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }

#define CONFIG_SYS_FLASH_PROTECTION

/* The configuration latch is Chip Select 1.
 * It's an 8-bit latch in the lower 8 bits of the word.
 */
#define CONFIG_SYS_LBC_CFGLATCH_BASE	0xFB000000	/* Base of config latch */
#define CONFIG_SYS_BR1_PRELIM		0xFB001801	/* 32-bit port */
#define CONFIG_SYS_OR1_PRELIM		0xFFFF0FF7	/* 64K is enough */

#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_TEXT_BASE	/* start of monitor	*/

#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
#define CONFIG_SYS_RAMBOOT
#else
#undef	CONFIG_SYS_RAMBOOT
#endif

#ifdef CONFIG_SYS_RAMBOOT
#define CONFIG_SYS_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
#endif

#define CONFIG_SYS_CCSRBAR		0xe0000000
#define CONFIG_SYS_CCSRBAR_PHYS_LOW	CONFIG_SYS_CCSRBAR

/* DDR Setup */
#define CONFIG_SYS_FSL_DDR1
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup*/
#define CONFIG_DDR_SPD
#undef CONFIG_FSL_DDR_INTERACTIVE

#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */

#define CONFIG_MEM_INIT_VALUE		0xDeadBeef

#define CONFIG_SYS_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory*/
#define CONFIG_SYS_SDRAM_BASE		CONFIG_SYS_DDR_SDRAM_BASE

#define CONFIG_NUM_DDR_CONTROLLERS	1
#define CONFIG_DIMM_SLOTS_PER_CTLR	1
#define CONFIG_CHIP_SELECTS_PER_CTRL	(2 * CONFIG_DIMM_SLOTS_PER_CTLR)

/* I2C addresses of SPD EEPROMs */
#define SPD_EEPROM_ADDRESS	0x54	/* CTLR 0 DIMM 0 */

#undef CONFIG_CLOCKS_IN_MHZ

/* local bus definitions */
#define CONFIG_SYS_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
#define CONFIG_SYS_OR2_PRELIM		0xfc006901
#define CONFIG_SYS_LBC_LCRR		0x00030004	/* local bus freq	*/
#define CONFIG_SYS_LBC_LBCR		0x00000000
#define CONFIG_SYS_LBC_LSRT		0x20000000
#define CONFIG_SYS_LBC_MRTPR		0x20000000
#define CONFIG_SYS_LBC_LSDMR_1		0x2861b723
#define CONFIG_SYS_LBC_LSDMR_2		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_3		0x0861b723
#define CONFIG_SYS_LBC_LSDMR_4		0x1861b723
#define CONFIG_SYS_LBC_LSDMR_5		0x4061b723

#define CONFIG_SYS_INIT_RAM_LOCK	1
#define CONFIG_SYS_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x4000		/* Size of used area in RAM */

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

#define CONFIG_SYS_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CONFIG_SYS_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     2
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	1
#define CONFIG_SYS_NS16550_CLK		get_bus_freq(0)

#define CONFIG_SYS_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CONFIG_SYS_NS16550_COM1	(CONFIG_SYS_CCSRBAR+0x4500)
#define CONFIG_SYS_NS16550_COM2	(CONFIG_SYS_CCSRBAR+0x4600)

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CONFIG_AUTO_COMPLETE	1	/* add autocompletion support   */
#define CONFIG_SYS_HUSH_PARSER		1	/* Use the HUSH parser		*/

/* pass open firmware flat tree */
#define CONFIG_OF_LIBFDT		1
#define CONFIG_OF_BOARD_SETUP		1
#define CONFIG_OF_STDOUT_VIA_ALIAS	1

/*
 * I2C
 */
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_FSL
#define CONFIG_SYS_FSL_I2C_SPEED	400000
#define CONFIG_SYS_FSL_I2C_SLAVE	0x7F
#define CONFIG_SYS_FSL_I2C_OFFSET	0x3000
#undef CONFIG_SYS_I2C_NOPROBES

/* I2C RTC */
#define CONFIG_RTC_DS1337		/* This is really a DS1339 RTC	*/
#define CONFIG_SYS_I2C_RTC_ADDR	0x68	/* at address 0x68		*/

/* I2C EEPROM.	AT24C32, we keep our environment in here.
*/
#define CONFIG_SYS_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN		2
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	20

/*
 * Standard 8555 PCI mapping.
 * Addresses are mapped 1-1.
 */
#define CONFIG_SYS_PCI1_MEM_BASE	0x80000000
#define CONFIG_SYS_PCI1_MEM_PHYS	CONFIG_SYS_PCI1_MEM_BASE
#define CONFIG_SYS_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI1_IO_BASE	0x00000000
#define CONFIG_SYS_PCI1_IO_PHYS	0xe2000000
#define CONFIG_SYS_PCI1_IO_SIZE	0x01000000	/* 16M */

#define CONFIG_SYS_PCI2_MEM_BASE	0xa0000000
#define CONFIG_SYS_PCI2_MEM_PHYS	CONFIG_SYS_PCI2_MEM_BASE
#define CONFIG_SYS_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CONFIG_SYS_PCI2_IO_BASE	0x00000000
#define CONFIG_SYS_PCI2_IO_PHYS	0xe3000000
#define CONFIG_SYS_PCI2_IO_SIZE	0x01000000	/* 16M */

#if defined(CONFIG_PCI)			/* PCI Ethernet card */
#define CONFIG_MPC85XX_PCI2	1
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#define CONFIG_EEPRO100
#define CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
  #define PCI_ENET0_IOADDR	0xe0000000
  #define PCI_ENET0_MEMADDR	0xe0000000
  #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#define CONFIG_PCI_SCAN_SHOW
#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */

#endif /* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#define CONFIG_MII		1	/* MII PHY management		*/

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"

#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		4
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define CONFIG_ETHPRIME		"TSEC0"

#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

#define CONFIG_ETHER_ON_FCC2		/* define if ether on FCC   */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CONFIG_SYS_CMXFCR_MASK2	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CONFIG_SYS_CMXFCR_VALUE2	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CONFIG_SYS_CPMFCR_RAMTYPE	0
#if 0
  #define CONFIG_SYS_FCC_PSMR		(FCC_PSMR_FDE)
#else
  #define CONFIG_SYS_FCC_PSMR		0
#endif
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif					/* CONFIG_ETHER_INDEX */

/* MDIO is done through the TSEC0 control.
*/
#define CONFIG_MII			/* MII PHY management */
#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/

#endif

/* Environment - default config is in flash, see below */
#if 0	/* in EEPROM */
# define CONFIG_ENV_IS_IN_EEPROM	1
# define CONFIG_ENV_OFFSET		0
# define CONFIG_ENV_SIZE		2048
#else	/* in flash */
# define CONFIG_ENV_IS_IN_FLASH	1
# ifdef CONFIG_STXSSA_4M
#  define CONFIG_ENV_SECT_SIZE	0x20000
# else	/* default configuration - 64 MiB flash */
#  define CONFIG_ENV_SECT_SIZE	0x40000
# endif
# define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
# define CONFIG_ENV_SIZE		0x4000
# define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
# define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CONFIG_SYS_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DATE
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_EEPROM
#define CONFIG_CMD_I2C
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING
#define CONFIG_CMD_SNTP
#define CONFIG_CMD_REGINFO

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif

#if defined(CONFIG_SYS_RAMBOOT)
    #undef CONFIG_CMD_SAVEENV
    #undef CONFIG_CMD_LOADS
#else
    #define CONFIG_CMD_ELF
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define CONFIG_SYS_PROMPT	"SSA=> "	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/
#define CONFIG_SYS_LOAD_ADDR	0x1000000	/* default load address */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CONFIG_SYS_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#endif

/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
#endif

/*
 * Environment in EEPROM is compatible with different flash sector sizes,
 * but only little space is available, so we use a very simple setup.
 * With environment in flash, we use a more powerful default configuration.
 */
#ifdef CONFIG_ENV_IS_IN_EEPROM		/* use restricted "standard" environment */

#define CONFIG_BAUDRATE		38400

#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
#define CONFIG_BOOTCOMMAND	"bootm 0xffc00000 0xffd00000"
#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
#define CONFIG_SERVERIP		192.168.85.1
#define CONFIG_IPADDR		192.168.85.60
#define CONFIG_GATEWAYIP	192.168.85.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_HOSTNAME		STX_SSA
#define CONFIG_ROOTPATH		"/gppproot"
#define CONFIG_BOOTFILE		"uImage"
#define CONFIG_LOADADDR		0x1000000

#else /* ENV IS IN FLASH		-- use a full-blown envionment */

#define CONFIG_BAUDRATE		115200

#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"hostname=gp3ssa\0"						\
	"bootfile=/tftpboot/gp3ssa/uImage\0"				\
	"loadaddr=400000\0"						\
	"netdev=eth0\0"							\
	"consdev=ttyS1\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$serverip:$rootpath\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
		":$hostname:$netdev:off panic=1\0"			\
	"addcons=setenv bootargs $bootargs "				\
		"console=$consdev,$baudrate\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm $kernel_addr\0"					\
	"flash_self=run ramargs addip addcons;"				\
		"bootm $kernel_addr $ramdisk_addr\0"			\
	"net_nfs=tftp $loadaddr $bootfile;"				\
		"run nfsargs addip addcons;bootm\0"			\
	"rootpath=/opt/eldk/ppc_85xx\0"					\
	"kernel_addr=FC000000\0"					\
	"ramdisk_addr=FC200000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#endif	/* CONFIG_ENV_IS_IN_EEPROM */

#endif	/* __CONFIG_H */
Commit	Line	Data
35171dc0 DM	1	/*
	2	* (C) Copyright 2005 Embedded Alley Solutions, Inc.
	3	* Dan Malek <dan@embeddedalley.com>
	4	* Copied from STx GP3.
	5	* Updates for Silicon Tx GP3 SSA board.
	6	*
	7	* (C) Copyright 2002,2003 Motorola,Inc.
	8	* Xianghua Xiao <X.Xiao@motorola.com>
	9	*
3765b3e7	10	* SPDX-License-Identifier: GPL-2.0+
35171dc0 DM	11	*/
	12
	13	/* mpc8560ads board configuration file */
	14	/* please refer to doc/README.mpc85xx for more info */
	15	/* make sure you change the MAC address and other network params first,
	16	* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
	17	*/
	18
	19	#ifndef __CONFIG_H
	20	#define __CONFIG_H
	21
	22	/* High Level Configuration Options */
	23	#define CONFIG_BOOKE 1 /* BOOKE */
	24	#define CONFIG_E500 1 /* BOOKE e500 family */
35171dc0 DM	25	#define CONFIG_CPM2 1 /* has CPM2 */
35171dc0 DM	26	#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
f060054d	27	#define CONFIG_MPC8560 1
35171dc0	28
28415b62	29	#define CONFIG_SYS_TEXT_BASE 0xFFF80000
2ae18241	30
f1152f8c	31	#define CONFIG_PCI /* PCI ethernet support */
842033e6	32	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
f1152f8c WD	33	#define CONFIG_TSEC_ENET /* tsec ethernet support*/
f1152f8c WD	34	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
35171dc0	35	#define CONFIG_ENV_OVERWRITE
35171dc0	36
572b13af	37	#define CONFIG_FSL_LAW 1 /* Use common FSL init code */
35171dc0 DM	38
	39	/* sysclk for MPC85xx
	40	*/
	41
f1152f8c	42	#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
35171dc0 DM	43
	44	/* Blinkin' LEDs for Robert :-)
	45	*/
	46	#define CONFIG_SHOW_ACTIVITY 1
	47
	48	/*
	49	* These can be toggled for performance analysis, otherwise use default.
	50	*/
f1152f8c WD	51	#define CONFIG_L2_CACHE /* toggle L2 cache */
f1152f8c WD	52	#define CONFIG_BTB /* toggle branch predition */
35171dc0	53
53677ef1	54	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
35171dc0	55
6d0f6bcf JCPV	56	#undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */
	57	#define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */
	58	#define CONFIG_SYS_MEMTEST_END 0x00400000
35171dc0 DM	59
35171dc0 DM	60
f1152f8c	61	/* Localbus connector. There are many options that can be
35171dc0 DM	62	* connected here, including sdram or lots of flash.
	63	* This address, however, is used to configure a 256M local bus
	64	* window that includes the Config latch below.
	65	*/
6d0f6bcf JCPV	66	#define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
6d0f6bcf JCPV	67	#define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */
35171dc0 DM	68
	69	/* There are various flash options used, we configure for the largest,
	70	* which is 64Mbytes. The CFI works fine and will discover the proper
	71	* sizes.
	72	*/
ee152983	73	#ifdef CONFIG_STXSSA_4M
6d0f6bcf	74	#define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
ee152983	75	#else
6d0f6bcf	76	#define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
ee152983	77	#endif
6d0f6bcf JCPV	78	#define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE \| 0x1801) /* port size 32bit */
6d0f6bcf JCPV	79	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE \| 0x0FF7)
35171dc0	80
6d0f6bcf	81	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	82	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	83	#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
	84	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	85	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */
35171dc0	86
6d0f6bcf	87	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE }
35171dc0	88
6d0f6bcf	89	#define CONFIG_SYS_FLASH_PROTECTION
35171dc0 DM	90
	91	/* The configuration latch is Chip Select 1.
	92	* It's an 8-bit latch in the lower 8 bits of the word.
	93	*/
6d0f6bcf JCPV	94	#define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
	95	#define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */
	96	#define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
35171dc0	97
14d0a02a	98	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */
35171dc0	99
6d0f6bcf JCPV	100	#if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE)
6d0f6bcf JCPV	101	#define CONFIG_SYS_RAMBOOT
35171dc0	102	#else
6d0f6bcf	103	#undef CONFIG_SYS_RAMBOOT
35171dc0 DM	104	#endif
35171dc0 DM	105
6d0f6bcf JCPV	106	#ifdef CONFIG_SYS_RAMBOOT
6d0f6bcf JCPV	107	#define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
35171dc0	108	#endif
e46fedfe TT	109
	110	#define CONFIG_SYS_CCSRBAR 0xe0000000
	111	#define CONFIG_SYS_CCSRBAR_PHYS_LOW CONFIG_SYS_CCSRBAR
35171dc0	112
0e7927db	113	/* DDR Setup */
5614e71b	114	#define CONFIG_SYS_FSL_DDR1
0e7927db KG	115	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/
	116	#define CONFIG_DDR_SPD
	117	#undef CONFIG_FSL_DDR_INTERACTIVE
35171dc0	118
0e7927db	119	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
0e7927db	120	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
35171dc0	121
0e7927db KG	122	#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
0e7927db KG	123
6d0f6bcf JCPV	124	#define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/
6d0f6bcf JCPV	125	#define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE
35171dc0	126
0e7927db KG	127	#define CONFIG_NUM_DDR_CONTROLLERS 1
	128	#define CONFIG_DIMM_SLOTS_PER_CTLR 1
	129	#define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR)
	130
	131	/* I2C addresses of SPD EEPROMs */
	132	#define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */
35171dc0 DM	133
	134	#undef CONFIG_CLOCKS_IN_MHZ
	135
	136	/* local bus definitions */
6d0f6bcf JCPV	137	#define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
	138	#define CONFIG_SYS_OR2_PRELIM 0xfc006901
	139	#define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */
	140	#define CONFIG_SYS_LBC_LBCR 0x00000000
	141	#define CONFIG_SYS_LBC_LSRT 0x20000000
	142	#define CONFIG_SYS_LBC_MRTPR 0x20000000
	143	#define CONFIG_SYS_LBC_LSDMR_1 0x2861b723
	144	#define CONFIG_SYS_LBC_LSDMR_2 0x0861b723
	145	#define CONFIG_SYS_LBC_LSDMR_3 0x0861b723
	146	#define CONFIG_SYS_LBC_LSDMR_4 0x1861b723
	147	#define CONFIG_SYS_LBC_LSDMR_5 0x4061b723
35171dc0	148
6d0f6bcf JCPV	149	#define CONFIG_SYS_INIT_RAM_LOCK 1
6d0f6bcf JCPV	150	#define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
553f0982	151	#define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */
35171dc0	152
25ddd1fb	153	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	154	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
35171dc0	155
6d0f6bcf JCPV	156	#define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
6d0f6bcf JCPV	157	#define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
35171dc0 DM	158
	159	/* Serial Port */
	160	#define CONFIG_CONS_INDEX 2
6d0f6bcf JCPV	161	#define CONFIG_SYS_NS16550
	162	#define CONFIG_SYS_NS16550_SERIAL
	163	#define CONFIG_SYS_NS16550_REG_SIZE 1
	164	#define CONFIG_SYS_NS16550_CLK get_bus_freq(0)
35171dc0	165
6d0f6bcf	166	#define CONFIG_SYS_BAUDRATE_TABLE \
35171dc0 DM	167	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
35171dc0 DM	168
6d0f6bcf JCPV	169	#define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500)
6d0f6bcf JCPV	170	#define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600)
35171dc0	171
c64a89d6	172	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
5be58f5f	173	#define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */
6d0f6bcf	174	#define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */
35171dc0	175
28415b62 WD	176	/* pass open firmware flat tree */
	177	#define CONFIG_OF_LIBFDT 1
	178	#define CONFIG_OF_BOARD_SETUP 1
	179	#define CONFIG_OF_STDOUT_VIA_ALIAS 1
	180
e1893815 WD	181	/*
	182	* I2C
	183	*/
00f792e0 HS	184	#define CONFIG_SYS_I2C
	185	#define CONFIG_SYS_I2C_FSL
	186	#define CONFIG_SYS_FSL_I2C_SPEED 400000
	187	#define CONFIG_SYS_FSL_I2C_SLAVE 0x7F
	188	#define CONFIG_SYS_FSL_I2C_OFFSET 0x3000
6d0f6bcf	189	#undef CONFIG_SYS_I2C_NOPROBES
35171dc0	190
e1893815 WD	191	/* I2C RTC */
e1893815 WD	192	#define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */
6d0f6bcf	193	#define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */
e1893815	194
f1152f8c	195	/* I2C EEPROM. AT24C32, we keep our environment in here.
35171dc0	196	*/
6d0f6bcf JCPV	197	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */
	198	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2
	199	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	200	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20
35171dc0 DM	201
	202	/*
	203	* Standard 8555 PCI mapping.
	204	* Addresses are mapped 1-1.
	205	*/
6d0f6bcf JCPV	206	#define CONFIG_SYS_PCI1_MEM_BASE 0x80000000
	207	#define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE
	208	#define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */
	209	#define CONFIG_SYS_PCI1_IO_BASE 0x00000000
	210	#define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000
	211	#define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */
	212
	213	#define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000
	214	#define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE
	215	#define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */
	216	#define CONFIG_SYS_PCI2_IO_BASE 0x00000000
	217	#define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000
	218	#define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */
35171dc0	219
53677ef1	220	#if defined(CONFIG_PCI) /* PCI Ethernet card */
38ad82da	221	#define CONFIG_MPC85XX_PCI2 1
f1152f8c	222	#define CONFIG_PCI_PNP /* do pci plug-and-play */
35171dc0	223
f1152f8c WD	224	#define CONFIG_EEPRO100
f1152f8c WD	225	#define CONFIG_TULIP
35171dc0 DM	226
35171dc0 DM	227	#if !defined(CONFIG_PCI_PNP)
f1152f8c WD	228	#define PCI_ENET0_IOADDR 0xe0000000
	229	#define PCI_ENET0_MEMADDR 0xe0000000
	230	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
35171dc0 DM	231	#endif
35171dc0 DM	232
f1152f8c	233	#define CONFIG_PCI_SCAN_SHOW
6d0f6bcf	234	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
35171dc0 DM	235
	236	#endif /* CONFIG_PCI */
	237
	238	#if defined(CONFIG_TSEC_ENET)
	239
35171dc0 DM	240	#define CONFIG_MII 1 /* MII PHY management */
35171dc0 DM	241
255a3577 KP	242	#define CONFIG_TSEC1 1
	243	#define CONFIG_TSEC1_NAME "TSEC0"
	244	#define CONFIG_TSEC2 1
	245	#define CONFIG_TSEC2_NAME "TSEC1"
35171dc0 DM	246
	247	#define TSEC1_PHY_ADDR 2
	248	#define TSEC2_PHY_ADDR 4
	249	#define TSEC1_PHYIDX 0
	250	#define TSEC2_PHYIDX 0
3a79013e AF	251	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	252	#define TSEC2_FLAGS TSEC_GIGABIT
35171dc0 DM	253	#define CONFIG_ETHPRIME "TSEC0"
	254
	255	#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
	256
f1152f8c WD	257	#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
	258	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	259	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
35171dc0 DM	260
	261	#if (CONFIG_ETHER_INDEX == 2)
	262	/*
	263	* - Rx-CLK is CLK13
	264	* - Tx-CLK is CLK14
	265	* - Select bus for bd/buffers
	266	* - Full duplex
	267	*/
d4590da4 MF	268	#define CONFIG_SYS_CMXFCR_MASK2 (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
d4590da4 MF	269	#define CONFIG_SYS_CMXFCR_VALUE2 (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
6d0f6bcf	270	#define CONFIG_SYS_CPMFCR_RAMTYPE 0
35171dc0	271	#if 0
6d0f6bcf	272	#define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE)
35171dc0	273	#else
6d0f6bcf	274	#define CONFIG_SYS_FCC_PSMR 0
35171dc0 DM	275	#endif
	276	#define FETH2_RST 0x01
	277	#elif (CONFIG_ETHER_INDEX == 3)
	278	/* need more definitions here for FE3 */
	279	#define FETH3_RST 0x80
f1152f8c	280	#endif /* CONFIG_ETHER_INDEX */
35171dc0 DM	281
	282	/* MDIO is done through the TSEC0 control.
	283	*/
	284	#define CONFIG_MII /* MII PHY management */
	285	#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
	286
	287	#endif
	288
c64a89d6 WD	289	/* Environment - default config is in flash, see below */
c64a89d6 WD	290	#if 0 /* in EEPROM */
bb1f8b4f	291	# define CONFIG_ENV_IS_IN_EEPROM 1
0e8d1586 JCPV	292	# define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	293	# define CONFIG_ENV_SIZE 2048
c64a89d6	294	#else /* in flash */
5a1aceb0	295	# define CONFIG_ENV_IS_IN_FLASH 1
ee152983	296	# ifdef CONFIG_STXSSA_4M
0e8d1586	297	# define CONFIG_ENV_SECT_SIZE 0x20000
ee152983	298	# else /* default configuration - 64 MiB flash */
0e8d1586	299	# define CONFIG_ENV_SECT_SIZE 0x40000
ee152983	300	# endif
6d0f6bcf	301	# define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	302	# define CONFIG_ENV_SIZE 0x4000
	303	# define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE)
	304	# define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
35171dc0 DM	305	#endif
35171dc0 DM	306
35171dc0	307	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	308	#define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
35171dc0	309
c64a89d6 WD	310	#define CONFIG_TIMESTAMP /* Print image info with ts */
c64a89d6 WD	311
2835e518	312
079a136c JL	313	/*
	314	* BOOTP options
	315	*/
	316	#define CONFIG_BOOTP_BOOTFILESIZE
	317	#define CONFIG_BOOTP_BOOTPATH
	318	#define CONFIG_BOOTP_GATEWAY
	319	#define CONFIG_BOOTP_HOSTNAME
	320
	321
2835e518 JL	322	/*
	323	* Command line configuration.
	324	*/
	325	#include <config_cmd_default.h>
	326
e1893815 WD	327	#define CONFIG_CMD_DATE
	328	#define CONFIG_CMD_DHCP
	329	#define CONFIG_CMD_EEPROM
2835e518	330	#define CONFIG_CMD_I2C
e1893815 WD	331	#define CONFIG_CMD_NFS
	332	#define CONFIG_CMD_PING
	333	#define CONFIG_CMD_SNTP
199e262e	334	#define CONFIG_CMD_REGINFO
2835e518 JL	335
	336	#if defined(CONFIG_PCI)
	337	#define CONFIG_CMD_PCI
	338	#endif
	339
	340	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
	341	#define CONFIG_CMD_MII
	342	#endif
	343
6d0f6bcf	344	#if defined(CONFIG_SYS_RAMBOOT)
bdab39d3	345	#undef CONFIG_CMD_SAVEENV
2835e518	346	#undef CONFIG_CMD_LOADS
35171dc0	347	#else
2835e518	348	#define CONFIG_CMD_ELF
35171dc0	349	#endif
2835e518	350
35171dc0 DM	351
	352	#undef CONFIG_WATCHDOG /* watchdog disabled */
	353
	354	/*
	355	* Miscellaneous configurable options
	356	*/
6d0f6bcf JCPV	357	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	358	#define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */
ef0df52a	359	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	360	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
35171dc0	361	#else
6d0f6bcf	362	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
35171dc0	363	#endif
6d0f6bcf JCPV	364	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	365	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	366	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
	367	#define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */
35171dc0 DM	368
	369	/*
	370	* For booting Linux, the board info and command line data
	371	* have to be in the first 8 MB of memory, since this is
	372	* the maximum mapped by the Linux kernel during initialization.
	373	*/
6d0f6bcf	374	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
35171dc0	375
ef0df52a	376	#if defined(CONFIG_CMD_KGDB)
35171dc0	377	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
35171dc0 DM	378	#endif
	379
	380	/Note: change below for your network setting!!! /
	381	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	382	#define CONFIG_HAS_ETH0
35171dc0 DM	383	#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
	384	#define CONFIG_HAS_ETH1
	385	#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
	386	#define CONFIG_HAS_ETH2
	387	#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
	388	#endif
	389
c64a89d6 WD	390	/*
	391	* Environment in EEPROM is compatible with different flash sector sizes,
	392	* but only little space is available, so we use a very simple setup.
	393	* With environment in flash, we use a more powerful default configuration.
	394	*/
bb1f8b4f	395	#ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
c64a89d6	396
f1152f8c	397	#define CONFIG_BAUDRATE 38400
c64a89d6 WD	398
	399	#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
	400	#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
	401	#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
53677ef1	402	#define CONFIG_SERVERIP 192.168.85.1
f1152f8c	403	#define CONFIG_IPADDR 192.168.85.60
35171dc0 DM	404	#define CONFIG_GATEWAYIP 192.168.85.1
35171dc0 DM	405	#define CONFIG_NETMASK 255.255.255.0
53677ef1	406	#define CONFIG_HOSTNAME STX_SSA
8b3637c6	407	#define CONFIG_ROOTPATH "/gppproot"
b3f44c21	408	#define CONFIG_BOOTFILE "uImage"
35171dc0 DM	409	#define CONFIG_LOADADDR 0x1000000
35171dc0 DM	410
c64a89d6 WD	411	#else /* ENV IS IN FLASH -- use a full-blown envionment */
c64a89d6 WD	412
f1152f8c	413	#define CONFIG_BAUDRATE 115200
c64a89d6 WD	414
	415	#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
	416
	417	#define CONFIG_PREBOOT "echo;" \
	418	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	419	"echo"
	420
	421	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	422
	423	#define CONFIG_EXTRA_ENV_SETTINGS \
	424	"hostname=gp3ssa\0" \
	425	"bootfile=/tftpboot/gp3ssa/uImage\0" \
	426	"loadaddr=400000\0" \
	427	"netdev=eth0\0" \
	428	"consdev=ttyS1\0" \
	429	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	430	"nfsroot=$serverip:$rootpath\0" \
	431	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	432	"addip=setenv bootargs $bootargs " \
	433	"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
	434	":$hostname:$netdev:off panic=1\0" \
	435	"addcons=setenv bootargs $bootargs " \
	436	"console=$consdev,$baudrate\0" \
	437	"flash_nfs=run nfsargs addip addcons;" \
	438	"bootm $kernel_addr\0" \
	439	"flash_self=run ramargs addip addcons;" \
	440	"bootm $kernel_addr $ramdisk_addr\0" \
	441	"net_nfs=tftp $loadaddr $bootfile;" \
	442	"run nfsargs addip addcons;bootm\0" \
	443	"rootpath=/opt/eldk/ppc_85xx\0" \
	444	"kernel_addr=FC000000\0" \
	445	"ramdisk_addr=FC200000\0" \
	446	""
	447	#define CONFIG_BOOTCOMMAND "run flash_self"
	448
bb1f8b4f	449	#endif /* CONFIG_ENV_IS_IN_EEPROM */
c64a89d6	450
35171dc0	451	#endif /* __CONFIG_H */