[people/ms/u-boot.git] / include / configs / stxssa.h

/*
 * (C) Copyright 2005 Embedded Alley Solutions, Inc.
 * Dan Malek <dan@embeddedalley.com>
 * Copied from STx GP3.
 * Updates for Silicon Tx GP3 SSA board.
 *
 * (C) Copyright 2002,2003 Motorola,Inc.
 * Xianghua Xiao <X.Xiao@motorola.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.	 See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/* mpc8560ads board configuration file */
/* please refer to doc/README.mpc85xx for more info */
/* make sure you change the MAC address and other network params first,
 * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* High Level Configuration Options */
#define CONFIG_BOOKE		1	/* BOOKE		*/
#define CONFIG_E500		1	/* BOOKE e500 family	*/
#define CONFIG_MPC85xx		1	/* MPC8540/MPC8560	*/
#define CONFIG_CPM2		1	/* has CPM2 */
#define CONFIG_STXSSA		1	/* Silicon Tx GPPP SSA board specific*/

#define CONFIG_PCI			/* PCI ethernet support	*/
#define CONFIG_TSEC_ENET		/* tsec ethernet support*/
#undef CONFIG_ETHER_ON_FCC		/* cpm FCC ethernet support */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_SPD_EEPROM		/* Use SPD EEPROM for DDR setup */
#undef	CONFIG_DDR_ECC			/* only for ECC DDR module */
#undef CONFIG_DDR_DLL			/* possible DLL fix needed */
#define CONFIG_DDR_2T_TIMING		/* Sets the 2T timing bit */


/* sysclk for MPC85xx
 */

#define CONFIG_SYS_CLK_FREQ	33000000 /* most pci cards are 33Mhz */

/* Blinkin' LEDs for Robert :-)
*/
#define CONFIG_SHOW_ACTIVITY 1

/*
 * These can be toggled for performance analysis, otherwise use default.
 */
#define CONFIG_L2_CACHE				/* toggle L2 cache	       */
#define  CONFIG_BTB				/* toggle branch predition */
#define  CONFIG_ADDR_STREAMING			/* toggle addr streaming	*/

#define CONFIG_BOARD_EARLY_INIT_F   1	     	/* Call board_pre_init	 */

#undef	CFG_DRAM_TEST			    	/* memory test, takes time	*/
#define CFG_MEMTEST_START	0x00200000  	/* memtest region */
#define CFG_MEMTEST_END		0x00400000


/* Localbus connector.	There are many options that can be
 * connected here, including sdram or lots of flash.
 * This address, however, is used to configure a 256M local bus
 * window that includes the Config latch below.
 */
#define CFG_LBC_OPTION_BASE	0xF0000000	/* Localbus Extension */
#define CFG_LBC_OPTION_SIZE	256		/* 256MB */

/* There are various flash options used, we configure for the largest,
 * which is 64Mbytes.  The CFI works fine and will discover the proper
 * sizes.
 */
#ifdef CONFIG_STXSSA_4M
#define CFG_FLASH_BASE		0xFFC00000	/* start of  4 MiB flash */
#else
#define CFG_FLASH_BASE		0xFC000000	/* start of 64 MiB flash */
#endif
#define CFG_BR0_PRELIM	(CFG_FLASH_BASE | 0x1801) /* port size 32bit	 */
#define CFG_OR0_PRELIM	(CFG_FLASH_BASE | 0x0FF7)

#define CFG_FLASH_CFI		1
#define CFG_FLASH_CFI_DRIVER	1
#undef CFG_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
#define CFG_MAX_FLASH_SECT	256	/* max number of sectors on one chip */
#define CFG_MAX_FLASH_BANKS	1	/* max number of memory banks	*/

#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }

#define CFG_FLASH_PROTECTION

/* The configuration latch is Chip Select 1.
 * It's an 8-bit latch in the lower 8 bits of the word.
 */
#define CFG_LBC_CFGLATCH_BASE	0xFB000000	/* Base of config latch */
#define CFG_BR1_PRELIM		0xFB001801	/* 32-bit port */
#define CFG_OR1_PRELIM		0xFFFF0FF7	/* 64K is enough */

#define CFG_MONITOR_BASE	TEXT_BASE	/* start of monitor	*/

#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
#define CFG_RAMBOOT
#else
#undef	CFG_RAMBOOT
#endif

#ifdef CFG_RAMBOOT
#define CFG_CCSRBAR_DEFAULT	0x40000000	/* CCSRBAR by BDI cfg	*/
#else
#define CFG_CCSRBAR_DEFAULT	0xff700000	/* CCSRBAR Default	*/
#endif
#define CFG_CCSRBAR		0xe0000000	/* relocated CCSRBAR	*/
#define CFG_IMMR		CFG_CCSRBAR	/* PQII uses CFG_IMMR	*/


/*
 * DDR Setup
 */

/*
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 */
#define CFG_DDR_SDRAM_BASE	0x00000000	/* DDR is system memory  */
#define CFG_SDRAM_BASE		CFG_DDR_SDRAM_BASE

#define SPD_EEPROM_ADDRESS	0x54		/*  DDR DIMM */

#undef CONFIG_CLOCKS_IN_MHZ

/* local bus definitions */
#define CFG_BR2_PRELIM		0xf8001861	/* 64MB localbus SDRAM	*/
#define CFG_OR2_PRELIM		0xfc006901
#define CFG_LBC_LCRR		0x00030004	/* local bus freq	*/
#define CFG_LBC_LBCR		0x00000000
#define CFG_LBC_LSRT		0x20000000
#define CFG_LBC_MRTPR		0x20000000
#define CFG_LBC_LSDMR_1		0x2861b723
#define CFG_LBC_LSDMR_2		0x0861b723
#define CFG_LBC_LSDMR_3		0x0861b723
#define CFG_LBC_LSDMR_4		0x1861b723
#define CFG_LBC_LSDMR_5		0x4061b723

#define CONFIG_L1_INIT_RAM
#define CFG_INIT_RAM_LOCK	1
#define CFG_INIT_RAM_ADDR	0x60000000	/* Initial RAM address	*/
#define CFG_INIT_RAM_END	0x4000		/* End of used area in RAM */

#define CFG_GBL_DATA_SIZE	128		/* num bytes initial data */
#define CFG_GBL_DATA_OFFSET	(CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
#define CFG_INIT_SP_OFFSET	CFG_GBL_DATA_OFFSET

#define CFG_MONITOR_LEN		(256 * 1024)	/* Reserve 256 kB for Mon */
#define CFG_MALLOC_LEN		(512 * 1024)	/* Reserved for malloc */

/* Serial Port */
#define CONFIG_CONS_INDEX     2
#undef	CONFIG_SERIAL_SOFTWARE_FIFO
#define CFG_NS16550
#define CFG_NS16550_SERIAL
#define CFG_NS16550_REG_SIZE	1
#define CFG_NS16550_CLK		get_bus_freq(0)

#define CFG_BAUDRATE_TABLE  \
	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}

#define CFG_NS16550_COM1	(CFG_CCSRBAR+0x4500)
#define CFG_NS16550_COM2	(CFG_CCSRBAR+0x4600)

#define CONFIG_CMDLINE_EDITING	1	/* add command line history	*/
#define CFG_HUSH_PARSER		1	/* Use the HUSH parser		*/
#ifdef	CFG_HUSH_PARSER
#define CFG_PROMPT_HUSH_PS2 "> "
#endif

/* I2C */
#define CONFIG_FSL_I2C			/* Use FSL common I2C driver */
#define  CONFIG_HARD_I2C		/* I2C with hardware support*/
#undef	CONFIG_SOFT_I2C			/* I2C bit-banged */
#define CFG_I2C_SPEED		400000	/* I2C speed and slave address	*/
#define CFG_I2C_SLAVE		0x7F
#if 0
#define CFG_I2C_NOPROBES	{0x00}	/* Don't probe these addrs */
#else
/* I did the 'if 0' so we could keep the syntax above if ever needed. */
#undef CFG_I2C_NOPROBES
#endif
#define CFG_I2C_OFFSET		0x3000

/* I2C EEPROM.	AT24C32, we keep our environment in here.
*/
#define CFG_I2C_EEPROM_ADDR		0x51	/* 1010001x		*/
#define CFG_I2C_EEPROM_ADDR_LEN		2
#define CFG_EEPROM_PAGE_WRITE_BITS	5	/* =32 Bytes per write	*/
#define CFG_EEPROM_PAGE_WRITE_ENABLE
#define CFG_EEPROM_PAGE_WRITE_DELAY_MS	20

/*
 * Standard 8555 PCI mapping.
 * Addresses are mapped 1-1.
 */
#define CFG_PCI1_MEM_BASE	0x80000000
#define CFG_PCI1_MEM_PHYS	CFG_PCI1_MEM_BASE
#define CFG_PCI1_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI1_IO_BASE	0x00000000
#define CFG_PCI1_IO_PHYS	0xe2000000
#define CFG_PCI1_IO_SIZE	0x01000000	/* 16M */

#define CFG_PCI2_MEM_BASE	0xa0000000
#define CFG_PCI2_MEM_PHYS	CFG_PCI2_MEM_BASE
#define CFG_PCI2_MEM_SIZE	0x20000000	/* 512M */
#define CFG_PCI2_IO_BASE	0x00000000
#define CFG_PCI2_IO_PHYS	0xe3000000
#define CFG_PCI2_IO_SIZE	0x01000000	/* 16M */

#if defined(CONFIG_PCI) 		/* PCI Ethernet card */
#define CONFIG_MPC85XX_PCI2	1
#define CONFIG_NET_MULTI
#define CONFIG_PCI_PNP			/* do pci plug-and-play */

#define CONFIG_EEPRO100
#define CONFIG_TULIP

#if !defined(CONFIG_PCI_PNP)
  #define PCI_ENET0_IOADDR	0xe0000000
  #define PCI_ENET0_MEMADDR	0xe0000000
  #define PCI_IDSEL_NUMBER	0x0c	/* slot0->3(IDSEL)=12->15 */
#endif

#define CONFIG_PCI_SCAN_SHOW
#define CFG_PCI_SUBSYS_VENDORID 0x1057	/* Motorola */

#endif /* CONFIG_PCI */

#if defined(CONFIG_TSEC_ENET)

#ifndef CONFIG_NET_MULTI
#define CONFIG_NET_MULTI	1
#endif

#define CONFIG_MII		1	/* MII PHY management		*/

#define CONFIG_TSEC1	1
#define CONFIG_TSEC1_NAME	"TSEC0"
#define CONFIG_TSEC2	1
#define CONFIG_TSEC2_NAME	"TSEC1"

#define TSEC1_PHY_ADDR		2
#define TSEC2_PHY_ADDR		4
#define TSEC1_PHYIDX		0
#define TSEC2_PHYIDX		0
#define TSEC1_FLAGS		TSEC_GIGABIT
#define TSEC2_FLAGS		TSEC_GIGABIT
#define CONFIG_ETHPRIME		"TSEC0"

#elif defined(CONFIG_ETHER_ON_FCC)	/* CPM FCC Ethernet */

#define CONFIG_ETHER_ON_FCC2		/* define if ether on FCC   */
#undef	CONFIG_ETHER_NONE		/* define if ether on something else */
#define CONFIG_ETHER_INDEX	2	/* which channel for ether  */

#if (CONFIG_ETHER_INDEX == 2)
  /*
   * - Rx-CLK is CLK13
   * - Tx-CLK is CLK14
   * - Select bus for bd/buffers
   * - Full duplex
   */
  #define CFG_CMXFCR_MASK	(CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK)
  #define CFG_CMXFCR_VALUE	(CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14)
  #define CFG_CPMFCR_RAMTYPE	0
#if 0
  #define CFG_FCC_PSMR		(FCC_PSMR_FDE)
#else
  #define CFG_FCC_PSMR		0
#endif
  #define FETH2_RST		0x01
#elif (CONFIG_ETHER_INDEX == 3)
  /* need more definitions here for FE3 */
  #define FETH3_RST		0x80
#endif					/* CONFIG_ETHER_INDEX */

/* MDIO is done through the TSEC0 control.
*/
#define CONFIG_MII			/* MII PHY management */
#undef CONFIG_BITBANGMII		/* bit-bang MII PHY management	*/

#endif

/* Environment - default config is in flash, see below */
#if 0	/* in EEPROM */
# define CFG_ENV_IS_IN_EEPROM	1
# define CFG_ENV_OFFSET		0
# define CFG_ENV_SIZE		2048
#else	/* in flash */
# define CFG_ENV_IS_IN_FLASH	1
# ifdef CONFIG_STXSSA_4M
#  define CFG_ENV_SECT_SIZE	0x20000
# else	/* default configuration - 64 MiB flash */
#  define CFG_ENV_SECT_SIZE	0x40000
# endif
# define CFG_ENV_ADDR		(CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
# define CFG_ENV_SIZE		0x4000
# define CFG_ENV_ADDR_REDUND	(CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
# define CFG_ENV_SIZE_REDUND	(CFG_ENV_SIZE)
#endif

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#define CFG_LOADS_BAUD_CHANGE	1	/* allow baudrate change	*/

#define	CONFIG_TIMESTAMP		/* Print image info with ts	*/


/*
 * BOOTP options
 */
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_PING
#define CONFIG_CMD_I2C

#if defined(CONFIG_PCI)
    #define CONFIG_CMD_PCI
#endif

#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
    #define CONFIG_CMD_MII
#endif

#if defined(CFG_RAMBOOT)
    #undef CONFIG_CMD_ENV
    #undef CONFIG_CMD_LOADS
#else
    #define CONFIG_CMD_ELF
#endif


#undef CONFIG_WATCHDOG			/* watchdog disabled		*/

/*
 * Miscellaneous configurable options
 */
#define CFG_LONGHELP			/* undef to save memory		*/
#define CFG_PROMPT	"SSA=> "	/* Monitor Command Prompt	*/
#if defined(CONFIG_CMD_KGDB)
#define CFG_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define CFG_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
#define CFG_MAXARGS	16		/* max number of command args	*/
#define CFG_BARGSIZE	CFG_CBSIZE	/* Boot Argument Buffer Size	*/
#define CFG_LOAD_ADDR	0x1000000	/* default load address */
#define CFG_HZ		1000		/* decrementer freq: 1 ms ticks */

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define CFG_BOOTMAPSZ		(8 << 20) /* Initial Memory map for Linux */

/* Cache Configuration */
#define CFG_DCACHE_SIZE		32768
#define CFG_CACHELINE_SIZE	32
#if defined(CONFIG_CMD_KGDB)
#define CFG_CACHELINE_SHIFT	5	/* log base 2 of the above value */
#endif

/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH */
#define BOOTFLAG_WARM	0x02		/* Software reboot		*/

#if defined(CONFIG_CMD_KGDB)
#define CONFIG_KGDB_BAUDRATE	230400	/* speed to run kgdb serial port */
#define CONFIG_KGDB_SER_INDEX	2	/* which serial port to use */
#endif

/*Note: change below for your network setting!!! */
#if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC)
#define CONFIG_HAS_ETH0
#define CONFIG_ETHADDR	 00:e0:0c:07:9b:8a
#define CONFIG_HAS_ETH1
#define CONFIG_ETH1ADDR  00:e0:0c:07:9b:8b
#define CONFIG_HAS_ETH2
#define CONFIG_ETH2ADDR  00:e0:0c:07:9b:8c
#endif

/*
 * Environment in EEPROM is compatible with different flash sector sizes,
 * but only little space is available, so we use a very simple setup.
 * With environment in flash, we use a more powerful default configuration.
 */
#ifdef CFG_ENV_IS_IN_EEPROM		/* use restricted "standard" environment */

#define CONFIG_BAUDRATE		38400

#define CONFIG_BOOTDELAY	3	/* -1 disable autoboot */
#define CONFIG_BOOTCOMMAND	"bootm 0xffc00000 0xffd00000"
#define CONFIG_BOOTARGS		"root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
#define CONFIG_SERVERIP 	192.168.85.1
#define CONFIG_IPADDR		192.168.85.60
#define CONFIG_GATEWAYIP	192.168.85.1
#define CONFIG_NETMASK		255.255.255.0
#define CONFIG_HOSTNAME 	STX_SSA
#define CONFIG_ROOTPATH 	/gppproot
#define CONFIG_BOOTFILE 	uImage
#define CONFIG_LOADADDR		0x1000000

#else /* ENV IS IN FLASH		-- use a full-blown envionment */

#define CONFIG_BAUDRATE		115200

#define CONFIG_BOOTDELAY	5	/* -1 disable autoboot */

#define CONFIG_PREBOOT	"echo;"	\
	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	"echo"

#undef	CONFIG_BOOTARGS		/* the boot command will set bootargs	*/

#define	CONFIG_EXTRA_ENV_SETTINGS					\
	"hostname=gp3ssa\0"						\
	"bootfile=/tftpboot/gp3ssa/uImage\0"				\
	"loadaddr=400000\0"						\
	"netdev=eth0\0"							\
	"consdev=ttyS1\0"						\
	"nfsargs=setenv bootargs root=/dev/nfs rw "			\
		"nfsroot=$serverip:$rootpath\0"				\
	"ramargs=setenv bootargs root=/dev/ram rw\0"			\
	"addip=setenv bootargs $bootargs "				\
		"ip=$ipaddr:$serverip:$gatewayip:$netmask"		\
		":$hostname:$netdev:off panic=1\0"			\
	"addcons=setenv bootargs $bootargs "				\
		"console=$consdev,$baudrate\0"				\
	"flash_nfs=run nfsargs addip addcons;"				\
		"bootm $kernel_addr\0"					\
	"flash_self=run ramargs addip addcons;"				\
		"bootm $kernel_addr $ramdisk_addr\0"			\
	"net_nfs=tftp $loadaddr $bootfile;"				\
		"run nfsargs addip addcons;bootm\0"			\
	"rootpath=/opt/eldk/ppc_85xx\0"					\
	"kernel_addr=FC000000\0"					\
	"ramdisk_addr=FC200000\0"					\
	""
#define CONFIG_BOOTCOMMAND	"run flash_self"

#endif	/* CFG_ENV_IS_IN_EEPROM */

#endif	/* __CONFIG_H */
Commit	Line	Data
35171dc0 DM	1	/*
	2	* (C) Copyright 2005 Embedded Alley Solutions, Inc.
	3	* Dan Malek <dan@embeddedalley.com>
	4	* Copied from STx GP3.
	5	* Updates for Silicon Tx GP3 SSA board.
	6	*
	7	* (C) Copyright 2002,2003 Motorola,Inc.
	8	* Xianghua Xiao <X.Xiao@motorola.com>
	9	*
	10	* See file CREDITS for list of people who contributed to this
	11	* project.
	12	*
	13	* This program is free software; you can redistribute it and/or
	14	* modify it under the terms of the GNU General Public License as
	15	* published by the Free Software Foundation; either version 2 of
	16	* the License, or (at your option) any later version.
	17	*
	18	* This program is distributed in the hope that it will be useful,
	19	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	20	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	21	* GNU General Public License for more details.
	22	*
	23	* You should have received a copy of the GNU General Public License
	24	* along with this program; if not, write to the Free Software
	25	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	26	* MA 02111-1307 USA
	27	*/
	28
	29	/* mpc8560ads board configuration file */
	30	/* please refer to doc/README.mpc85xx for more info */
	31	/* make sure you change the MAC address and other network params first,
	32	* search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file
	33	*/
	34
	35	#ifndef __CONFIG_H
	36	#define __CONFIG_H
	37
	38	/* High Level Configuration Options */
	39	#define CONFIG_BOOKE 1 /* BOOKE */
	40	#define CONFIG_E500 1 /* BOOKE e500 family */
	41	#define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */
	42	#define CONFIG_CPM2 1 /* has CPM2 */
	43	#define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/
	44
f1152f8c WD	45	#define CONFIG_PCI /* PCI ethernet support */
	46	#define CONFIG_TSEC_ENET /* tsec ethernet support*/
	47	#undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */
35171dc0	48	#define CONFIG_ENV_OVERWRITE
f1152f8c WD	49	#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */
	50	#undef CONFIG_DDR_ECC /* only for ECC DDR module */
	51	#undef CONFIG_DDR_DLL /* possible DLL fix needed */
35171dc0 DM	52	#define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
	53
	54
	55	/* sysclk for MPC85xx
	56	*/
	57
f1152f8c	58	#define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */
35171dc0 DM	59
	60	/* Blinkin' LEDs for Robert :-)
	61	*/
	62	#define CONFIG_SHOW_ACTIVITY 1
	63
	64	/*
	65	* These can be toggled for performance analysis, otherwise use default.
	66	*/
f1152f8c WD	67	#define CONFIG_L2_CACHE /* toggle L2 cache */
	68	#define CONFIG_BTB /* toggle branch predition */
	69	#define CONFIG_ADDR_STREAMING /* toggle addr streaming */
35171dc0	70
f1152f8c	71	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
35171dc0	72
f1152f8c WD	73	#undef CFG_DRAM_TEST /* memory test, takes time */
	74	#define CFG_MEMTEST_START 0x00200000 /* memtest region */
	75	#define CFG_MEMTEST_END 0x00400000
35171dc0 DM	76
35171dc0 DM	77
f1152f8c	78	/* Localbus connector. There are many options that can be
35171dc0 DM	79	* connected here, including sdram or lots of flash.
	80	* This address, however, is used to configure a 256M local bus
	81	* window that includes the Config latch below.
	82	*/
f1152f8c	83	#define CFG_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */
35171dc0 DM	84	#define CFG_LBC_OPTION_SIZE 256 /* 256MB */
	85
	86	/* There are various flash options used, we configure for the largest,
	87	* which is 64Mbytes. The CFI works fine and will discover the proper
	88	* sizes.
	89	*/
ee152983	90	#ifdef CONFIG_STXSSA_4M
f1152f8c	91	#define CFG_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */
ee152983	92	#else
f1152f8c	93	#define CFG_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */
ee152983 WD	94	#endif
	95	#define CFG_BR0_PRELIM (CFG_FLASH_BASE \| 0x1801) /* port size 32bit */
	96	#define CFG_OR0_PRELIM (CFG_FLASH_BASE \| 0x0FF7)
35171dc0 DM	97
	98	#define CFG_FLASH_CFI 1
	99	#define CFG_FLASH_CFI_DRIVER 1
f1152f8c	100	#undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
35171dc0 DM	101	#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
	102	#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */
	103
	104	#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE }
	105
	106	#define CFG_FLASH_PROTECTION
	107
	108	/* The configuration latch is Chip Select 1.
	109	* It's an 8-bit latch in the lower 8 bits of the word.
	110	*/
ee152983 WD	111	#define CFG_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */
ee152983 WD	112	#define CFG_BR1_PRELIM 0xFB001801 /* 32-bit port */
f1152f8c	113	#define CFG_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */
35171dc0	114
f1152f8c	115	#define CFG_MONITOR_BASE TEXT_BASE /* start of monitor */
35171dc0 DM	116
	117	#if (CFG_MONITOR_BASE < CFG_FLASH_BASE)
	118	#define CFG_RAMBOOT
	119	#else
f1152f8c	120	#undef CFG_RAMBOOT
35171dc0 DM	121	#endif
	122
	123	#ifdef CFG_RAMBOOT
f1152f8c	124	#define CFG_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */
35171dc0	125	#else
f1152f8c	126	#define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */
35171dc0	127	#endif
f1152f8c	128	#define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */
35171dc0 DM	129	#define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */
	130
	131
	132	/*
	133	* DDR Setup
	134	*/
	135
	136	/*
	137	* Base addresses -- Note these are effective addresses where the
	138	* actual resources get mapped (not physical addresses)
	139	*/
	140	#define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */
	141	#define CFG_SDRAM_BASE CFG_DDR_SDRAM_BASE
	142
f1152f8c	143	#define SPD_EEPROM_ADDRESS 0x54 /* DDR DIMM */
35171dc0 DM	144
	145	#undef CONFIG_CLOCKS_IN_MHZ
	146
	147	/* local bus definitions */
f1152f8c	148	#define CFG_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */
35171dc0	149	#define CFG_OR2_PRELIM 0xfc006901
f1152f8c	150	#define CFG_LBC_LCRR 0x00030004 /* local bus freq */
35171dc0 DM	151	#define CFG_LBC_LBCR 0x00000000
	152	#define CFG_LBC_LSRT 0x20000000
	153	#define CFG_LBC_MRTPR 0x20000000
	154	#define CFG_LBC_LSDMR_1 0x2861b723
	155	#define CFG_LBC_LSDMR_2 0x0861b723
	156	#define CFG_LBC_LSDMR_3 0x0861b723
	157	#define CFG_LBC_LSDMR_4 0x1861b723
	158	#define CFG_LBC_LSDMR_5 0x4061b723
	159
	160	#define CONFIG_L1_INIT_RAM
f1152f8c WD	161	#define CFG_INIT_RAM_LOCK 1
	162	#define CFG_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */
	163	#define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */
35171dc0	164
f1152f8c	165	#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */
35171dc0 DM	166	#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE)
	167	#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET
	168
f1152f8c WD	169	#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */
f1152f8c WD	170	#define CFG_MALLOC_LEN (512 * 1024) /* Reserved for malloc */
35171dc0 DM	171
	172	/* Serial Port */
	173	#define CONFIG_CONS_INDEX 2
	174	#undef CONFIG_SERIAL_SOFTWARE_FIFO
	175	#define CFG_NS16550
	176	#define CFG_NS16550_SERIAL
f1152f8c	177	#define CFG_NS16550_REG_SIZE 1
35171dc0 DM	178	#define CFG_NS16550_CLK get_bus_freq(0)
35171dc0 DM	179
35171dc0 DM	180	#define CFG_BAUDRATE_TABLE \
	181	{300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200}
	182
f1152f8c WD	183	#define CFG_NS16550_COM1 (CFG_CCSRBAR+0x4500)
f1152f8c WD	184	#define CFG_NS16550_COM2 (CFG_CCSRBAR+0x4600)
35171dc0	185
c64a89d6 WD	186	#define CONFIG_CMDLINE_EDITING 1 /* add command line history */
c64a89d6 WD	187	#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */
f1152f8c	188	#ifdef CFG_HUSH_PARSER
35171dc0 DM	189	#define CFG_PROMPT_HUSH_PS2 "> "
	190	#endif
	191
	192	/* I2C */
	193	#define CONFIG_FSL_I2C /* Use FSL common I2C driver */
f1152f8c	194	#define CONFIG_HARD_I2C /* I2C with hardware support*/
35171dc0 DM	195	#undef CONFIG_SOFT_I2C /* I2C bit-banged */
	196	#define CFG_I2C_SPEED 400000 /* I2C speed and slave address */
	197	#define CFG_I2C_SLAVE 0x7F
	198	#if 0
f1152f8c	199	#define CFG_I2C_NOPROBES {0x00} /* Don't probe these addrs */
35171dc0 DM	200	#else
	201	/* I did the 'if 0' so we could keep the syntax above if ever needed. */
	202	#undef CFG_I2C_NOPROBES
	203	#endif
	204	#define CFG_I2C_OFFSET 0x3000
	205
f1152f8c	206	/* I2C EEPROM. AT24C32, we keep our environment in here.
35171dc0 DM	207	*/
	208	#define CFG_I2C_EEPROM_ADDR 0x51 /* 1010001x */
	209	#define CFG_I2C_EEPROM_ADDR_LEN 2
	210	#define CFG_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */
	211	#define CFG_EEPROM_PAGE_WRITE_ENABLE
	212	#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20
	213
	214	/*
	215	* Standard 8555 PCI mapping.
	216	* Addresses are mapped 1-1.
	217	*/
	218	#define CFG_PCI1_MEM_BASE 0x80000000
	219	#define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE
	220	#define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */
	221	#define CFG_PCI1_IO_BASE 0x00000000
	222	#define CFG_PCI1_IO_PHYS 0xe2000000
	223	#define CFG_PCI1_IO_SIZE 0x01000000 /* 16M */
	224
	225	#define CFG_PCI2_MEM_BASE 0xa0000000
	226	#define CFG_PCI2_MEM_PHYS CFG_PCI2_MEM_BASE
	227	#define CFG_PCI2_MEM_SIZE 0x20000000 /* 512M */
	228	#define CFG_PCI2_IO_BASE 0x00000000
	229	#define CFG_PCI2_IO_PHYS 0xe3000000
	230	#define CFG_PCI2_IO_SIZE 0x01000000 /* 16M */
	231
	232	#if defined(CONFIG_PCI) /* PCI Ethernet card */
38ad82da	233	#define CONFIG_MPC85XX_PCI2 1
35171dc0	234	#define CONFIG_NET_MULTI
f1152f8c	235	#define CONFIG_PCI_PNP /* do pci plug-and-play */
35171dc0	236
f1152f8c WD	237	#define CONFIG_EEPRO100
f1152f8c WD	238	#define CONFIG_TULIP
35171dc0 DM	239
35171dc0 DM	240	#if !defined(CONFIG_PCI_PNP)
f1152f8c WD	241	#define PCI_ENET0_IOADDR 0xe0000000
	242	#define PCI_ENET0_MEMADDR 0xe0000000
	243	#define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */
35171dc0 DM	244	#endif
35171dc0 DM	245
f1152f8c WD	246	#define CONFIG_PCI_SCAN_SHOW
f1152f8c WD	247	#define CFG_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */
35171dc0 DM	248
	249	#endif /* CONFIG_PCI */
	250
	251	#if defined(CONFIG_TSEC_ENET)
	252
	253	#ifndef CONFIG_NET_MULTI
f1152f8c	254	#define CONFIG_NET_MULTI 1
35171dc0 DM	255	#endif
	256
	257	#define CONFIG_MII 1 /* MII PHY management */
	258
255a3577 KP	259	#define CONFIG_TSEC1 1
	260	#define CONFIG_TSEC1_NAME "TSEC0"
	261	#define CONFIG_TSEC2 1
	262	#define CONFIG_TSEC2_NAME "TSEC1"
35171dc0 DM	263
	264	#define TSEC1_PHY_ADDR 2
	265	#define TSEC2_PHY_ADDR 4
	266	#define TSEC1_PHYIDX 0
	267	#define TSEC2_PHYIDX 0
3a79013e AF	268	#define TSEC1_FLAGS TSEC_GIGABIT
3a79013e AF	269	#define TSEC2_FLAGS TSEC_GIGABIT
35171dc0 DM	270	#define CONFIG_ETHPRIME "TSEC0"
	271
	272	#elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */
	273
f1152f8c WD	274	#define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */
	275	#undef CONFIG_ETHER_NONE /* define if ether on something else */
	276	#define CONFIG_ETHER_INDEX 2 /* which channel for ether */
35171dc0 DM	277
	278	#if (CONFIG_ETHER_INDEX == 2)
	279	/*
	280	* - Rx-CLK is CLK13
	281	* - Tx-CLK is CLK14
	282	* - Select bus for bd/buffers
	283	* - Full duplex
	284	*/
f1152f8c WD	285	#define CFG_CMXFCR_MASK (CMXFCR_FC2 \| CMXFCR_RF2CS_MSK \| CMXFCR_TF2CS_MSK)
	286	#define CFG_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 \| CMXFCR_TF2CS_CLK14)
	287	#define CFG_CPMFCR_RAMTYPE 0
35171dc0	288	#if 0
f1152f8c	289	#define CFG_FCC_PSMR (FCC_PSMR_FDE)
35171dc0	290	#else
f1152f8c	291	#define CFG_FCC_PSMR 0
35171dc0 DM	292	#endif
	293	#define FETH2_RST 0x01
	294	#elif (CONFIG_ETHER_INDEX == 3)
	295	/* need more definitions here for FE3 */
	296	#define FETH3_RST 0x80
f1152f8c	297	#endif /* CONFIG_ETHER_INDEX */
35171dc0 DM	298
	299	/* MDIO is done through the TSEC0 control.
	300	*/
	301	#define CONFIG_MII /* MII PHY management */
	302	#undef CONFIG_BITBANGMII /* bit-bang MII PHY management */
	303
	304	#endif
	305
c64a89d6 WD	306	/* Environment - default config is in flash, see below */
c64a89d6 WD	307	#if 0 /* in EEPROM */
ee152983 WD	308	# define CFG_ENV_IS_IN_EEPROM 1
	309	# define CFG_ENV_OFFSET 0
	310	# define CFG_ENV_SIZE 2048
c64a89d6	311	#else /* in flash */
ee152983 WD	312	# define CFG_ENV_IS_IN_FLASH 1
	313	# ifdef CONFIG_STXSSA_4M
	314	# define CFG_ENV_SECT_SIZE 0x20000
	315	# else /* default configuration - 64 MiB flash */
	316	# define CFG_ENV_SECT_SIZE 0x40000
	317	# endif
	318	# define CFG_ENV_ADDR (CFG_MONITOR_BASE - CFG_ENV_SECT_SIZE)
	319	# define CFG_ENV_SIZE 0x4000
	320	# define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR - CFG_ENV_SECT_SIZE)
	321	# define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE)
35171dc0 DM	322	#endif
35171dc0 DM	323
35171dc0 DM	324	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
	325	#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */
	326
c64a89d6 WD	327	#define CONFIG_TIMESTAMP /* Print image info with ts */
c64a89d6 WD	328
2835e518	329
079a136c JL	330	/*
	331	* BOOTP options
	332	*/
	333	#define CONFIG_BOOTP_BOOTFILESIZE
	334	#define CONFIG_BOOTP_BOOTPATH
	335	#define CONFIG_BOOTP_GATEWAY
	336	#define CONFIG_BOOTP_HOSTNAME
	337
	338
2835e518 JL	339	/*
	340	* Command line configuration.
	341	*/
	342	#include <config_cmd_default.h>
	343
	344	#define CONFIG_CMD_PING
	345	#define CONFIG_CMD_I2C
	346
	347	#if defined(CONFIG_PCI)
	348	#define CONFIG_CMD_PCI
	349	#endif
	350
	351	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
	352	#define CONFIG_CMD_MII
	353	#endif
	354
35171dc0	355	#if defined(CFG_RAMBOOT)
2835e518 JL	356	#undef CONFIG_CMD_ENV
2835e518 JL	357	#undef CONFIG_CMD_LOADS
35171dc0	358	#else
2835e518	359	#define CONFIG_CMD_ELF
35171dc0	360	#endif
2835e518	361
35171dc0 DM	362
	363	#undef CONFIG_WATCHDOG /* watchdog disabled */
	364
	365	/*
	366	* Miscellaneous configurable options
	367	*/
	368	#define CFG_LONGHELP /* undef to save memory */
	369	#define CFG_PROMPT "SSA=> " /* Monitor Command Prompt */
ef0df52a	370	#if defined(CONFIG_CMD_KGDB)
35171dc0 DM	371	#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */
	372	#else
	373	#define CFG_CBSIZE 256 /* Console I/O Buffer Size */
	374	#endif
	375	#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */
	376	#define CFG_MAXARGS 16 /* max number of command args */
	377	#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */
	378	#define CFG_LOAD_ADDR 0x1000000 /* default load address */
	379	#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */
	380
	381	/*
	382	* For booting Linux, the board info and command line data
	383	* have to be in the first 8 MB of memory, since this is
	384	* the maximum mapped by the Linux kernel during initialization.
	385	*/
	386	#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
	387
	388	/* Cache Configuration */
	389	#define CFG_DCACHE_SIZE 32768
	390	#define CFG_CACHELINE_SIZE 32
ef0df52a	391	#if defined(CONFIG_CMD_KGDB)
35171dc0 DM	392	#define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */
	393	#endif
	394
	395	/*
	396	* Internal Definitions
	397	*
	398	* Boot Flags
	399	*/
	400	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	401	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	402
ef0df52a	403	#if defined(CONFIG_CMD_KGDB)
35171dc0 DM	404	#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */
	405	#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */
	406	#endif
	407
	408	/Note: change below for your network setting!!! /
	409	#if defined(CONFIG_TSEC_ENET) \|\| defined(CONFIG_ETHER_ON_FCC)
10327dc5	410	#define CONFIG_HAS_ETH0
35171dc0 DM	411	#define CONFIG_ETHADDR 00:e0:0c:07:9b:8a
	412	#define CONFIG_HAS_ETH1
	413	#define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b
	414	#define CONFIG_HAS_ETH2
	415	#define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c
	416	#endif
	417
c64a89d6 WD	418	/*
	419	* Environment in EEPROM is compatible with different flash sector sizes,
	420	* but only little space is available, so we use a very simple setup.
	421	* With environment in flash, we use a more powerful default configuration.
	422	*/
	423	#ifdef CFG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */
	424
f1152f8c	425	#define CONFIG_BAUDRATE 38400
c64a89d6 WD	426
	427	#define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */
	428	#define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000"
	429	#define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate"
35171dc0	430	#define CONFIG_SERVERIP 192.168.85.1
f1152f8c	431	#define CONFIG_IPADDR 192.168.85.60
35171dc0 DM	432	#define CONFIG_GATEWAYIP 192.168.85.1
	433	#define CONFIG_NETMASK 255.255.255.0
	434	#define CONFIG_HOSTNAME STX_SSA
	435	#define CONFIG_ROOTPATH /gppproot
	436	#define CONFIG_BOOTFILE uImage
	437	#define CONFIG_LOADADDR 0x1000000
	438
c64a89d6 WD	439	#else /* ENV IS IN FLASH -- use a full-blown envionment */
c64a89d6 WD	440
f1152f8c	441	#define CONFIG_BAUDRATE 115200
c64a89d6 WD	442
	443	#define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */
	444
	445	#define CONFIG_PREBOOT "echo;" \
	446	"echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \
	447	"echo"
	448
	449	#undef CONFIG_BOOTARGS /* the boot command will set bootargs */
	450
	451	#define CONFIG_EXTRA_ENV_SETTINGS \
	452	"hostname=gp3ssa\0" \
	453	"bootfile=/tftpboot/gp3ssa/uImage\0" \
	454	"loadaddr=400000\0" \
	455	"netdev=eth0\0" \
	456	"consdev=ttyS1\0" \
	457	"nfsargs=setenv bootargs root=/dev/nfs rw " \
	458	"nfsroot=$serverip:$rootpath\0" \
	459	"ramargs=setenv bootargs root=/dev/ram rw\0" \
	460	"addip=setenv bootargs $bootargs " \
	461	"ip=$ipaddr:$serverip:$gatewayip:$netmask" \
	462	":$hostname:$netdev:off panic=1\0" \
	463	"addcons=setenv bootargs $bootargs " \
	464	"console=$consdev,$baudrate\0" \
	465	"flash_nfs=run nfsargs addip addcons;" \
	466	"bootm $kernel_addr\0" \
	467	"flash_self=run ramargs addip addcons;" \
	468	"bootm $kernel_addr $ramdisk_addr\0" \
	469	"net_nfs=tftp $loadaddr $bootfile;" \
	470	"run nfsargs addip addcons;bootm\0" \
	471	"rootpath=/opt/eldk/ppc_85xx\0" \
	472	"kernel_addr=FC000000\0" \
	473	"ramdisk_addr=FC200000\0" \
	474	""
	475	#define CONFIG_BOOTCOMMAND "run flash_self"
	476
	477	#endif /* CFG_ENV_IS_IN_EEPROM */
	478
35171dc0	479	#endif /* __CONFIG_H */