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35171dc0 DM |
1 | /* |
2 | * (C) Copyright 2005 Embedded Alley Solutions, Inc. | |
3 | * Dan Malek <dan@embeddedalley.com> | |
4 | * Copied from STx GP3. | |
5 | * Updates for Silicon Tx GP3 SSA board. | |
6 | * | |
7 | * (C) Copyright 2002,2003 Motorola,Inc. | |
8 | * Xianghua Xiao <X.Xiao@motorola.com> | |
9 | * | |
10 | * See file CREDITS for list of people who contributed to this | |
11 | * project. | |
12 | * | |
13 | * This program is free software; you can redistribute it and/or | |
14 | * modify it under the terms of the GNU General Public License as | |
15 | * published by the Free Software Foundation; either version 2 of | |
16 | * the License, or (at your option) any later version. | |
17 | * | |
18 | * This program is distributed in the hope that it will be useful, | |
19 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
20 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
21 | * GNU General Public License for more details. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License | |
24 | * along with this program; if not, write to the Free Software | |
25 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
26 | * MA 02111-1307 USA | |
27 | */ | |
28 | ||
29 | /* mpc8560ads board configuration file */ | |
30 | /* please refer to doc/README.mpc85xx for more info */ | |
31 | /* make sure you change the MAC address and other network params first, | |
32 | * search for CONFIG_ETHADDR,CONFIG_SERVERIP,etc in this file | |
33 | */ | |
34 | ||
35 | #ifndef __CONFIG_H | |
36 | #define __CONFIG_H | |
37 | ||
38 | /* High Level Configuration Options */ | |
39 | #define CONFIG_BOOKE 1 /* BOOKE */ | |
40 | #define CONFIG_E500 1 /* BOOKE e500 family */ | |
41 | #define CONFIG_MPC85xx 1 /* MPC8540/MPC8560 */ | |
42 | #define CONFIG_CPM2 1 /* has CPM2 */ | |
43 | #define CONFIG_STXSSA 1 /* Silicon Tx GPPP SSA board specific*/ | |
f060054d | 44 | #define CONFIG_MPC8560 1 |
35171dc0 | 45 | |
28415b62 | 46 | #define CONFIG_SYS_TEXT_BASE 0xFFF80000 |
2ae18241 | 47 | |
f1152f8c WD |
48 | #define CONFIG_PCI /* PCI ethernet support */ |
49 | #define CONFIG_TSEC_ENET /* tsec ethernet support*/ | |
50 | #undef CONFIG_ETHER_ON_FCC /* cpm FCC ethernet support */ | |
35171dc0 | 51 | #define CONFIG_ENV_OVERWRITE |
35171dc0 | 52 | |
572b13af | 53 | #define CONFIG_FSL_LAW 1 /* Use common FSL init code */ |
35171dc0 DM |
54 | |
55 | /* sysclk for MPC85xx | |
56 | */ | |
57 | ||
f1152f8c | 58 | #define CONFIG_SYS_CLK_FREQ 33000000 /* most pci cards are 33Mhz */ |
35171dc0 DM |
59 | |
60 | /* Blinkin' LEDs for Robert :-) | |
61 | */ | |
62 | #define CONFIG_SHOW_ACTIVITY 1 | |
63 | ||
64 | /* | |
65 | * These can be toggled for performance analysis, otherwise use default. | |
66 | */ | |
f1152f8c WD |
67 | #define CONFIG_L2_CACHE /* toggle L2 cache */ |
68 | #define CONFIG_BTB /* toggle branch predition */ | |
35171dc0 | 69 | |
53677ef1 | 70 | #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ |
35171dc0 | 71 | |
6d0f6bcf JCPV |
72 | #undef CONFIG_SYS_DRAM_TEST /* memory test, takes time */ |
73 | #define CONFIG_SYS_MEMTEST_START 0x00200000 /* memtest region */ | |
74 | #define CONFIG_SYS_MEMTEST_END 0x00400000 | |
35171dc0 DM |
75 | |
76 | ||
f1152f8c | 77 | /* Localbus connector. There are many options that can be |
35171dc0 DM |
78 | * connected here, including sdram or lots of flash. |
79 | * This address, however, is used to configure a 256M local bus | |
80 | * window that includes the Config latch below. | |
81 | */ | |
6d0f6bcf JCPV |
82 | #define CONFIG_SYS_LBC_OPTION_BASE 0xF0000000 /* Localbus Extension */ |
83 | #define CONFIG_SYS_LBC_OPTION_SIZE 256 /* 256MB */ | |
35171dc0 DM |
84 | |
85 | /* There are various flash options used, we configure for the largest, | |
86 | * which is 64Mbytes. The CFI works fine and will discover the proper | |
87 | * sizes. | |
88 | */ | |
ee152983 | 89 | #ifdef CONFIG_STXSSA_4M |
6d0f6bcf | 90 | #define CONFIG_SYS_FLASH_BASE 0xFFC00000 /* start of 4 MiB flash */ |
ee152983 | 91 | #else |
6d0f6bcf | 92 | #define CONFIG_SYS_FLASH_BASE 0xFC000000 /* start of 64 MiB flash */ |
ee152983 | 93 | #endif |
6d0f6bcf JCPV |
94 | #define CONFIG_SYS_BR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x1801) /* port size 32bit */ |
95 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_FLASH_BASE | 0x0FF7) | |
35171dc0 | 96 | |
6d0f6bcf | 97 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 98 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
99 | #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ |
100 | #define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ | |
101 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ | |
35171dc0 | 102 | |
6d0f6bcf | 103 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } |
35171dc0 | 104 | |
6d0f6bcf | 105 | #define CONFIG_SYS_FLASH_PROTECTION |
35171dc0 DM |
106 | |
107 | /* The configuration latch is Chip Select 1. | |
108 | * It's an 8-bit latch in the lower 8 bits of the word. | |
109 | */ | |
6d0f6bcf JCPV |
110 | #define CONFIG_SYS_LBC_CFGLATCH_BASE 0xFB000000 /* Base of config latch */ |
111 | #define CONFIG_SYS_BR1_PRELIM 0xFB001801 /* 32-bit port */ | |
112 | #define CONFIG_SYS_OR1_PRELIM 0xFFFF0FF7 /* 64K is enough */ | |
35171dc0 | 113 | |
14d0a02a | 114 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE /* start of monitor */ |
35171dc0 | 115 | |
6d0f6bcf JCPV |
116 | #if (CONFIG_SYS_MONITOR_BASE < CONFIG_SYS_FLASH_BASE) |
117 | #define CONFIG_SYS_RAMBOOT | |
35171dc0 | 118 | #else |
6d0f6bcf | 119 | #undef CONFIG_SYS_RAMBOOT |
35171dc0 DM |
120 | #endif |
121 | ||
6d0f6bcf JCPV |
122 | #ifdef CONFIG_SYS_RAMBOOT |
123 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0x40000000 /* CCSRBAR by BDI cfg */ | |
35171dc0 | 124 | #else |
6d0f6bcf | 125 | #define CONFIG_SYS_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ |
35171dc0 | 126 | #endif |
6d0f6bcf JCPV |
127 | #define CONFIG_SYS_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ |
128 | #define CONFIG_SYS_CCSRBAR_PHYS CONFIG_SYS_CCSRBAR /* physical addr of CCSRBAR */ | |
129 | #define CONFIG_SYS_IMMR CONFIG_SYS_CCSRBAR /* PQII uses CONFIG_SYS_IMMR */ | |
35171dc0 | 130 | |
0e7927db KG |
131 | /* DDR Setup */ |
132 | #define CONFIG_FSL_DDR1 | |
133 | #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ | |
134 | #define CONFIG_DDR_SPD | |
135 | #undef CONFIG_FSL_DDR_INTERACTIVE | |
35171dc0 | 136 | |
0e7927db | 137 | #undef CONFIG_DDR_ECC /* only for ECC DDR module */ |
0e7927db | 138 | #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */ |
35171dc0 | 139 | |
0e7927db KG |
140 | #define CONFIG_MEM_INIT_VALUE 0xDeadBeef |
141 | ||
6d0f6bcf JCPV |
142 | #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ |
143 | #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE | |
35171dc0 | 144 | |
0e7927db KG |
145 | #define CONFIG_NUM_DDR_CONTROLLERS 1 |
146 | #define CONFIG_DIMM_SLOTS_PER_CTLR 1 | |
147 | #define CONFIG_CHIP_SELECTS_PER_CTRL (2 * CONFIG_DIMM_SLOTS_PER_CTLR) | |
148 | ||
149 | /* I2C addresses of SPD EEPROMs */ | |
150 | #define SPD_EEPROM_ADDRESS 0x54 /* CTLR 0 DIMM 0 */ | |
35171dc0 DM |
151 | |
152 | #undef CONFIG_CLOCKS_IN_MHZ | |
153 | ||
154 | /* local bus definitions */ | |
6d0f6bcf JCPV |
155 | #define CONFIG_SYS_BR2_PRELIM 0xf8001861 /* 64MB localbus SDRAM */ |
156 | #define CONFIG_SYS_OR2_PRELIM 0xfc006901 | |
157 | #define CONFIG_SYS_LBC_LCRR 0x00030004 /* local bus freq */ | |
158 | #define CONFIG_SYS_LBC_LBCR 0x00000000 | |
159 | #define CONFIG_SYS_LBC_LSRT 0x20000000 | |
160 | #define CONFIG_SYS_LBC_MRTPR 0x20000000 | |
161 | #define CONFIG_SYS_LBC_LSDMR_1 0x2861b723 | |
162 | #define CONFIG_SYS_LBC_LSDMR_2 0x0861b723 | |
163 | #define CONFIG_SYS_LBC_LSDMR_3 0x0861b723 | |
164 | #define CONFIG_SYS_LBC_LSDMR_4 0x1861b723 | |
165 | #define CONFIG_SYS_LBC_LSDMR_5 0x4061b723 | |
35171dc0 | 166 | |
6d0f6bcf JCPV |
167 | #define CONFIG_SYS_INIT_RAM_LOCK 1 |
168 | #define CONFIG_SYS_INIT_RAM_ADDR 0x60000000 /* Initial RAM address */ | |
553f0982 | 169 | #define CONFIG_SYS_INIT_RAM_SIZE 0x4000 /* Size of used area in RAM */ |
35171dc0 | 170 | |
25ddd1fb | 171 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 172 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
35171dc0 | 173 | |
6d0f6bcf JCPV |
174 | #define CONFIG_SYS_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ |
175 | #define CONFIG_SYS_MALLOC_LEN (512 * 1024) /* Reserved for malloc */ | |
35171dc0 DM |
176 | |
177 | /* Serial Port */ | |
178 | #define CONFIG_CONS_INDEX 2 | |
6d0f6bcf JCPV |
179 | #define CONFIG_SYS_NS16550 |
180 | #define CONFIG_SYS_NS16550_SERIAL | |
181 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
182 | #define CONFIG_SYS_NS16550_CLK get_bus_freq(0) | |
35171dc0 | 183 | |
6d0f6bcf | 184 | #define CONFIG_SYS_BAUDRATE_TABLE \ |
35171dc0 DM |
185 | {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 115200} |
186 | ||
6d0f6bcf JCPV |
187 | #define CONFIG_SYS_NS16550_COM1 (CONFIG_SYS_CCSRBAR+0x4500) |
188 | #define CONFIG_SYS_NS16550_COM2 (CONFIG_SYS_CCSRBAR+0x4600) | |
35171dc0 | 189 | |
c64a89d6 | 190 | #define CONFIG_CMDLINE_EDITING 1 /* add command line history */ |
5be58f5f | 191 | #define CONFIG_AUTO_COMPLETE 1 /* add autocompletion support */ |
6d0f6bcf JCPV |
192 | #define CONFIG_SYS_HUSH_PARSER 1 /* Use the HUSH parser */ |
193 | #ifdef CONFIG_SYS_HUSH_PARSER | |
194 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
35171dc0 DM |
195 | #endif |
196 | ||
28415b62 WD |
197 | /* pass open firmware flat tree */ |
198 | #define CONFIG_OF_LIBFDT 1 | |
199 | #define CONFIG_OF_BOARD_SETUP 1 | |
200 | #define CONFIG_OF_STDOUT_VIA_ALIAS 1 | |
201 | ||
e1893815 WD |
202 | /* |
203 | * I2C | |
204 | */ | |
35171dc0 | 205 | #define CONFIG_FSL_I2C /* Use FSL common I2C driver */ |
f1152f8c | 206 | #define CONFIG_HARD_I2C /* I2C with hardware support*/ |
35171dc0 | 207 | #undef CONFIG_SOFT_I2C /* I2C bit-banged */ |
6d0f6bcf JCPV |
208 | #define CONFIG_SYS_I2C_SPEED 400000 /* I2C speed and slave address */ |
209 | #define CONFIG_SYS_I2C_SLAVE 0x7F | |
210 | #undef CONFIG_SYS_I2C_NOPROBES | |
211 | #define CONFIG_SYS_I2C_OFFSET 0x3000 | |
35171dc0 | 212 | |
e1893815 WD |
213 | /* I2C RTC */ |
214 | #define CONFIG_RTC_DS1337 /* This is really a DS1339 RTC */ | |
6d0f6bcf | 215 | #define CONFIG_SYS_I2C_RTC_ADDR 0x68 /* at address 0x68 */ |
e1893815 | 216 | |
f1152f8c | 217 | /* I2C EEPROM. AT24C32, we keep our environment in here. |
35171dc0 | 218 | */ |
6d0f6bcf JCPV |
219 | #define CONFIG_SYS_I2C_EEPROM_ADDR 0x51 /* 1010001x */ |
220 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 | |
221 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 5 /* =32 Bytes per write */ | |
222 | #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 20 | |
35171dc0 DM |
223 | |
224 | /* | |
225 | * Standard 8555 PCI mapping. | |
226 | * Addresses are mapped 1-1. | |
227 | */ | |
6d0f6bcf JCPV |
228 | #define CONFIG_SYS_PCI1_MEM_BASE 0x80000000 |
229 | #define CONFIG_SYS_PCI1_MEM_PHYS CONFIG_SYS_PCI1_MEM_BASE | |
230 | #define CONFIG_SYS_PCI1_MEM_SIZE 0x20000000 /* 512M */ | |
231 | #define CONFIG_SYS_PCI1_IO_BASE 0x00000000 | |
232 | #define CONFIG_SYS_PCI1_IO_PHYS 0xe2000000 | |
233 | #define CONFIG_SYS_PCI1_IO_SIZE 0x01000000 /* 16M */ | |
234 | ||
235 | #define CONFIG_SYS_PCI2_MEM_BASE 0xa0000000 | |
236 | #define CONFIG_SYS_PCI2_MEM_PHYS CONFIG_SYS_PCI2_MEM_BASE | |
237 | #define CONFIG_SYS_PCI2_MEM_SIZE 0x20000000 /* 512M */ | |
238 | #define CONFIG_SYS_PCI2_IO_BASE 0x00000000 | |
239 | #define CONFIG_SYS_PCI2_IO_PHYS 0xe3000000 | |
240 | #define CONFIG_SYS_PCI2_IO_SIZE 0x01000000 /* 16M */ | |
35171dc0 | 241 | |
53677ef1 | 242 | #if defined(CONFIG_PCI) /* PCI Ethernet card */ |
38ad82da | 243 | #define CONFIG_MPC85XX_PCI2 1 |
35171dc0 | 244 | #define CONFIG_NET_MULTI |
f1152f8c | 245 | #define CONFIG_PCI_PNP /* do pci plug-and-play */ |
35171dc0 | 246 | |
f1152f8c WD |
247 | #define CONFIG_EEPRO100 |
248 | #define CONFIG_TULIP | |
35171dc0 DM |
249 | |
250 | #if !defined(CONFIG_PCI_PNP) | |
f1152f8c WD |
251 | #define PCI_ENET0_IOADDR 0xe0000000 |
252 | #define PCI_ENET0_MEMADDR 0xe0000000 | |
253 | #define PCI_IDSEL_NUMBER 0x0c /* slot0->3(IDSEL)=12->15 */ | |
35171dc0 DM |
254 | #endif |
255 | ||
f1152f8c | 256 | #define CONFIG_PCI_SCAN_SHOW |
6d0f6bcf | 257 | #define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x1057 /* Motorola */ |
35171dc0 DM |
258 | |
259 | #endif /* CONFIG_PCI */ | |
260 | ||
261 | #if defined(CONFIG_TSEC_ENET) | |
262 | ||
263 | #ifndef CONFIG_NET_MULTI | |
f1152f8c | 264 | #define CONFIG_NET_MULTI 1 |
35171dc0 DM |
265 | #endif |
266 | ||
267 | #define CONFIG_MII 1 /* MII PHY management */ | |
268 | ||
255a3577 KP |
269 | #define CONFIG_TSEC1 1 |
270 | #define CONFIG_TSEC1_NAME "TSEC0" | |
271 | #define CONFIG_TSEC2 1 | |
272 | #define CONFIG_TSEC2_NAME "TSEC1" | |
35171dc0 DM |
273 | |
274 | #define TSEC1_PHY_ADDR 2 | |
275 | #define TSEC2_PHY_ADDR 4 | |
276 | #define TSEC1_PHYIDX 0 | |
277 | #define TSEC2_PHYIDX 0 | |
3a79013e AF |
278 | #define TSEC1_FLAGS TSEC_GIGABIT |
279 | #define TSEC2_FLAGS TSEC_GIGABIT | |
35171dc0 DM |
280 | #define CONFIG_ETHPRIME "TSEC0" |
281 | ||
282 | #elif defined(CONFIG_ETHER_ON_FCC) /* CPM FCC Ethernet */ | |
283 | ||
f1152f8c WD |
284 | #define CONFIG_ETHER_ON_FCC2 /* define if ether on FCC */ |
285 | #undef CONFIG_ETHER_NONE /* define if ether on something else */ | |
286 | #define CONFIG_ETHER_INDEX 2 /* which channel for ether */ | |
35171dc0 DM |
287 | |
288 | #if (CONFIG_ETHER_INDEX == 2) | |
289 | /* | |
290 | * - Rx-CLK is CLK13 | |
291 | * - Tx-CLK is CLK14 | |
292 | * - Select bus for bd/buffers | |
293 | * - Full duplex | |
294 | */ | |
6d0f6bcf JCPV |
295 | #define CONFIG_SYS_CMXFCR_MASK (CMXFCR_FC2 | CMXFCR_RF2CS_MSK | CMXFCR_TF2CS_MSK) |
296 | #define CONFIG_SYS_CMXFCR_VALUE (CMXFCR_RF2CS_CLK13 | CMXFCR_TF2CS_CLK14) | |
297 | #define CONFIG_SYS_CPMFCR_RAMTYPE 0 | |
35171dc0 | 298 | #if 0 |
6d0f6bcf | 299 | #define CONFIG_SYS_FCC_PSMR (FCC_PSMR_FDE) |
35171dc0 | 300 | #else |
6d0f6bcf | 301 | #define CONFIG_SYS_FCC_PSMR 0 |
35171dc0 DM |
302 | #endif |
303 | #define FETH2_RST 0x01 | |
304 | #elif (CONFIG_ETHER_INDEX == 3) | |
305 | /* need more definitions here for FE3 */ | |
306 | #define FETH3_RST 0x80 | |
f1152f8c | 307 | #endif /* CONFIG_ETHER_INDEX */ |
35171dc0 DM |
308 | |
309 | /* MDIO is done through the TSEC0 control. | |
310 | */ | |
311 | #define CONFIG_MII /* MII PHY management */ | |
312 | #undef CONFIG_BITBANGMII /* bit-bang MII PHY management */ | |
313 | ||
314 | #endif | |
315 | ||
c64a89d6 WD |
316 | /* Environment - default config is in flash, see below */ |
317 | #if 0 /* in EEPROM */ | |
bb1f8b4f | 318 | # define CONFIG_ENV_IS_IN_EEPROM 1 |
0e8d1586 JCPV |
319 | # define CONFIG_ENV_OFFSET 0 |
320 | # define CONFIG_ENV_SIZE 2048 | |
c64a89d6 | 321 | #else /* in flash */ |
5a1aceb0 | 322 | # define CONFIG_ENV_IS_IN_FLASH 1 |
ee152983 | 323 | # ifdef CONFIG_STXSSA_4M |
0e8d1586 | 324 | # define CONFIG_ENV_SECT_SIZE 0x20000 |
ee152983 | 325 | # else /* default configuration - 64 MiB flash */ |
0e8d1586 | 326 | # define CONFIG_ENV_SECT_SIZE 0x40000 |
ee152983 | 327 | # endif |
6d0f6bcf | 328 | # define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE - CONFIG_ENV_SECT_SIZE) |
0e8d1586 JCPV |
329 | # define CONFIG_ENV_SIZE 0x4000 |
330 | # define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR - CONFIG_ENV_SECT_SIZE) | |
331 | # define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
35171dc0 DM |
332 | #endif |
333 | ||
35171dc0 | 334 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ |
6d0f6bcf | 335 | #define CONFIG_SYS_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ |
35171dc0 | 336 | |
c64a89d6 WD |
337 | #define CONFIG_TIMESTAMP /* Print image info with ts */ |
338 | ||
2835e518 | 339 | |
079a136c JL |
340 | /* |
341 | * BOOTP options | |
342 | */ | |
343 | #define CONFIG_BOOTP_BOOTFILESIZE | |
344 | #define CONFIG_BOOTP_BOOTPATH | |
345 | #define CONFIG_BOOTP_GATEWAY | |
346 | #define CONFIG_BOOTP_HOSTNAME | |
347 | ||
348 | ||
2835e518 JL |
349 | /* |
350 | * Command line configuration. | |
351 | */ | |
352 | #include <config_cmd_default.h> | |
353 | ||
e1893815 WD |
354 | #define CONFIG_CMD_DATE |
355 | #define CONFIG_CMD_DHCP | |
356 | #define CONFIG_CMD_EEPROM | |
2835e518 | 357 | #define CONFIG_CMD_I2C |
e1893815 WD |
358 | #define CONFIG_CMD_NFS |
359 | #define CONFIG_CMD_PING | |
360 | #define CONFIG_CMD_SNTP | |
199e262e | 361 | #define CONFIG_CMD_REGINFO |
2835e518 JL |
362 | |
363 | #if defined(CONFIG_PCI) | |
364 | #define CONFIG_CMD_PCI | |
365 | #endif | |
366 | ||
367 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
368 | #define CONFIG_CMD_MII | |
369 | #endif | |
370 | ||
6d0f6bcf | 371 | #if defined(CONFIG_SYS_RAMBOOT) |
bdab39d3 | 372 | #undef CONFIG_CMD_SAVEENV |
2835e518 | 373 | #undef CONFIG_CMD_LOADS |
35171dc0 | 374 | #else |
2835e518 | 375 | #define CONFIG_CMD_ELF |
35171dc0 | 376 | #endif |
2835e518 | 377 | |
35171dc0 DM |
378 | |
379 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
380 | ||
381 | /* | |
382 | * Miscellaneous configurable options | |
383 | */ | |
6d0f6bcf JCPV |
384 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
385 | #define CONFIG_SYS_PROMPT "SSA=> " /* Monitor Command Prompt */ | |
ef0df52a | 386 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 387 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
35171dc0 | 388 | #else |
6d0f6bcf | 389 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
35171dc0 | 390 | #endif |
6d0f6bcf JCPV |
391 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
392 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
393 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
394 | #define CONFIG_SYS_LOAD_ADDR 0x1000000 /* default load address */ | |
395 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
35171dc0 DM |
396 | |
397 | /* | |
398 | * For booting Linux, the board info and command line data | |
399 | * have to be in the first 8 MB of memory, since this is | |
400 | * the maximum mapped by the Linux kernel during initialization. | |
401 | */ | |
6d0f6bcf | 402 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
35171dc0 | 403 | |
ef0df52a | 404 | #if defined(CONFIG_CMD_KGDB) |
35171dc0 DM |
405 | #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ |
406 | #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ | |
407 | #endif | |
408 | ||
409 | /*Note: change below for your network setting!!! */ | |
410 | #if defined(CONFIG_TSEC_ENET) || defined(CONFIG_ETHER_ON_FCC) | |
10327dc5 | 411 | #define CONFIG_HAS_ETH0 |
35171dc0 DM |
412 | #define CONFIG_ETHADDR 00:e0:0c:07:9b:8a |
413 | #define CONFIG_HAS_ETH1 | |
414 | #define CONFIG_ETH1ADDR 00:e0:0c:07:9b:8b | |
415 | #define CONFIG_HAS_ETH2 | |
416 | #define CONFIG_ETH2ADDR 00:e0:0c:07:9b:8c | |
417 | #endif | |
418 | ||
c64a89d6 WD |
419 | /* |
420 | * Environment in EEPROM is compatible with different flash sector sizes, | |
421 | * but only little space is available, so we use a very simple setup. | |
422 | * With environment in flash, we use a more powerful default configuration. | |
423 | */ | |
bb1f8b4f | 424 | #ifdef CONFIG_ENV_IS_IN_EEPROM /* use restricted "standard" environment */ |
c64a89d6 | 425 | |
f1152f8c | 426 | #define CONFIG_BAUDRATE 38400 |
c64a89d6 WD |
427 | |
428 | #define CONFIG_BOOTDELAY 3 /* -1 disable autoboot */ | |
429 | #define CONFIG_BOOTCOMMAND "bootm 0xffc00000 0xffd00000" | |
430 | #define CONFIG_BOOTARGS "root=/dev/nfs rw ip=any console=ttyS1,$baudrate" | |
53677ef1 | 431 | #define CONFIG_SERVERIP 192.168.85.1 |
f1152f8c | 432 | #define CONFIG_IPADDR 192.168.85.60 |
35171dc0 DM |
433 | #define CONFIG_GATEWAYIP 192.168.85.1 |
434 | #define CONFIG_NETMASK 255.255.255.0 | |
53677ef1 WD |
435 | #define CONFIG_HOSTNAME STX_SSA |
436 | #define CONFIG_ROOTPATH /gppproot | |
437 | #define CONFIG_BOOTFILE uImage | |
35171dc0 DM |
438 | #define CONFIG_LOADADDR 0x1000000 |
439 | ||
c64a89d6 WD |
440 | #else /* ENV IS IN FLASH -- use a full-blown envionment */ |
441 | ||
f1152f8c | 442 | #define CONFIG_BAUDRATE 115200 |
c64a89d6 WD |
443 | |
444 | #define CONFIG_BOOTDELAY 5 /* -1 disable autoboot */ | |
445 | ||
446 | #define CONFIG_PREBOOT "echo;" \ | |
447 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
448 | "echo" | |
449 | ||
450 | #undef CONFIG_BOOTARGS /* the boot command will set bootargs */ | |
451 | ||
452 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
453 | "hostname=gp3ssa\0" \ | |
454 | "bootfile=/tftpboot/gp3ssa/uImage\0" \ | |
455 | "loadaddr=400000\0" \ | |
456 | "netdev=eth0\0" \ | |
457 | "consdev=ttyS1\0" \ | |
458 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ | |
459 | "nfsroot=$serverip:$rootpath\0" \ | |
460 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ | |
461 | "addip=setenv bootargs $bootargs " \ | |
462 | "ip=$ipaddr:$serverip:$gatewayip:$netmask" \ | |
463 | ":$hostname:$netdev:off panic=1\0" \ | |
464 | "addcons=setenv bootargs $bootargs " \ | |
465 | "console=$consdev,$baudrate\0" \ | |
466 | "flash_nfs=run nfsargs addip addcons;" \ | |
467 | "bootm $kernel_addr\0" \ | |
468 | "flash_self=run ramargs addip addcons;" \ | |
469 | "bootm $kernel_addr $ramdisk_addr\0" \ | |
470 | "net_nfs=tftp $loadaddr $bootfile;" \ | |
471 | "run nfsargs addip addcons;bootm\0" \ | |
472 | "rootpath=/opt/eldk/ppc_85xx\0" \ | |
473 | "kernel_addr=FC000000\0" \ | |
474 | "ramdisk_addr=FC200000\0" \ | |
475 | "" | |
476 | #define CONFIG_BOOTCOMMAND "run flash_self" | |
477 | ||
bb1f8b4f | 478 | #endif /* CONFIG_ENV_IS_IN_EEPROM */ |
c64a89d6 | 479 | |
35171dc0 | 480 | #endif /* __CONFIG_H */ |