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6bdf4306 WD |
1 | /* |
2 | * (C) Copyright 2000-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com | |
26 | * U-Boot port on STx XTc 8xx board | |
27 | * Mostly copied from Panto's NETTA2 board. | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC875 1 /* This is a MPC875 CPU */ | |
39 | #define CONFIG_STXXTC 1 /* ...on a STx XTc board */ | |
40 | ||
2ae18241 WD |
41 | #define CONFIG_SYS_TEXT_BASE 0x40F00000 |
42 | ||
6bdf4306 WD |
43 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ |
44 | #undef CONFIG_8xx_CONS_SMC2 | |
45 | #undef CONFIG_8xx_CONS_NONE | |
46 | ||
670d9f13 | 47 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ |
6bdf4306 WD |
48 | |
49 | #define CONFIG_XIN 10000000 /* 10 MHz input xtal */ | |
50 | ||
51 | /* Select one of few clock rates defined later in this file. | |
52 | */ | |
53 | /* #define MPC8XX_HZ 50000000 */ | |
54 | #define MPC8XX_HZ 66666666 | |
55 | ||
56 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ | |
57 | ||
58 | #if 0 | |
59 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
60 | #else | |
61 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
62 | #endif | |
63 | ||
64 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
65 | ||
66 | #undef CONFIG_BOOTARGS | |
67 | #define CONFIG_BOOTCOMMAND \ | |
53677ef1 WD |
68 | "tftpboot; " \ |
69 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
70 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
6bdf4306 WD |
71 | "bootm" |
72 | ||
74de7aef | 73 | #define CONFIG_SOURCE |
6bdf4306 | 74 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ |
6d0f6bcf | 75 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
6bdf4306 WD |
76 | |
77 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
78 | ||
79 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
80 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
81 | ||
d3b8c1a7 JL |
82 | /* |
83 | * BOOTP options | |
84 | */ | |
85 | #define CONFIG_BOOTP_SUBNETMASK | |
86 | #define CONFIG_BOOTP_GATEWAY | |
87 | #define CONFIG_BOOTP_HOSTNAME | |
88 | #define CONFIG_BOOTP_BOOTPATH | |
89 | #define CONFIG_BOOTP_BOOTFILESIZE | |
90 | #define CONFIG_BOOTP_NISDOMAIN | |
91 | ||
6bdf4306 WD |
92 | |
93 | #undef CONFIG_MAC_PARTITION | |
94 | #undef CONFIG_DOS_PARTITION | |
95 | ||
96 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
97 | ||
53677ef1 | 98 | #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ |
6bdf4306 | 99 | #define FEC_ENET 1 /* eth.c needs it that way... */ |
6d0f6bcf | 100 | #undef CONFIG_SYS_DISCOVER_PHY |
6bdf4306 | 101 | #define CONFIG_MII 1 |
0f3ba7e9 | 102 | #define CONFIG_MII_INIT 1 |
6bdf4306 WD |
103 | #undef CONFIG_RMII |
104 | ||
105 | #define CONFIG_ETHER_ON_FEC1 1 | |
53677ef1 | 106 | #define CONFIG_FEC1_PHY 1 /* phy address of FEC */ |
6bdf4306 WD |
107 | #undef CONFIG_FEC1_PHY_NORXERR |
108 | ||
109 | #define CONFIG_ETHER_ON_FEC2 1 | |
110 | #define CONFIG_FEC2_PHY 3 | |
111 | #undef CONFIG_FEC2_PHY_NORXERR | |
112 | ||
113 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
114 | ||
ef0df52a JL |
115 | |
116 | /* | |
117 | * Command line configuration. | |
118 | */ | |
119 | #include <config_cmd_default.h> | |
120 | ||
121 | #define CONFIG_CMD_DHCP | |
122 | #define CONFIG_CMD_MII | |
ef0df52a JL |
123 | #define CONFIG_CMD_NFS |
124 | #define CONFIG_CMD_PING | |
125 | ||
6bdf4306 WD |
126 | |
127 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
128 | #define CONFIG_MISC_INIT_R | |
129 | ||
6bdf4306 WD |
130 | /* |
131 | * Miscellaneous configurable options | |
132 | */ | |
6d0f6bcf JCPV |
133 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
134 | #define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */ | |
6bdf4306 | 135 | |
6d0f6bcf JCPV |
136 | #define CONFIG_SYS_HUSH_PARSER 1 |
137 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
6bdf4306 | 138 | |
ef0df52a | 139 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 140 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
6bdf4306 | 141 | #else |
6d0f6bcf | 142 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
6bdf4306 | 143 | #endif |
6d0f6bcf JCPV |
144 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
145 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
146 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
6bdf4306 | 147 | |
6d0f6bcf JCPV |
148 | #define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */ |
149 | #define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
6bdf4306 | 150 | |
6d0f6bcf | 151 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
6bdf4306 | 152 | |
6d0f6bcf | 153 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
6bdf4306 | 154 | |
6d0f6bcf | 155 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
6bdf4306 WD |
156 | |
157 | /* | |
158 | * Low Level Configuration Settings | |
159 | * (address mappings, register initial values, etc.) | |
160 | * You should know what you are doing if you make changes here. | |
161 | */ | |
162 | /*----------------------------------------------------------------------- | |
163 | * Internal Memory Mapped Register | |
164 | */ | |
6d0f6bcf | 165 | #define CONFIG_SYS_IMMR 0xFF000000 |
6bdf4306 WD |
166 | |
167 | /*----------------------------------------------------------------------- | |
168 | * Definitions for initial stack pointer and data area (in DPRAM) | |
169 | */ | |
6d0f6bcf | 170 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 171 | #define CONFIG_SYS_INIT_RAM_SIZE 0x3000 /* Size of used area in DPRAM */ |
25ddd1fb | 172 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 173 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
6bdf4306 WD |
174 | |
175 | /*----------------------------------------------------------------------- | |
176 | * Start addresses for the final memory configuration | |
177 | * (Set up by the startup code) | |
6d0f6bcf | 178 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
6bdf4306 | 179 | */ |
6d0f6bcf JCPV |
180 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
181 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
6bdf4306 | 182 | #if defined(DEBUG) |
6d0f6bcf | 183 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ |
6bdf4306 | 184 | #else |
6d0f6bcf | 185 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ |
6bdf4306 WD |
186 | #endif |
187 | ||
188 | /* yes this is weird, I know :) */ | |
6d0f6bcf JCPV |
189 | #define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE | 0x00F00000) |
190 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
6bdf4306 | 191 | |
6d0f6bcf | 192 | #define CONFIG_SYS_RESET_ADDRESS 0x80000000 |
6bdf4306 WD |
193 | |
194 | /* | |
195 | * For booting Linux, the board info and command line data | |
196 | * have to be in the first 8 MB of memory, since this is | |
197 | * the maximum mapped by the Linux kernel during initialization. | |
198 | */ | |
6d0f6bcf | 199 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
6bdf4306 WD |
200 | |
201 | /*----------------------------------------------------------------------- | |
202 | * FLASH organization | |
203 | */ | |
5a1aceb0 | 204 | #define CONFIG_ENV_IS_IN_FLASH 1 |
0e8d1586 | 205 | #define CONFIG_ENV_SECT_SIZE 0x10000 |
6bdf4306 | 206 | |
6d0f6bcf | 207 | #define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000) |
0e8d1586 JCPV |
208 | #define CONFIG_ENV_OFFSET 0 |
209 | #define CONFIG_ENV_SIZE 0x4000 | |
6bdf4306 | 210 | |
6d0f6bcf | 211 | #define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000) |
0e8d1586 JCPV |
212 | #define CONFIG_ENV_OFFSET_REDUND 0 |
213 | #define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE | |
6bdf4306 | 214 | |
6d0f6bcf | 215 | #define CONFIG_SYS_FLASH_CFI 1 |
00b1883a | 216 | #define CONFIG_FLASH_CFI_DRIVER 1 |
6d0f6bcf JCPV |
217 | #undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ |
218 | #define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
219 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
6bdf4306 | 220 | |
6d0f6bcf | 221 | #define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 } |
6bdf4306 | 222 | |
6d0f6bcf | 223 | #define CONFIG_SYS_FLASH_PROTECTION |
6bdf4306 WD |
224 | |
225 | /*----------------------------------------------------------------------- | |
226 | * Cache Configuration | |
227 | */ | |
6d0f6bcf | 228 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
ef0df52a | 229 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 230 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
6bdf4306 WD |
231 | #endif |
232 | ||
233 | /*----------------------------------------------------------------------- | |
234 | * SYPCR - System Protection Control 11-9 | |
235 | * SYPCR can only be written once after reset! | |
236 | *----------------------------------------------------------------------- | |
237 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
238 | */ | |
239 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 240 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
6bdf4306 WD |
241 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
242 | #else | |
6d0f6bcf | 243 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) |
6bdf4306 WD |
244 | #endif |
245 | ||
246 | /*----------------------------------------------------------------------- | |
247 | * SIUMCR - SIU Module Configuration 11-6 | |
248 | *----------------------------------------------------------------------- | |
249 | * PCMCIA config., multi-function pin tri-state | |
250 | */ | |
6d0f6bcf | 251 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) |
6bdf4306 WD |
252 | |
253 | /*----------------------------------------------------------------------- | |
254 | * TBSCR - Time Base Status and Control 11-26 | |
255 | *----------------------------------------------------------------------- | |
256 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
257 | */ | |
6d0f6bcf | 258 | #define CONFIG_SYS_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) |
6bdf4306 WD |
259 | |
260 | /*----------------------------------------------------------------------- | |
261 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
262 | *----------------------------------------------------------------------- | |
263 | */ | |
6d0f6bcf | 264 | #define CONFIG_SYS_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) |
6bdf4306 WD |
265 | |
266 | /*----------------------------------------------------------------------- | |
267 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
268 | *----------------------------------------------------------------------- | |
269 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
270 | */ | |
6d0f6bcf | 271 | #define CONFIG_SYS_PISCR (PISCR_PS | PISCR_PITF) |
6bdf4306 WD |
272 | |
273 | /*----------------------------------------------------------------------- | |
274 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
275 | *----------------------------------------------------------------------- | |
276 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
277 | * interrupt status bit | |
278 | * | |
279 | */ | |
280 | ||
281 | #if CONFIG_XIN == 10000000 | |
282 | ||
283 | #if MPC8XX_HZ == 50000000 | |
6d0f6bcf | 284 | #define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ |
6bdf4306 | 285 | (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 286 | PLPRCR_TEXPS) |
6bdf4306 | 287 | #elif MPC8XX_HZ == 66666666 |
6d0f6bcf | 288 | #define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ |
6bdf4306 | 289 | (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ |
53677ef1 | 290 | PLPRCR_TEXPS) |
6bdf4306 WD |
291 | #else |
292 | #error unsupported CPU freq for XIN = 10MHz | |
293 | #endif | |
294 | #else | |
295 | #error unsupported freq for XIN (must be 10MHz) | |
296 | #endif | |
297 | ||
298 | ||
299 | /* | |
300 | *----------------------------------------------------------------------- | |
301 | * SCCR - System Clock and reset Control Register 15-27 | |
302 | *----------------------------------------------------------------------- | |
303 | * Set clock output, timebase and RTC source and divider, | |
304 | * power management and some other internal clocks | |
305 | * | |
306 | * Note: When TBS == 0 the timebase is independent of current cpu clock. | |
307 | */ | |
308 | ||
309 | #define SCCR_MASK SCCR_EBDF11 | |
310 | #if MPC8XX_HZ > 66666666 | |
6d0f6bcf | 311 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
6bdf4306 WD |
312 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
313 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
314 | SCCR_DFALCD00 | SCCR_EBDF01) | |
315 | #else | |
6d0f6bcf | 316 | #define CONFIG_SYS_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ |
6bdf4306 WD |
317 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ |
318 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
319 | SCCR_DFALCD00) | |
320 | #endif | |
321 | ||
322 | /*----------------------------------------------------------------------- | |
323 | * | |
324 | *----------------------------------------------------------------------- | |
325 | * | |
326 | */ | |
6d0f6bcf JCPV |
327 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
328 | #define CONFIG_SYS_DER 0 | |
6bdf4306 WD |
329 | |
330 | /* | |
331 | * Init Memory Controller: | |
332 | * | |
333 | * BR0/1 and OR0/1 (FLASH) | |
334 | */ | |
335 | ||
336 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
337 | #define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ | |
338 | ||
339 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
340 | * restrict access enough to keep SRAM working (if any) | |
341 | * but not too much to meddle with FLASH accesses | |
342 | */ | |
343 | ||
344 | #define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ | |
345 | ||
6d0f6bcf JCPV |
346 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 |
347 | #define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | |
6bdf4306 WD |
348 | |
349 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
6d0f6bcf | 350 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) |
6bdf4306 | 351 | |
6d0f6bcf JCPV |
352 | #define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) |
353 | #define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH) | |
354 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
6bdf4306 | 355 | |
6d0f6bcf JCPV |
356 | #define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH) |
357 | #define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
6bdf4306 WD |
358 | |
359 | /* | |
360 | * BR4 and OR4 (SDRAM) | |
361 | * | |
362 | */ | |
363 | #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
364 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ | |
365 | ||
366 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
6d0f6bcf | 367 | #define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) |
6bdf4306 | 368 | |
6d0f6bcf JCPV |
369 | #define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM) |
370 | #define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) | |
6bdf4306 WD |
371 | |
372 | /* | |
373 | * Memory Periodic Timer Prescaler | |
374 | */ | |
375 | ||
376 | /* | |
377 | * Memory Periodic Timer Prescaler | |
378 | * | |
379 | * The Divider for PTA (refresh timer) configuration is based on an | |
380 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
381 | * the number of chip selects (NCS) and the actually needed refresh | |
382 | * rate is done by setting MPTPR. | |
383 | * | |
384 | * PTA is calculated from | |
385 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
386 | * | |
387 | * gclk CPU clock (not bus clock!) | |
388 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
389 | * | |
390 | * 4096 Rows from SDRAM example configuration | |
391 | * 1000 factor s -> ms | |
392 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
393 | * 4 Number of refresh cycles per period | |
394 | * 64 Refresh cycle in ms per number of rows | |
395 | * -------------------------------------------- | |
396 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
397 | * | |
398 | * 50 MHz => 50.000.000 / Divider = 98 | |
399 | * 66 Mhz => 66.000.000 / Divider = 129 | |
400 | * 80 Mhz => 80.000.000 / Divider = 156 | |
401 | */ | |
402 | ||
6d0f6bcf | 403 | #define CONFIG_SYS_MAMR_PTA 234 |
6bdf4306 WD |
404 | |
405 | /* | |
406 | * For 16 MBit, refresh rates could be 31.3 us | |
407 | * (= 64 ms / 2K = 125 / quad bursts). | |
408 | * For a simpler initialization, 15.6 us is used instead. | |
409 | * | |
6d0f6bcf JCPV |
410 | * #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks |
411 | * #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
6bdf4306 | 412 | */ |
6d0f6bcf JCPV |
413 | #define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ |
414 | #define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
6bdf4306 WD |
415 | |
416 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
6d0f6bcf JCPV |
417 | #define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ |
418 | #define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
6bdf4306 WD |
419 | |
420 | /* | |
421 | * MAMR settings for SDRAM | |
422 | */ | |
423 | ||
424 | /* 8 column SDRAM */ | |
6d0f6bcf | 425 | #define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
6bdf4306 WD |
426 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ |
427 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
428 | ||
429 | /* 9 column SDRAM */ | |
6d0f6bcf | 430 | #define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ |
6bdf4306 WD |
431 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ |
432 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
433 | ||
6bdf4306 WD |
434 | #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ |
435 | ||
436 | /****************************************************************/ | |
437 | ||
438 | #define NAND_SIZE 0x00010000 /* 64K */ | |
439 | #define NAND_BASE 0xF1000000 | |
440 | ||
6bdf4306 WD |
441 | /*****************************************************************************/ |
442 | ||
6d0f6bcf | 443 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
6bdf4306 WD |
444 | |
445 | /*****************************************************************************/ | |
446 | ||
447 | /* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, | |
448 | * CxOE and CxRESET. We use the CxOE. | |
449 | */ | |
450 | #define STATUS_LED_BIT 0x00000080 /* bit 24 */ | |
451 | ||
6d0f6bcf | 452 | #define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2) |
6bdf4306 WD |
453 | #define STATUS_LED_STATE STATUS_LED_BLINKING |
454 | ||
455 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
456 | #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ | |
457 | ||
458 | #ifndef __ASSEMBLY__ | |
459 | ||
460 | /* LEDs */ | |
461 | ||
462 | /* led_id_t is unsigned int mask */ | |
463 | typedef unsigned int led_id_t; | |
464 | ||
465 | #define __led_toggle(_msk) \ | |
466 | do { \ | |
6d0f6bcf | 467 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ |
6bdf4306 WD |
468 | } while(0) |
469 | ||
470 | #define __led_set(_msk, _st) \ | |
471 | do { \ | |
472 | if ((_st)) \ | |
6d0f6bcf | 473 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ |
6bdf4306 | 474 | else \ |
6d0f6bcf | 475 | ((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ |
6bdf4306 WD |
476 | } while(0) |
477 | ||
478 | #define __led_init(msk, st) __led_set(msk, st) | |
479 | ||
480 | #endif | |
481 | ||
482 | /******************************************************************************/ | |
483 | ||
6d0f6bcf JCPV |
484 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV 1 |
485 | #define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1 | |
486 | #define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1 | |
6bdf4306 WD |
487 | |
488 | /******************************************************************************/ | |
489 | ||
490 | /* use board specific hardware */ | |
491 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
492 | #define CONFIG_HW_WATCHDOG | |
6bdf4306 WD |
493 | |
494 | /*****************************************************************************/ | |
495 | ||
496 | #define CONFIG_AUTO_COMPLETE 1 | |
497 | #define CONFIG_CRC32_VERIFY 1 | |
498 | #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 | |
499 | ||
070610c5 WD |
500 | /*****************************************************************************/ |
501 | ||
62bcdda2 GVB |
502 | /* pass open firmware flattened device tree */ |
503 | #define CONFIG_OF_LIBFDT 1 | |
6bdf4306 | 504 | |
070610c5 | 505 | #define OF_TBCLK (MPC8XX_HZ / 16) |
6bdf4306 WD |
506 | |
507 | #endif /* __CONFIG_H */ |