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6bdf4306 WD |
1 | /* |
2 | * (C) Copyright 2000-2004 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com | |
26 | * U-Boot port on STx XTc 8xx board | |
27 | * Mostly copied from Panto's NETTA2 board. | |
28 | */ | |
29 | ||
30 | #ifndef __CONFIG_H | |
31 | #define __CONFIG_H | |
32 | ||
33 | /* | |
34 | * High Level Configuration Options | |
35 | * (easy to change) | |
36 | */ | |
37 | ||
38 | #define CONFIG_MPC875 1 /* This is a MPC875 CPU */ | |
39 | #define CONFIG_STXXTC 1 /* ...on a STx XTc board */ | |
40 | ||
41 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
42 | #undef CONFIG_8xx_CONS_SMC2 | |
43 | #undef CONFIG_8xx_CONS_NONE | |
44 | ||
670d9f13 | 45 | #define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */ |
6bdf4306 WD |
46 | |
47 | #define CONFIG_XIN 10000000 /* 10 MHz input xtal */ | |
48 | ||
49 | /* Select one of few clock rates defined later in this file. | |
50 | */ | |
51 | /* #define MPC8XX_HZ 50000000 */ | |
52 | #define MPC8XX_HZ 66666666 | |
53 | ||
54 | #define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ | |
55 | ||
56 | #if 0 | |
57 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
58 | #else | |
59 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
60 | #endif | |
61 | ||
62 | #undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */ | |
63 | ||
64 | #undef CONFIG_BOOTARGS | |
65 | #define CONFIG_BOOTCOMMAND \ | |
66 | "tftpboot; " \ | |
67 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ | |
68 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
69 | "bootm" | |
70 | ||
71 | #define CONFIG_AUTOSCRIPT | |
72 | #define CONFIG_LOADS_ECHO 0 /* echo off for serial download */ | |
73 | #undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ | |
74 | ||
75 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
76 | ||
77 | #define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
78 | #define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */ | |
79 | ||
80 | #define CONFIG_BOOTP_MASK (CONFIG_BOOTP_DEFAULT | CONFIG_BOOTP_BOOTFILESIZE | CONFIG_BOOTP_NISDOMAIN) | |
81 | ||
82 | #undef CONFIG_MAC_PARTITION | |
83 | #undef CONFIG_DOS_PARTITION | |
84 | ||
85 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
86 | ||
87 | #define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */ | |
88 | #define FEC_ENET 1 /* eth.c needs it that way... */ | |
89 | #undef CFG_DISCOVER_PHY | |
90 | #define CONFIG_MII 1 | |
91 | #undef CONFIG_RMII | |
92 | ||
93 | #define CONFIG_ETHER_ON_FEC1 1 | |
94 | #define CONFIG_FEC1_PHY 1 /* phy address of FEC */ | |
95 | #undef CONFIG_FEC1_PHY_NORXERR | |
96 | ||
97 | #define CONFIG_ETHER_ON_FEC2 1 | |
98 | #define CONFIG_FEC2_PHY 3 | |
99 | #undef CONFIG_FEC2_PHY_NORXERR | |
100 | ||
101 | #define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */ | |
102 | ||
ef0df52a JL |
103 | |
104 | /* | |
105 | * Command line configuration. | |
106 | */ | |
107 | #include <config_cmd_default.h> | |
108 | ||
109 | #define CONFIG_CMD_DHCP | |
110 | #define CONFIG_CMD_MII | |
111 | #define CONFIG_CMD_NAND | |
112 | #define CONFIG_CMD_NFS | |
113 | #define CONFIG_CMD_PING | |
114 | ||
6bdf4306 WD |
115 | |
116 | #define CONFIG_BOARD_EARLY_INIT_F 1 | |
117 | #define CONFIG_MISC_INIT_R | |
118 | ||
6bdf4306 WD |
119 | /* |
120 | * Miscellaneous configurable options | |
121 | */ | |
122 | #define CFG_LONGHELP /* undef to save memory */ | |
123 | #define CFG_PROMPT "xtc> " /* Monitor Command Prompt */ | |
124 | ||
125 | #define CFG_HUSH_PARSER 1 | |
126 | #define CFG_PROMPT_HUSH_PS2 "> " | |
127 | ||
ef0df52a | 128 | #if defined(CONFIG_CMD_KGDB) |
6bdf4306 WD |
129 | #define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ |
130 | #else | |
131 | #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ | |
132 | #endif | |
133 | #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ | |
134 | #define CFG_MAXARGS 16 /* max number of command args */ | |
135 | #define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ | |
136 | ||
137 | #define CFG_MEMTEST_START 0x0300000 /* memtest works on */ | |
138 | #define CFG_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */ | |
139 | ||
140 | #define CFG_LOAD_ADDR 0x100000 /* default load address */ | |
141 | ||
142 | #define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ | |
143 | ||
144 | #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } | |
145 | ||
146 | /* | |
147 | * Low Level Configuration Settings | |
148 | * (address mappings, register initial values, etc.) | |
149 | * You should know what you are doing if you make changes here. | |
150 | */ | |
151 | /*----------------------------------------------------------------------- | |
152 | * Internal Memory Mapped Register | |
153 | */ | |
154 | #define CFG_IMMR 0xFF000000 | |
155 | ||
156 | /*----------------------------------------------------------------------- | |
157 | * Definitions for initial stack pointer and data area (in DPRAM) | |
158 | */ | |
159 | #define CFG_INIT_RAM_ADDR CFG_IMMR | |
160 | #define CFG_INIT_RAM_END 0x3000 /* End of used area in DPRAM */ | |
161 | #define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ | |
162 | #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) | |
163 | #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET | |
164 | ||
165 | /*----------------------------------------------------------------------- | |
166 | * Start addresses for the final memory configuration | |
167 | * (Set up by the startup code) | |
168 | * Please note that CFG_SDRAM_BASE _must_ start at 0 | |
169 | */ | |
170 | #define CFG_SDRAM_BASE 0x00000000 | |
171 | #define CFG_FLASH_BASE 0x40000000 | |
172 | #if defined(DEBUG) | |
173 | #define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ | |
174 | #else | |
175 | #define CFG_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */ | |
176 | #endif | |
177 | ||
178 | /* yes this is weird, I know :) */ | |
179 | #define CFG_MONITOR_BASE (CFG_FLASH_BASE | 0x00F00000) | |
180 | #define CFG_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
181 | ||
182 | #define CFG_RESET_ADDRESS 0x80000000 | |
183 | ||
184 | /* | |
185 | * For booting Linux, the board info and command line data | |
186 | * have to be in the first 8 MB of memory, since this is | |
187 | * the maximum mapped by the Linux kernel during initialization. | |
188 | */ | |
189 | #define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ | |
190 | ||
191 | /*----------------------------------------------------------------------- | |
192 | * FLASH organization | |
193 | */ | |
194 | #define CFG_ENV_IS_IN_FLASH 1 | |
195 | #define CFG_ENV_SECT_SIZE 0x10000 | |
196 | ||
197 | #define CFG_ENV_ADDR (CFG_FLASH_BASE + 0x00000000) | |
198 | #define CFG_ENV_OFFSET 0 | |
199 | #define CFG_ENV_SIZE 0x4000 | |
200 | ||
201 | #define CFG_ENV_ADDR_REDUND (CFG_FLASH_BASE + 0x00010000) | |
202 | #define CFG_ENV_OFFSET_REDUND 0 | |
203 | #define CFG_ENV_SIZE_REDUND CFG_ENV_SIZE | |
204 | ||
205 | #define CFG_FLASH_CFI 1 | |
206 | #define CFG_FLASH_CFI_DRIVER 1 | |
207 | #undef CFG_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */ | |
208 | #define CFG_MAX_FLASH_SECT 128 /* max number of sectors on one chip */ | |
209 | #define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ | |
210 | ||
211 | #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE, CFG_FLASH_BASE + 0x2000000 } | |
212 | ||
213 | #define CFG_FLASH_PROTECTION | |
214 | ||
215 | /*----------------------------------------------------------------------- | |
216 | * Cache Configuration | |
217 | */ | |
218 | #define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ | |
ef0df52a | 219 | #if defined(CONFIG_CMD_KGDB) |
6bdf4306 WD |
220 | #define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
221 | #endif | |
222 | ||
223 | /*----------------------------------------------------------------------- | |
224 | * SYPCR - System Protection Control 11-9 | |
225 | * SYPCR can only be written once after reset! | |
226 | *----------------------------------------------------------------------- | |
227 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
228 | */ | |
229 | #if defined(CONFIG_WATCHDOG) | |
230 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ | |
231 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) | |
232 | #else | |
233 | #define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) | |
234 | #endif | |
235 | ||
236 | /*----------------------------------------------------------------------- | |
237 | * SIUMCR - SIU Module Configuration 11-6 | |
238 | *----------------------------------------------------------------------- | |
239 | * PCMCIA config., multi-function pin tri-state | |
240 | */ | |
241 | #define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E) | |
242 | ||
243 | /*----------------------------------------------------------------------- | |
244 | * TBSCR - Time Base Status and Control 11-26 | |
245 | *----------------------------------------------------------------------- | |
246 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
247 | */ | |
248 | #define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) | |
249 | ||
250 | /*----------------------------------------------------------------------- | |
251 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
252 | *----------------------------------------------------------------------- | |
253 | */ | |
254 | #define CFG_RTCSC (RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE) | |
255 | ||
256 | /*----------------------------------------------------------------------- | |
257 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
258 | *----------------------------------------------------------------------- | |
259 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
260 | */ | |
261 | #define CFG_PISCR (PISCR_PS | PISCR_PITF) | |
262 | ||
263 | /*----------------------------------------------------------------------- | |
264 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
265 | *----------------------------------------------------------------------- | |
266 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
267 | * interrupt status bit | |
268 | * | |
269 | */ | |
270 | ||
271 | #if CONFIG_XIN == 10000000 | |
272 | ||
273 | #if MPC8XX_HZ == 50000000 | |
274 | #define CFG_PLPRCR ((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \ | |
275 | (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ | |
276 | PLPRCR_TEXPS) | |
277 | #elif MPC8XX_HZ == 66666666 | |
278 | #define CFG_PLPRCR ((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \ | |
279 | (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \ | |
280 | PLPRCR_TEXPS) | |
281 | #else | |
282 | #error unsupported CPU freq for XIN = 10MHz | |
283 | #endif | |
284 | #else | |
285 | #error unsupported freq for XIN (must be 10MHz) | |
286 | #endif | |
287 | ||
288 | ||
289 | /* | |
290 | *----------------------------------------------------------------------- | |
291 | * SCCR - System Clock and reset Control Register 15-27 | |
292 | *----------------------------------------------------------------------- | |
293 | * Set clock output, timebase and RTC source and divider, | |
294 | * power management and some other internal clocks | |
295 | * | |
296 | * Note: When TBS == 0 the timebase is independent of current cpu clock. | |
297 | */ | |
298 | ||
299 | #define SCCR_MASK SCCR_EBDF11 | |
300 | #if MPC8XX_HZ > 66666666 | |
301 | #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ | |
302 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
303 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
304 | SCCR_DFALCD00 | SCCR_EBDF01) | |
305 | #else | |
306 | #define CFG_SCCR (/* SCCR_TBS | */ SCCR_CRQEN | \ | |
307 | SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ | |
308 | SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ | |
309 | SCCR_DFALCD00) | |
310 | #endif | |
311 | ||
312 | /*----------------------------------------------------------------------- | |
313 | * | |
314 | *----------------------------------------------------------------------- | |
315 | * | |
316 | */ | |
317 | /*#define CFG_DER 0x2002000F*/ | |
318 | #define CFG_DER 0 | |
319 | ||
320 | /* | |
321 | * Init Memory Controller: | |
322 | * | |
323 | * BR0/1 and OR0/1 (FLASH) | |
324 | */ | |
325 | ||
326 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
327 | #define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */ | |
328 | ||
329 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
330 | * restrict access enough to keep SRAM working (if any) | |
331 | * but not too much to meddle with FLASH accesses | |
332 | */ | |
333 | ||
334 | #define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */ | |
335 | ||
336 | #define CFG_REMAP_OR_AM 0x80000000 | |
337 | #define CFG_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | |
338 | ||
339 | /* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */ | |
340 | #define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_BI | OR_SCY_5_CLK | OR_TRLX) | |
341 | ||
342 | #define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) | |
343 | #define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) | |
344 | #define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
345 | ||
346 | #define CFG_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CFG_OR_TIMING_FLASH) | |
347 | #define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V ) | |
348 | ||
349 | /* | |
350 | * BR4 and OR4 (SDRAM) | |
351 | * | |
352 | */ | |
353 | #define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */ | |
354 | #define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */ | |
355 | ||
356 | /* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ | |
357 | #define CFG_OR_TIMING_SDRAM (OR_CSNT_SAM | OR_G5LS) | |
358 | ||
359 | #define CFG_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CFG_OR_TIMING_SDRAM) | |
360 | #define CFG_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V) | |
361 | ||
362 | /* | |
363 | * Memory Periodic Timer Prescaler | |
364 | */ | |
365 | ||
366 | /* | |
367 | * Memory Periodic Timer Prescaler | |
368 | * | |
369 | * The Divider for PTA (refresh timer) configuration is based on an | |
370 | * example SDRAM configuration (64 MBit, one bank). The adjustment to | |
371 | * the number of chip selects (NCS) and the actually needed refresh | |
372 | * rate is done by setting MPTPR. | |
373 | * | |
374 | * PTA is calculated from | |
375 | * PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS) | |
376 | * | |
377 | * gclk CPU clock (not bus clock!) | |
378 | * Trefresh Refresh cycle * 4 (four word bursts used) | |
379 | * | |
380 | * 4096 Rows from SDRAM example configuration | |
381 | * 1000 factor s -> ms | |
382 | * 32 PTP (pre-divider from MPTPR) from SDRAM example configuration | |
383 | * 4 Number of refresh cycles per period | |
384 | * 64 Refresh cycle in ms per number of rows | |
385 | * -------------------------------------------- | |
386 | * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000 | |
387 | * | |
388 | * 50 MHz => 50.000.000 / Divider = 98 | |
389 | * 66 Mhz => 66.000.000 / Divider = 129 | |
390 | * 80 Mhz => 80.000.000 / Divider = 156 | |
391 | */ | |
392 | ||
393 | #define CFG_MAMR_PTA 234 | |
394 | ||
395 | /* | |
396 | * For 16 MBit, refresh rates could be 31.3 us | |
397 | * (= 64 ms / 2K = 125 / quad bursts). | |
398 | * For a simpler initialization, 15.6 us is used instead. | |
399 | * | |
400 | * #define CFG_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks | |
401 | * #define CFG_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank | |
402 | */ | |
403 | #define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */ | |
404 | #define CFG_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */ | |
405 | ||
406 | /* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */ | |
407 | #define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */ | |
408 | #define CFG_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */ | |
409 | ||
410 | /* | |
411 | * MAMR settings for SDRAM | |
412 | */ | |
413 | ||
414 | /* 8 column SDRAM */ | |
415 | #define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
416 | MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ | |
417 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
418 | ||
419 | /* 9 column SDRAM */ | |
420 | #define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ | |
421 | MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ | |
422 | MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) | |
423 | ||
424 | /* | |
425 | * Internal Definitions | |
426 | * | |
427 | * Boot Flags | |
428 | */ | |
429 | #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ | |
430 | #define BOOTFLAG_WARM 0x02 /* Software reboot */ | |
431 | ||
432 | #define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */ | |
433 | ||
434 | /****************************************************************/ | |
435 | ||
436 | #define NAND_SIZE 0x00010000 /* 64K */ | |
437 | #define NAND_BASE 0xF1000000 | |
438 | ||
439 | /****************************************************************/ | |
440 | ||
441 | /* NAND */ | |
6db39708 | 442 | #define CFG_NAND_LEGACY |
6bdf4306 WD |
443 | #define CFG_NAND_BASE NAND_BASE |
444 | #define CONFIG_MTD_NAND_ECC_JFFS2 | |
445 | #define CONFIG_MTD_NAND_VERIFY_WRITE | |
446 | #define CONFIG_MTD_NAND_UNSAFE | |
447 | ||
448 | #define CFG_MAX_NAND_DEVICE 1 | |
449 | #undef NAND_NO_RB | |
450 | ||
451 | #define SECTORSIZE 512 | |
452 | #define ADDR_COLUMN 1 | |
453 | #define ADDR_PAGE 2 | |
454 | #define ADDR_COLUMN_PAGE 3 | |
455 | #define NAND_ChipID_UNKNOWN 0x00 | |
456 | #define NAND_MAX_FLOORS 1 | |
457 | #define NAND_MAX_CHIPS 1 | |
458 | ||
459 | /* ALE = PC15, CLE = PB23, CE = PA7, F_RY_BY = PA6 */ | |
460 | #define NAND_DISABLE_CE(nand) \ | |
461 | do { \ | |
462 | (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) |= (1 << (15 - 7)); \ | |
463 | } while(0) | |
464 | ||
465 | #define NAND_ENABLE_CE(nand) \ | |
466 | do { \ | |
467 | (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat) &= ~(1 << (15 - 7)); \ | |
468 | } while(0) | |
469 | ||
470 | #define NAND_CTL_CLRALE(nandptr) \ | |
471 | do { \ | |
472 | (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) &= ~(1 << (15 - 15)); \ | |
473 | } while(0) | |
474 | ||
475 | #define NAND_CTL_SETALE(nandptr) \ | |
476 | do { \ | |
477 | (((volatile immap_t *)CFG_IMMR)->im_ioport.iop_pcdat) |= (1 << (15 - 15)); \ | |
478 | } while(0) | |
479 | ||
480 | #define NAND_CTL_CLRCLE(nandptr) \ | |
481 | do { \ | |
482 | (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) &= ~(1 << (31 - 23)); \ | |
483 | } while(0) | |
484 | ||
485 | #define NAND_CTL_SETCLE(nandptr) \ | |
486 | do { \ | |
487 | (((volatile immap_t *)CFG_IMMR)->im_cpm.cp_pbdat) |= (1 << (31 - 23)); \ | |
488 | } while(0) | |
489 | ||
490 | #ifndef NAND_NO_RB | |
491 | #define NAND_WAIT_READY(nand) \ | |
492 | do { \ | |
493 | int _tries = 0; \ | |
494 | while ((((volatile immap_t *)CFG_IMMR)->im_ioport.iop_padat & (1 << (15 - 6))) == 0) \ | |
495 | if (++_tries > 100000) \ | |
496 | break; \ | |
497 | } while (0) | |
498 | #else | |
499 | #define NAND_WAIT_READY(nand) udelay(12) | |
500 | #endif | |
501 | ||
502 | #define WRITE_NAND_COMMAND(d, adr) \ | |
503 | do { \ | |
504 | *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ | |
505 | } while(0) | |
506 | ||
507 | #define WRITE_NAND_ADDRESS(d, adr) \ | |
508 | do { \ | |
509 | *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ | |
510 | } while(0) | |
511 | ||
512 | #define WRITE_NAND(d, adr) \ | |
513 | do { \ | |
514 | *(volatile unsigned char *)((unsigned long)(adr)) = (unsigned char)(d); \ | |
515 | } while(0) | |
516 | ||
517 | #define READ_NAND(adr) \ | |
518 | ((unsigned char)(*(volatile unsigned char *)(unsigned long)(adr))) | |
519 | ||
520 | /*****************************************************************************/ | |
521 | ||
522 | #define CFG_DIRECT_FLASH_TFTP | |
523 | #define CFG_DIRECT_NAND_TFTP | |
524 | ||
525 | /*****************************************************************************/ | |
526 | ||
527 | /* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB, | |
528 | * CxOE and CxRESET. We use the CxOE. | |
529 | */ | |
530 | #define STATUS_LED_BIT 0x00000080 /* bit 24 */ | |
531 | ||
532 | #define STATUS_LED_PERIOD (CFG_HZ / 2) | |
533 | #define STATUS_LED_STATE STATUS_LED_BLINKING | |
534 | ||
535 | #define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */ | |
536 | #define STATUS_LED_BOOT 0 /* LED 0 used for boot status */ | |
537 | ||
538 | #ifndef __ASSEMBLY__ | |
539 | ||
540 | /* LEDs */ | |
541 | ||
542 | /* led_id_t is unsigned int mask */ | |
543 | typedef unsigned int led_id_t; | |
544 | ||
545 | #define __led_toggle(_msk) \ | |
546 | do { \ | |
547 | ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \ | |
548 | } while(0) | |
549 | ||
550 | #define __led_set(_msk, _st) \ | |
551 | do { \ | |
552 | if ((_st)) \ | |
553 | ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \ | |
554 | else \ | |
555 | ((volatile immap_t *)CFG_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \ | |
556 | } while(0) | |
557 | ||
558 | #define __led_init(msk, st) __led_set(msk, st) | |
559 | ||
560 | #endif | |
561 | ||
562 | /******************************************************************************/ | |
563 | ||
564 | #define CFG_CONSOLE_IS_IN_ENV 1 | |
565 | #define CFG_CONSOLE_OVERWRITE_ROUTINE 1 | |
566 | #define CFG_CONSOLE_ENV_OVERWRITE 1 | |
567 | ||
568 | /******************************************************************************/ | |
569 | ||
570 | /* use board specific hardware */ | |
571 | #undef CONFIG_WATCHDOG /* watchdog disabled */ | |
572 | #define CONFIG_HW_WATCHDOG | |
573 | #define CONFIG_SHOW_ACTIVITY | |
574 | ||
575 | /*****************************************************************************/ | |
576 | ||
577 | #define CONFIG_AUTO_COMPLETE 1 | |
578 | #define CONFIG_CRC32_VERIFY 1 | |
579 | #define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1 | |
580 | ||
070610c5 WD |
581 | /*****************************************************************************/ |
582 | ||
583 | /* pass open firmware flat tree */ | |
584 | #define CONFIG_OF_FLAT_TREE 1 | |
6bdf4306 | 585 | |
070610c5 WD |
586 | /* maximum size of the flat tree (8K) */ |
587 | #define OF_FLAT_TREE_MAX_SIZE 8192 | |
6bdf4306 | 588 | |
070610c5 WD |
589 | #define OF_CPU "PowerPC,MPC870@0" |
590 | #define OF_TBCLK (MPC8XX_HZ / 16) | |
e4f880ed KG |
591 | #define CONFIG_OF_HAS_BD_T 1 |
592 | #define CONFIG_OF_HAS_UBOOT_ENV 1 | |
6bdf4306 WD |
593 | |
594 | #endif /* __CONFIG_H */ |