[people/ms/u-boot.git] / include / configs / stxxtc.h

/*
 * (C) Copyright 2000-2004
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
 * U-Boot port on STx XTc 8xx board
 * Mostly copied from Panto's NETTA2 board.
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */

#define CONFIG_MPC875		1	/* This is a MPC875 CPU		*/
#define CONFIG_STXXTC		1	/* ...on a STx XTc  board	*/

#define	CONFIG_SYS_TEXT_BASE	0x40F00000

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE

#define CONFIG_BAUDRATE		115200	/* console baudrate = 115.2kbps	*/

#define CONFIG_XIN		10000000	/* 10 MHz input xtal */

/* Select one of few clock rates defined later in this file.
*/
/* #define MPC8XX_HZ		50000000 */
#define MPC8XX_HZ		66666666

#define CONFIG_8xx_GCLK_FREQ	MPC8XX_HZ

#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	5	/* autoboot after 5 seconds	*/
#endif

#undef	CONFIG_CLOCKS_IN_MHZ	/* clocks NOT passsed to Linux in MHz */

#undef	CONFIG_BOOTARGS
#define CONFIG_BOOTCOMMAND							\
	"tftpboot; "								\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"bootm"

#define CONFIG_SOURCE
#define CONFIG_LOADS_ECHO	0	/* echo off for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/

#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/

#define	CONFIG_STATUS_LED	1	/* Status LED enabled		*/
#define CONFIG_BOARD_SPECIFIC_LED	/* version has board specific leds */

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE
#define CONFIG_BOOTP_NISDOMAIN


#undef CONFIG_MAC_PARTITION
#undef CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/

#define	CONFIG_NET_MULTI	1	/* the only way to get the FEC in */
#define	FEC_ENET		1	/* eth.c needs it that way... */
#undef CONFIG_SYS_DISCOVER_PHY
#define CONFIG_MII		1
#define CONFIG_MII_INIT		1
#undef CONFIG_RMII

#define CONFIG_ETHER_ON_FEC1	1
#define CONFIG_FEC1_PHY		1	/* phy address of FEC */
#undef CONFIG_FEC1_PHY_NORXERR

#define CONFIG_ETHER_ON_FEC2	1
#define CONFIG_FEC2_PHY		3
#undef CONFIG_FEC2_PHY_NORXERR

#define CONFIG_ENV_OVERWRITE	1	/* allow modification of vendor params */


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_DHCP
#define CONFIG_CMD_MII
#define CONFIG_CMD_NFS
#define CONFIG_CMD_PING


#define CONFIG_BOARD_EARLY_INIT_F	1
#define CONFIG_MISC_INIT_R

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"xtc> "		/* Monitor Command Prompt	*/

#define CONFIG_SYS_HUSH_PARSER	1
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0300000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0700000	/* 3 ... 7 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_END	0x3000	/* End of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#if defined(DEBUG)
#define	CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 256 kB for Monitor	*/
#else
#define	CONFIG_SYS_MONITOR_LEN		(192 << 10)	/* Reserve 192 kB for Monitor	*/
#endif

/* yes this is weird, I know :) */
#define CONFIG_SYS_MONITOR_BASE	(CONFIG_SYS_FLASH_BASE | 0x00F00000)
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

#define CONFIG_SYS_RESET_ADDRESS	0x80000000

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define	CONFIG_ENV_IS_IN_FLASH	1
#define CONFIG_ENV_SECT_SIZE	0x10000

#define	CONFIG_ENV_ADDR		(CONFIG_SYS_FLASH_BASE + 0x00000000)
#define CONFIG_ENV_OFFSET		0
#define	CONFIG_ENV_SIZE		0x4000

#define CONFIG_ENV_ADDR_REDUND	(CONFIG_SYS_FLASH_BASE + 0x00010000)
#define CONFIG_ENV_OFFSET_REDUND	0
#define CONFIG_ENV_SIZE_REDUND	CONFIG_ENV_SIZE

#define CONFIG_SYS_FLASH_CFI		1
#define CONFIG_FLASH_CFI_DRIVER	1
#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE	/* use buffered writes (20x faster) */
#define CONFIG_SYS_MAX_FLASH_SECT	128	/* max number of sectors on one chip */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks	*/

#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }

#define CONFIG_SYS_FLASH_PROTECTION

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs */
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value */
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP)
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01 | SIUMCR_FRC | SIUMCR_GB5E)

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	(TBSCR_REFA | TBSCR_REFB | TBSCR_TBF)

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	(RTCSC_SEC | RTCSC_ALR | RTCSC_RTF| RTCSC_RTE)

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	(PISCR_PS | PISCR_PITF)

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 *
 */

#if CONFIG_XIN == 10000000

#if MPC8XX_HZ == 50000000
#define CONFIG_SYS_PLPRCR	((0 << PLPRCR_MFN_SHIFT) | (0 << PLPRCR_MFD_SHIFT) | \
			 (1 << PLPRCR_S_SHIFT) | (10 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
			 PLPRCR_TEXPS)
#elif MPC8XX_HZ == 66666666
#define CONFIG_SYS_PLPRCR	((1 << PLPRCR_MFN_SHIFT) | (2 << PLPRCR_MFD_SHIFT) | \
			 (1 << PLPRCR_S_SHIFT) | (13 << PLPRCR_MFI_SHIFT) | (0 << PLPRCR_PDF_SHIFT) | \
			 PLPRCR_TEXPS)
#else
#error unsupported CPU freq for XIN = 10MHz
#endif
#else
#error unsupported freq for XIN (must be 10MHz)
#endif


/*
 *-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 *
 * Note: When TBS == 0 the timebase is independent of current cpu clock.
 */

#define SCCR_MASK	SCCR_EBDF11
#if MPC8XX_HZ > 66666666
#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00 | SCCR_EBDF01)
#else
#define CONFIG_SYS_SCCR	(/* SCCR_TBS     | */ SCCR_CRQEN | \
			 SCCR_COM00   | SCCR_DFSYNC00 | SCCR_DFBRG00  | \
			 SCCR_DFNL000 | SCCR_DFNH000  | SCCR_DFLCD000 | \
			 SCCR_DFALCD00)
#endif

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x42000000	/* FLASH bank #1	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */

#define FLASH_BANK_MAX_SIZE	0x01000000	/* max size per chip */

#define CONFIG_SYS_REMAP_OR_AM		0x80000000
#define CONFIG_SYS_PRELIM_OR_AM	(0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))

/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1	*/
#define CONFIG_SYS_OR_TIMING_FLASH	(OR_CSNT_SAM  | OR_BI | OR_SCY_5_CLK | OR_TRLX)

#define CONFIG_SYS_OR0_REMAP	(CONFIG_SYS_REMAP_OR_AM  | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_OR0_PRELIM	(CONFIG_SYS_PRELIM_OR_AM | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )

#define CONFIG_SYS_OR1_PRELIM	((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR1_PRELIM	((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_PS_16 | BR_V )

/*
 * BR4 and OR4 (SDRAM)
 *
 */
#define SDRAM_BASE1_PRELIM	0x00000000	/* SDRAM bank #0	*/
#define	SDRAM_MAX_SIZE		(256 << 20)	/* max 256MB per bank	*/

/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care)	*/
#define CONFIG_SYS_OR_TIMING_SDRAM	(OR_CSNT_SAM | OR_G5LS)

#define CONFIG_SYS_OR4_PRELIM	((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) | CONFIG_SYS_OR_TIMING_SDRAM)
#define CONFIG_SYS_BR4_PRELIM	((SDRAM_BASE1_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_PS_32 | BR_V)

/*
 * Memory Periodic Timer Prescaler
 */

/*
 * Memory Periodic Timer Prescaler
 *
 * The Divider for PTA (refresh timer) configuration is based on an
 * example SDRAM configuration (64 MBit, one bank). The adjustment to
 * the number of chip selects (NCS) and the actually needed refresh
 * rate is done by setting MPTPR.
 *
 * PTA is calculated from
 *	PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
 *
 *	gclk	  CPU clock (not bus clock!)
 *	Trefresh  Refresh cycle * 4 (four word bursts used)
 *
 * 4096  Rows from SDRAM example configuration
 * 1000  factor s -> ms
 *   32  PTP (pre-divider from MPTPR) from SDRAM example configuration
 *    4  Number of refresh cycles per period
 *   64  Refresh cycle in ms per number of rows
 * --------------------------------------------
 * Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
 *
 * 50 MHz => 50.000.000 / Divider =  98
 * 66 Mhz => 66.000.000 / Divider = 129
 * 80 Mhz => 80.000.000 / Divider = 156
 */

#define CONFIG_SYS_MAMR_PTA		 234

/*
 * For 16 MBit, refresh rates could be 31.3 us
 * (= 64 ms / 2K = 125 / quad bursts).
 * For a simpler initialization, 15.6 us is used instead.
 *
 * #define CONFIG_SYS_MPTPR_2BK_2K	MPTPR_PTP_DIV32		for 2 banks
 * #define CONFIG_SYS_MPTPR_1BK_2K	MPTPR_PTP_DIV64		for 1 bank
 */
#define CONFIG_SYS_MPTPR_2BK_4K	MPTPR_PTP_DIV16		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_4K	MPTPR_PTP_DIV32		/* setting for 1 bank	*/

/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit		*/
#define CONFIG_SYS_MPTPR_2BK_8K	MPTPR_PTP_DIV8		/* setting for 2 banks	*/
#define CONFIG_SYS_MPTPR_1BK_8K	MPTPR_PTP_DIV16		/* setting for 1 bank	*/

/*
 * MAMR settings for SDRAM
 */

/* 8 column SDRAM */
#define CONFIG_SYS_MAMR_8COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

/* 9 column SDRAM */
#define CONFIG_SYS_MAMR_9COL	((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT)  | MAMR_PTAE	    |	\
			 MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 |	\
			 MAMR_RLFA_1X	 | MAMR_WLFA_1X	   | MAMR_TLFA_4X)

#define CONFIG_LAST_STAGE_INIT		/* needed to reset the damn phys */

/****************************************************************/

#define NAND_SIZE	0x00010000	/* 64K */
#define NAND_BASE	0xF1000000

/*****************************************************************************/

#define CONFIG_SYS_DIRECT_FLASH_TFTP

/*****************************************************************************/

/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
 * CxOE and CxRESET.  We use the CxOE.
 */
#define STATUS_LED_BIT		0x00000080		/* bit 24 */

#define STATUS_LED_PERIOD	(CONFIG_SYS_HZ / 2)
#define STATUS_LED_STATE	STATUS_LED_BLINKING

#define STATUS_LED_ACTIVE	0		/* LED on for bit == 0	*/
#define STATUS_LED_BOOT		0		/* LED 0 used for boot status */

#ifndef __ASSEMBLY__

/* LEDs */

/* led_id_t is unsigned int mask */
typedef unsigned int led_id_t;

#define __led_toggle(_msk) \
	do { \
		((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
	} while(0)

#define __led_set(_msk, _st) \
	do { \
		if ((_st)) \
			((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb |= (_msk); \
		else \
			((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
	} while(0)

#define __led_init(msk, st) __led_set(msk, st)

#endif

/******************************************************************************/

#define CONFIG_SYS_CONSOLE_IS_IN_ENV		1
#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE	1
#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE	1

/******************************************************************************/

/* use board specific hardware */
#undef	CONFIG_WATCHDOG			/* watchdog disabled		*/
#define CONFIG_HW_WATCHDOG

/*****************************************************************************/

#define CONFIG_AUTO_COMPLETE	1
#define CONFIG_CRC32_VERIFY	1
#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE	1

/*****************************************************************************/

/* pass open firmware flattened device tree */
#define CONFIG_OF_LIBFDT	1

#define OF_TBCLK		(MPC8XX_HZ / 16)

#endif	/* __CONFIG_H */
Commit	Line	Data
6bdf4306 WD	1	/*
	2	* (C) Copyright 2000-2004
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* Dan Malek, Embedded Edge, LLC, dan@embeddededge.com
	26	* U-Boot port on STx XTc 8xx board
	27	* Mostly copied from Panto's NETTA2 board.
	28	*/
	29
	30	#ifndef __CONFIG_H
	31	#define __CONFIG_H
	32
	33	/*
	34	* High Level Configuration Options
	35	* (easy to change)
	36	*/
	37
	38	#define CONFIG_MPC875 1 /* This is a MPC875 CPU */
	39	#define CONFIG_STXXTC 1 /* ...on a STx XTc board */
	40
2ae18241 WD	41	#define CONFIG_SYS_TEXT_BASE 0x40F00000
2ae18241 WD	42
6bdf4306 WD	43	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	44	#undef CONFIG_8xx_CONS_SMC2
	45	#undef CONFIG_8xx_CONS_NONE
	46
670d9f13	47	#define CONFIG_BAUDRATE 115200 /* console baudrate = 115.2kbps */
6bdf4306 WD	48
	49	#define CONFIG_XIN 10000000 /* 10 MHz input xtal */
	50
	51	/* Select one of few clock rates defined later in this file.
	52	*/
	53	/* #define MPC8XX_HZ 50000000 */
	54	#define MPC8XX_HZ 66666666
	55
	56	#define CONFIG_8xx_GCLK_FREQ MPC8XX_HZ
	57
	58	#if 0
	59	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	60	#else
	61	#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */
	62	#endif
	63
	64	#undef CONFIG_CLOCKS_IN_MHZ /* clocks NOT passsed to Linux in MHz */
	65
	66	#undef CONFIG_BOOTARGS
	67	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	68	"tftpboot; " \
	69	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
	70	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
6bdf4306 WD	71	"bootm"
6bdf4306 WD	72
74de7aef	73	#define CONFIG_SOURCE
6bdf4306	74	#define CONFIG_LOADS_ECHO 0 /* echo off for serial download */
6d0f6bcf	75	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
6bdf4306 WD	76
	77	#undef CONFIG_WATCHDOG /* watchdog disabled */
	78
	79	#define CONFIG_STATUS_LED 1 /* Status LED enabled */
	80	#define CONFIG_BOARD_SPECIFIC_LED /* version has board specific leds */
	81
d3b8c1a7 JL	82	/*
	83	* BOOTP options
	84	*/
	85	#define CONFIG_BOOTP_SUBNETMASK
	86	#define CONFIG_BOOTP_GATEWAY
	87	#define CONFIG_BOOTP_HOSTNAME
	88	#define CONFIG_BOOTP_BOOTPATH
	89	#define CONFIG_BOOTP_BOOTFILESIZE
	90	#define CONFIG_BOOTP_NISDOMAIN
	91
6bdf4306 WD	92
	93	#undef CONFIG_MAC_PARTITION
	94	#undef CONFIG_DOS_PARTITION
	95
	96	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	97
53677ef1	98	#define CONFIG_NET_MULTI 1 /* the only way to get the FEC in */
6bdf4306	99	#define FEC_ENET 1 /* eth.c needs it that way... */
6d0f6bcf	100	#undef CONFIG_SYS_DISCOVER_PHY
6bdf4306	101	#define CONFIG_MII 1
0f3ba7e9	102	#define CONFIG_MII_INIT 1
6bdf4306 WD	103	#undef CONFIG_RMII
	104
	105	#define CONFIG_ETHER_ON_FEC1 1
53677ef1	106	#define CONFIG_FEC1_PHY 1 /* phy address of FEC */
6bdf4306 WD	107	#undef CONFIG_FEC1_PHY_NORXERR
	108
	109	#define CONFIG_ETHER_ON_FEC2 1
	110	#define CONFIG_FEC2_PHY 3
	111	#undef CONFIG_FEC2_PHY_NORXERR
	112
	113	#define CONFIG_ENV_OVERWRITE 1 /* allow modification of vendor params */
	114
ef0df52a JL	115
	116	/*
	117	* Command line configuration.
	118	*/
	119	#include <config_cmd_default.h>
	120
	121	#define CONFIG_CMD_DHCP
	122	#define CONFIG_CMD_MII
ef0df52a JL	123	#define CONFIG_CMD_NFS
	124	#define CONFIG_CMD_PING
	125
6bdf4306 WD	126
	127	#define CONFIG_BOARD_EARLY_INIT_F 1
	128	#define CONFIG_MISC_INIT_R
	129
6bdf4306 WD	130	/*
	131	* Miscellaneous configurable options
	132	*/
6d0f6bcf JCPV	133	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	134	#define CONFIG_SYS_PROMPT "xtc> " /* Monitor Command Prompt */
6bdf4306	135
6d0f6bcf JCPV	136	#define CONFIG_SYS_HUSH_PARSER 1
6d0f6bcf JCPV	137	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
6bdf4306	138
ef0df52a	139	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	140	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
6bdf4306	141	#else
6d0f6bcf	142	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
6bdf4306	143	#endif
6d0f6bcf JCPV	144	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	145	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	146	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
6bdf4306	147
6d0f6bcf JCPV	148	#define CONFIG_SYS_MEMTEST_START 0x0300000 /* memtest works on */
6d0f6bcf JCPV	149	#define CONFIG_SYS_MEMTEST_END 0x0700000 /* 3 ... 7 MB in DRAM */
6bdf4306	150
6d0f6bcf	151	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
6bdf4306	152
6d0f6bcf	153	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
6bdf4306	154
6d0f6bcf	155	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
6bdf4306 WD	156
	157	/*
	158	* Low Level Configuration Settings
	159	* (address mappings, register initial values, etc.)
	160	* You should know what you are doing if you make changes here.
	161	*/
	162	/*-----------------------------------------------------------------------
	163	* Internal Memory Mapped Register
	164	*/
6d0f6bcf	165	#define CONFIG_SYS_IMMR 0xFF000000
6bdf4306 WD	166
	167	/*-----------------------------------------------------------------------
	168	* Definitions for initial stack pointer and data area (in DPRAM)
	169	*/
6d0f6bcf JCPV	170	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	171	#define CONFIG_SYS_INIT_RAM_END 0x3000 /* End of used area in DPRAM */
	172	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	173	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	174	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
6bdf4306 WD	175
	176	/*-----------------------------------------------------------------------
	177	* Start addresses for the final memory configuration
	178	* (Set up by the startup code)
6d0f6bcf	179	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
6bdf4306	180	*/
6d0f6bcf JCPV	181	#define CONFIG_SYS_SDRAM_BASE 0x00000000
6d0f6bcf JCPV	182	#define CONFIG_SYS_FLASH_BASE 0x40000000
6bdf4306	183	#if defined(DEBUG)
6d0f6bcf	184	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */
6bdf4306	185	#else
6d0f6bcf	186	#define CONFIG_SYS_MONITOR_LEN (192 << 10) /* Reserve 192 kB for Monitor */
6bdf4306 WD	187	#endif
	188
	189	/* yes this is weird, I know :) */
6d0f6bcf JCPV	190	#define CONFIG_SYS_MONITOR_BASE (CONFIG_SYS_FLASH_BASE \| 0x00F00000)
6d0f6bcf JCPV	191	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
6bdf4306	192
6d0f6bcf	193	#define CONFIG_SYS_RESET_ADDRESS 0x80000000
6bdf4306 WD	194
	195	/*
	196	* For booting Linux, the board info and command line data
	197	* have to be in the first 8 MB of memory, since this is
	198	* the maximum mapped by the Linux kernel during initialization.
	199	*/
6d0f6bcf	200	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
6bdf4306 WD	201
	202	/*-----------------------------------------------------------------------
	203	* FLASH organization
	204	*/
5a1aceb0	205	#define CONFIG_ENV_IS_IN_FLASH 1
0e8d1586	206	#define CONFIG_ENV_SECT_SIZE 0x10000
6bdf4306	207
6d0f6bcf	208	#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x00000000)
0e8d1586 JCPV	209	#define CONFIG_ENV_OFFSET 0
0e8d1586 JCPV	210	#define CONFIG_ENV_SIZE 0x4000
6bdf4306	211
6d0f6bcf	212	#define CONFIG_ENV_ADDR_REDUND (CONFIG_SYS_FLASH_BASE + 0x00010000)
0e8d1586 JCPV	213	#define CONFIG_ENV_OFFSET_REDUND 0
0e8d1586 JCPV	214	#define CONFIG_ENV_SIZE_REDUND CONFIG_ENV_SIZE
6bdf4306	215
6d0f6bcf	216	#define CONFIG_SYS_FLASH_CFI 1
00b1883a	217	#define CONFIG_FLASH_CFI_DRIVER 1
6d0f6bcf JCPV	218	#undef CONFIG_SYS_FLASH_USE_BUFFER_WRITE /* use buffered writes (20x faster) */
	219	#define CONFIG_SYS_MAX_FLASH_SECT 128 /* max number of sectors on one chip */
	220	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6bdf4306	221
6d0f6bcf	222	#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE + 0x2000000 }
6bdf4306	223
6d0f6bcf	224	#define CONFIG_SYS_FLASH_PROTECTION
6bdf4306 WD	225
	226	/*-----------------------------------------------------------------------
	227	* Cache Configuration
	228	*/
6d0f6bcf	229	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
ef0df52a	230	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	231	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
6bdf4306 WD	232	#endif
	233
	234	/*-----------------------------------------------------------------------
	235	* SYPCR - System Protection Control 11-9
	236	* SYPCR can only be written once after reset!
	237	*-----------------------------------------------------------------------
	238	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	239	*/
	240	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	241	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
6bdf4306 WD	242	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
6bdf4306 WD	243	#else
6d0f6bcf	244	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| SYPCR_SWP)
6bdf4306 WD	245	#endif
	246
	247	/*-----------------------------------------------------------------------
	248	* SIUMCR - SIU Module Configuration 11-6
	249	*-----------------------------------------------------------------------
	250	* PCMCIA config., multi-function pin tri-state
	251	*/
6d0f6bcf	252	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC00 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01 \| SIUMCR_FRC \| SIUMCR_GB5E)
6bdf4306 WD	253
	254	/*-----------------------------------------------------------------------
	255	* TBSCR - Time Base Status and Control 11-26
	256	*-----------------------------------------------------------------------
	257	* Clear Reference Interrupt Status, Timebase freezing enabled
	258	*/
6d0f6bcf	259	#define CONFIG_SYS_TBSCR (TBSCR_REFA \| TBSCR_REFB \| TBSCR_TBF)
6bdf4306 WD	260
	261	/*-----------------------------------------------------------------------
	262	* RTCSC - Real-Time Clock Status and Control Register 11-27
	263	*-----------------------------------------------------------------------
	264	*/
6d0f6bcf	265	#define CONFIG_SYS_RTCSC (RTCSC_SEC \| RTCSC_ALR \| RTCSC_RTF\| RTCSC_RTE)
6bdf4306 WD	266
	267	/*-----------------------------------------------------------------------
	268	* PISCR - Periodic Interrupt Status and Control 11-31
	269	*-----------------------------------------------------------------------
	270	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	271	*/
6d0f6bcf	272	#define CONFIG_SYS_PISCR (PISCR_PS \| PISCR_PITF)
6bdf4306 WD	273
	274	/*-----------------------------------------------------------------------
	275	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	276	*-----------------------------------------------------------------------
	277	* Reset PLL lock status sticky bit, timer expired status bit and timer
	278	* interrupt status bit
	279	*
	280	*/
	281
	282	#if CONFIG_XIN == 10000000
	283
	284	#if MPC8XX_HZ == 50000000
6d0f6bcf	285	#define CONFIG_SYS_PLPRCR ((0 << PLPRCR_MFN_SHIFT) \| (0 << PLPRCR_MFD_SHIFT) \| \
6bdf4306	286	(1 << PLPRCR_S_SHIFT) \| (10 << PLPRCR_MFI_SHIFT) \| (0 << PLPRCR_PDF_SHIFT) \| \
53677ef1	287	PLPRCR_TEXPS)
6bdf4306	288	#elif MPC8XX_HZ == 66666666
6d0f6bcf	289	#define CONFIG_SYS_PLPRCR ((1 << PLPRCR_MFN_SHIFT) \| (2 << PLPRCR_MFD_SHIFT) \| \
6bdf4306	290	(1 << PLPRCR_S_SHIFT) \| (13 << PLPRCR_MFI_SHIFT) \| (0 << PLPRCR_PDF_SHIFT) \| \
53677ef1	291	PLPRCR_TEXPS)
6bdf4306 WD	292	#else
	293	#error unsupported CPU freq for XIN = 10MHz
	294	#endif
	295	#else
	296	#error unsupported freq for XIN (must be 10MHz)
	297	#endif
	298
	299
	300	/*
	301	*-----------------------------------------------------------------------
	302	* SCCR - System Clock and reset Control Register 15-27
	303	*-----------------------------------------------------------------------
	304	* Set clock output, timebase and RTC source and divider,
	305	* power management and some other internal clocks
	306	*
	307	* Note: When TBS == 0 the timebase is independent of current cpu clock.
	308	*/
	309
	310	#define SCCR_MASK SCCR_EBDF11
	311	#if MPC8XX_HZ > 66666666
6d0f6bcf	312	#define CONFIG_SYS_SCCR (/* SCCR_TBS \| */ SCCR_CRQEN \| \
6bdf4306 WD	313	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	314	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	315	SCCR_DFALCD00 \| SCCR_EBDF01)
	316	#else
6d0f6bcf	317	#define CONFIG_SYS_SCCR (/* SCCR_TBS \| */ SCCR_CRQEN \| \
6bdf4306 WD	318	SCCR_COM00 \| SCCR_DFSYNC00 \| SCCR_DFBRG00 \| \
	319	SCCR_DFNL000 \| SCCR_DFNH000 \| SCCR_DFLCD000 \| \
	320	SCCR_DFALCD00)
	321	#endif
	322
	323	/*-----------------------------------------------------------------------
	324	*
	325	*-----------------------------------------------------------------------
	326	*
	327	*/
6d0f6bcf JCPV	328	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	329	#define CONFIG_SYS_DER 0
6bdf4306 WD	330
	331	/*
	332	* Init Memory Controller:
	333	*
	334	* BR0/1 and OR0/1 (FLASH)
	335	*/
	336
	337	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	338	#define FLASH_BASE1_PRELIM 0x42000000 /* FLASH bank #1 */
	339
	340	/* used to re-map FLASH both when starting from SRAM or FLASH:
	341	* restrict access enough to keep SRAM working (if any)
	342	* but not too much to meddle with FLASH accesses
	343	*/
	344
	345	#define FLASH_BANK_MAX_SIZE 0x01000000 /* max size per chip */
	346
6d0f6bcf JCPV	347	#define CONFIG_SYS_REMAP_OR_AM 0x80000000
6d0f6bcf JCPV	348	#define CONFIG_SYS_PRELIM_OR_AM (0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1))
6bdf4306 WD	349
6bdf4306 WD	350	/* FLASH timing: ACS = 11, TRLX = 0, CSNT = 1, SCY = 5, EHTR = 1 */
6d0f6bcf	351	#define CONFIG_SYS_OR_TIMING_FLASH (OR_CSNT_SAM \| OR_BI \| OR_SCY_5_CLK \| OR_TRLX)
6bdf4306	352
6d0f6bcf JCPV	353	#define CONFIG_SYS_OR0_REMAP (CONFIG_SYS_REMAP_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	354	#define CONFIG_SYS_OR0_PRELIM (CONFIG_SYS_PRELIM_OR_AM \| CONFIG_SYS_OR_TIMING_FLASH)
	355	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
6bdf4306	356
6d0f6bcf JCPV	357	#define CONFIG_SYS_OR1_PRELIM ((0xFFFFFFFFLU & ~(FLASH_BANK_MAX_SIZE - 1)) \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	358	#define CONFIG_SYS_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) \| BR_PS_16 \| BR_V )
6bdf4306 WD	359
	360	/*
	361	* BR4 and OR4 (SDRAM)
	362	*
	363	*/
	364	#define SDRAM_BASE1_PRELIM 0x00000000 /* SDRAM bank #0 */
	365	#define SDRAM_MAX_SIZE (256 << 20) /* max 256MB per bank */
	366
	367	/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */
6d0f6bcf	368	#define CONFIG_SYS_OR_TIMING_SDRAM (OR_CSNT_SAM \| OR_G5LS)
6bdf4306	369
6d0f6bcf JCPV	370	#define CONFIG_SYS_OR4_PRELIM ((0xFFFFFFFFLU & ~(SDRAM_MAX_SIZE - 1)) \| CONFIG_SYS_OR_TIMING_SDRAM)
6d0f6bcf JCPV	371	#define CONFIG_SYS_BR4_PRELIM ((SDRAM_BASE1_PRELIM & BR_BA_MSK) \| BR_MS_UPMA \| BR_PS_32 \| BR_V)
6bdf4306 WD	372
	373	/*
	374	* Memory Periodic Timer Prescaler
	375	*/
	376
	377	/*
	378	* Memory Periodic Timer Prescaler
	379	*
	380	* The Divider for PTA (refresh timer) configuration is based on an
	381	* example SDRAM configuration (64 MBit, one bank). The adjustment to
	382	* the number of chip selects (NCS) and the actually needed refresh
	383	* rate is done by setting MPTPR.
	384	*
	385	* PTA is calculated from
	386	* PTA = (gclk * Trefresh) / ((2 ^ (2 * DFBRG)) * PTP * NCS)
	387	*
	388	* gclk CPU clock (not bus clock!)
	389	* Trefresh Refresh cycle * 4 (four word bursts used)
	390	*
	391	* 4096 Rows from SDRAM example configuration
	392	* 1000 factor s -> ms
	393	* 32 PTP (pre-divider from MPTPR) from SDRAM example configuration
	394	* 4 Number of refresh cycles per period
	395	* 64 Refresh cycle in ms per number of rows
	396	* --------------------------------------------
	397	* Divider = 4096 * 32 * 1000 / (4 * 64) = 512000
	398	*
	399	* 50 MHz => 50.000.000 / Divider = 98
	400	* 66 Mhz => 66.000.000 / Divider = 129
	401	* 80 Mhz => 80.000.000 / Divider = 156
	402	*/
	403
6d0f6bcf	404	#define CONFIG_SYS_MAMR_PTA 234
6bdf4306 WD	405
	406	/*
	407	* For 16 MBit, refresh rates could be 31.3 us
	408	* (= 64 ms / 2K = 125 / quad bursts).
	409	* For a simpler initialization, 15.6 us is used instead.
	410	*
6d0f6bcf JCPV	411	* #define CONFIG_SYS_MPTPR_2BK_2K MPTPR_PTP_DIV32 for 2 banks
6d0f6bcf JCPV	412	* #define CONFIG_SYS_MPTPR_1BK_2K MPTPR_PTP_DIV64 for 1 bank
6bdf4306	413	*/
6d0f6bcf JCPV	414	#define CONFIG_SYS_MPTPR_2BK_4K MPTPR_PTP_DIV16 /* setting for 2 banks */
6d0f6bcf JCPV	415	#define CONFIG_SYS_MPTPR_1BK_4K MPTPR_PTP_DIV32 /* setting for 1 bank */
6bdf4306 WD	416
6bdf4306 WD	417	/* refresh rate 7.8 us (= 64 ms / 8K = 31.2 / quad bursts) for 256 MBit */
6d0f6bcf JCPV	418	#define CONFIG_SYS_MPTPR_2BK_8K MPTPR_PTP_DIV8 /* setting for 2 banks */
6d0f6bcf JCPV	419	#define CONFIG_SYS_MPTPR_1BK_8K MPTPR_PTP_DIV16 /* setting for 1 bank */
6bdf4306 WD	420
	421	/*
	422	* MAMR settings for SDRAM
	423	*/
	424
	425	/* 8 column SDRAM */
6d0f6bcf	426	#define CONFIG_SYS_MAMR_8COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
6bdf4306 WD	427	MAMR_AMA_TYPE_0 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A11 \| \
	428	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	429
	430	/* 9 column SDRAM */
6d0f6bcf	431	#define CONFIG_SYS_MAMR_9COL ((CONFIG_SYS_MAMR_PTA << MAMR_PTA_SHIFT) \| MAMR_PTAE \| \
6bdf4306 WD	432	MAMR_AMA_TYPE_1 \| MAMR_DSA_1_CYCL \| MAMR_G0CLA_A10 \| \
	433	MAMR_RLFA_1X \| MAMR_WLFA_1X \| MAMR_TLFA_4X)
	434
6bdf4306 WD	435	#define CONFIG_LAST_STAGE_INIT /* needed to reset the damn phys */
	436
	437	/****************************************************************/
	438
	439	#define NAND_SIZE 0x00010000 /* 64K */
	440	#define NAND_BASE 0xF1000000
	441
6bdf4306 WD	442	/*****************************************************************************/
6bdf4306 WD	443
6d0f6bcf	444	#define CONFIG_SYS_DIRECT_FLASH_TFTP
6bdf4306 WD	445
	446	/*****************************************************************************/
	447
	448	/* Status Leds are on the MODCK pins, which become the PCMCIA PGCRB,
	449	* CxOE and CxRESET. We use the CxOE.
	450	*/
	451	#define STATUS_LED_BIT 0x00000080 /* bit 24 */
	452
6d0f6bcf	453	#define STATUS_LED_PERIOD (CONFIG_SYS_HZ / 2)
6bdf4306 WD	454	#define STATUS_LED_STATE STATUS_LED_BLINKING
	455
	456	#define STATUS_LED_ACTIVE 0 /* LED on for bit == 0 */
	457	#define STATUS_LED_BOOT 0 /* LED 0 used for boot status */
	458
	459	#ifndef __ASSEMBLY__
	460
	461	/* LEDs */
	462
	463	/* led_id_t is unsigned int mask */
	464	typedef unsigned int led_id_t;
	465
	466	#define __led_toggle(_msk) \
	467	do { \
6d0f6bcf	468	((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb ^= (_msk); \
6bdf4306 WD	469	} while(0)
	470
	471	#define __led_set(_msk, _st) \
	472	do { \
	473	if ((_st)) \
6d0f6bcf	474	((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb \|= (_msk); \
6bdf4306	475	else \
6d0f6bcf	476	((volatile immap_t *)CONFIG_SYS_IMMR)->im_pcmcia.pcmc_pgcrb &= ~(_msk); \
6bdf4306 WD	477	} while(0)
	478
	479	#define __led_init(msk, st) __led_set(msk, st)
	480
	481	#endif
	482
	483	/******************************************************************************/
	484
6d0f6bcf JCPV	485	#define CONFIG_SYS_CONSOLE_IS_IN_ENV 1
	486	#define CONFIG_SYS_CONSOLE_OVERWRITE_ROUTINE 1
	487	#define CONFIG_SYS_CONSOLE_ENV_OVERWRITE 1
6bdf4306 WD	488
	489	/******************************************************************************/
	490
	491	/* use board specific hardware */
	492	#undef CONFIG_WATCHDOG /* watchdog disabled */
	493	#define CONFIG_HW_WATCHDOG
6bdf4306 WD	494
	495	/*****************************************************************************/
	496
	497	#define CONFIG_AUTO_COMPLETE 1
	498	#define CONFIG_CRC32_VERIFY 1
	499	#define CONFIG_HUSH_OLD_PARSER_COMPATIBLE 1
	500
070610c5 WD	501	/*****************************************************************************/
070610c5 WD	502
62bcdda2 GVB	503	/* pass open firmware flattened device tree */
62bcdda2 GVB	504	#define CONFIG_OF_LIBFDT 1
6bdf4306	505
070610c5	506	#define OF_TBCLK (MPC8XX_HZ / 16)
6bdf4306 WD	507
6bdf4306 WD	508	#endif /* __CONFIG_H */