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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
cba69eee IC |
2 | /* |
3 | * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net> | |
4 | * | |
5 | * (C) Copyright 2007-2011 | |
6 | * Allwinner Technology Co., Ltd. <www.allwinnertech.com> | |
7 | * Tom Cubie <tangliang@allwinnertech.com> | |
8 | * | |
9 | * Configuration settings for the Allwinner sunxi series of boards. | |
cba69eee IC |
10 | */ |
11 | ||
12 | #ifndef _SUNXI_COMMON_CONFIG_H | |
13 | #define _SUNXI_COMMON_CONFIG_H | |
14 | ||
daf6d399 | 15 | #include <asm/arch/cpu.h> |
e049fe28 HG |
16 | #include <linux/stringify.h> |
17 | ||
d29adf8e | 18 | #ifdef CONFIG_ARM64 |
e628f008 | 19 | #define CONFIG_SYS_BOOTM_LEN (32 << 20) |
d29adf8e AP |
20 | #endif |
21 | ||
cba69eee | 22 | /* Serial & console */ |
cba69eee IC |
23 | #define CONFIG_SYS_NS16550_SERIAL |
24 | /* ns16550 reg in the low bits of cpu reg */ | |
cba69eee | 25 | #define CONFIG_SYS_NS16550_CLK 24000000 |
4fb60552 | 26 | #ifndef CONFIG_DM_SERIAL |
1a81cf83 SG |
27 | # define CONFIG_SYS_NS16550_REG_SIZE -4 |
28 | # define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE | |
29 | # define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE | |
30 | # define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE | |
31 | # define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE | |
32 | # define CONFIG_SYS_NS16550_COM5 SUNXI_R_UART_BASE | |
33 | #endif | |
cba69eee | 34 | |
8a65f69c | 35 | /* CPU */ |
e4916e85 | 36 | #define COUNTER_FREQUENCY 24000000 |
8a65f69c | 37 | |
e049fe28 HG |
38 | /* |
39 | * The DRAM Base differs between some models. We cannot use macros for the | |
40 | * CONFIG_FOO defines which contain the DRAM base address since they end | |
41 | * up unexpanded in include/autoconf.mk . | |
42 | * | |
43 | * So we have to have this #ifdef #else #endif block for these. | |
44 | */ | |
45 | #ifdef CONFIG_MACH_SUN9I | |
46 | #define SDRAM_OFFSET(x) 0x2##x | |
47 | #define CONFIG_SYS_SDRAM_BASE 0x20000000 | |
17d6ecea | 48 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
ff42d107 HG |
49 | * since it needs to fit in with the other values. By also #defining it |
50 | * we get warnings if the Kconfig value mismatches. */ | |
e049fe28 HG |
51 | #define CONFIG_SPL_BSS_START_ADDR 0x2ff80000 |
52 | #else | |
53 | #define SDRAM_OFFSET(x) 0x4##x | |
cba69eee | 54 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
c199489f | 55 | /* V3s do not have enough memory to place code at 0x4a000000 */ |
17d6ecea | 56 | /* Note SPL_STACK_R_ADDR is set through Kconfig, we include it here |
ff42d107 HG |
57 | * since it needs to fit in with the other values. By also #defining it |
58 | * we get warnings if the Kconfig value mismatches. */ | |
e049fe28 HG |
59 | #define CONFIG_SPL_BSS_START_ADDR 0x4ff80000 |
60 | #endif | |
61 | ||
62 | #define CONFIG_SPL_BSS_MAX_SIZE 0x00080000 /* 512 KiB */ | |
e049fe28 | 63 | |
77fe9887 HG |
64 | /* |
65 | * The A80's A1 sram starts at 0x00010000 rather then at 0x00000000 and is | |
66 | * slightly bigger. Note that it is possible to map the first 32 KiB of the | |
67 | * A1 at 0x00000000 like with older SoCs by writing 0x16aa0001 to the | |
68 | * undocumented 0x008000e0 SYS_CTRL register. Where the 16aa is a key and | |
69 | * the 1 actually activates the mapping of the first 32 KiB to 0x00000000. | |
cadc7c20 IZ |
70 | * A64 and H5 also has SRAM A1 at 0x00010000, but no magic remap register |
71 | * is known yet. | |
72 | * H6 has SRAM A1 at 0x00020000. | |
77fe9887 | 73 | */ |
cadc7c20 IZ |
74 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SUNXI_SRAM_ADDRESS |
75 | /* FIXME: this may be larger on some SoCs */ | |
76 | #define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */ | |
cba69eee IC |
77 | |
78 | #define CONFIG_SYS_INIT_SP_OFFSET \ | |
79 | (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) | |
80 | #define CONFIG_SYS_INIT_SP_ADDR \ | |
81 | (CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET) | |
82 | ||
cba69eee IC |
83 | #define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE |
84 | #define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */ | |
85 | ||
a6e50a88 | 86 | #ifdef CONFIG_AHCI |
0751b138 | 87 | #define CONFIG_SYS_64BIT_LBA |
a6e50a88 IC |
88 | #endif |
89 | ||
e5268616 | 90 | #ifdef CONFIG_NAND_SUNXI |
a0dfa88b | 91 | #define CONFIG_SYS_NAND_MAX_ECCPOS 1664 |
4ccae81c | 92 | #define CONFIG_SYS_MAX_NAND_DEVICE 8 |
960caeba PZ |
93 | #endif |
94 | ||
e24ea55c | 95 | /* mmc config */ |
e24ea55c | 96 | #define CONFIG_MMC_SUNXI_SLOT 0 |
fb1c43cc MR |
97 | |
98 | #if defined(CONFIG_ENV_IS_IN_MMC) | |
99219664 MR |
99 | /* |
100 | * This is actually (CONFIG_ENV_OFFSET - | |
101 | * (CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR * 512)), but the value will be used | |
102 | * directly in a makefile, without the preprocessor expansion. | |
103 | */ | |
104 | #define CONFIG_BOARD_SIZE_LIMIT 0x7e000 | |
105 | #endif | |
106 | ||
ae042beb | 107 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 |
e24ea55c | 108 | |
cba69eee IC |
109 | /* |
110 | * Miscellaneous configurable options | |
111 | */ | |
06beadb0 IC |
112 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
113 | #define CONFIG_SYS_PBSIZE 1024 /* Print Buffer Size */ | |
cba69eee | 114 | |
cba69eee | 115 | /* standalone support */ |
e049fe28 | 116 | #define CONFIG_STANDALONE_LOAD_ADDR CONFIG_SYS_LOAD_ADDR |
cba69eee | 117 | |
cba69eee IC |
118 | /* FLASH and environment organization */ |
119 | ||
fa5e1020 | 120 | #define CONFIG_SYS_MONITOR_LEN (768 << 10) /* 768 KiB */ |
cba69eee | 121 | |
cadc7c20 IZ |
122 | /* |
123 | * We cannot use expressions here, because expressions won't be evaluated in | |
124 | * autoconf.mk. | |
125 | */ | |
126 | #if CONFIG_SUNXI_SRAM_ADDRESS == 0x10000 | |
7f0ef5a9 | 127 | #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ |
54522c92 AP |
128 | #ifdef CONFIG_ARM64 |
129 | /* end of SRAM A2 for now, as SRAM A1 is pretty tight for an ARM64 build */ | |
130 | #define LOW_LEVEL_SRAM_STACK 0x00054000 | |
131 | #else | |
bc613d85 | 132 | #define LOW_LEVEL_SRAM_STACK 0x00018000 |
54522c92 | 133 | #endif /* !CONFIG_ARM64 */ |
e5715e71 | 134 | #elif CONFIG_SUNXI_SRAM_ADDRESS == 0x20000 |
8ec293e0 JS |
135 | #ifdef CONFIG_MACH_SUN50I_H616 |
136 | #define CONFIG_SPL_MAX_SIZE 0xbfa0 /* 48 KiB */ | |
137 | #define LOW_LEVEL_SRAM_STACK 0x58000 | |
138 | #else | |
e5715e71 IZ |
139 | #define CONFIG_SPL_MAX_SIZE 0x7fa0 /* 32 KiB */ |
140 | /* end of SRAM A2 on H6 for now */ | |
141 | #define LOW_LEVEL_SRAM_STACK 0x00118000 | |
8ec293e0 | 142 | #endif |
d96ebc46 | 143 | #else |
7f0ef5a9 | 144 | #define CONFIG_SPL_MAX_SIZE 0x5fa0 /* 24KB on sun4i/sun7i */ |
bc613d85 | 145 | #define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */ |
d96ebc46 | 146 | #endif |
50827a59 | 147 | |
bc613d85 AP |
148 | #define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK |
149 | ||
8ec293e0 | 150 | #ifndef CONFIG_MACH_SUN50I_H616 |
50827a59 | 151 | #define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */ |
8ec293e0 | 152 | #endif |
50827a59 | 153 | |
c26fb9db | 154 | /* Ethernet support */ |
c26fb9db | 155 | |
2582ca0d | 156 | #ifdef CONFIG_USB_EHCI_HCD |
6a72e804 | 157 | #define CONFIG_USB_OHCI_NEW |
6a72e804 | 158 | #define CONFIG_SYS_USB_OHCI_MAX_ROOT_PORTS 1 |
1a800f7a HG |
159 | #endif |
160 | ||
cba69eee | 161 | #ifndef CONFIG_SPL_BUILD |
2ec3a612 | 162 | |
671f9ad8 AP |
163 | #ifdef CONFIG_ARM64 |
164 | /* | |
165 | * Boards seem to come with at least 512MB of DRAM. | |
166 | * The kernel should go at 512K, which is the default text offset (that will | |
167 | * be adjusted at runtime if needed). | |
168 | * There is no compression for arm64 kernels (yet), so leave some space | |
169 | * for really big kernels, say 256MB for now. | |
170 | * Scripts, PXE and DTBs should go afterwards, leaving the rest for the initrd. | |
671f9ad8 | 171 | */ |
17d6ecea JS |
172 | #define BOOTM_SIZE __stringify(0xa000000) |
173 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(0080000)) | |
747c2421 AF |
174 | #define KERNEL_COMP_ADDR_R __stringify(SDRAM_OFFSET(4000000)) |
175 | #define KERNEL_COMP_SIZE __stringify(0xb000000) | |
17d6ecea JS |
176 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(FA00000)) |
177 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(FC00000)) | |
178 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(FD00000)) | |
179 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(FE00000)) | |
180 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(FF00000)) | |
671f9ad8 AP |
181 | |
182 | #else | |
8c95c556 | 183 | /* |
5c965ed9 | 184 | * 160M RAM (256M minimum minus 64MB heap + 32MB for u-boot, stack, fb, etc. |
8c95c556 | 185 | * 32M uncompressed kernel, 16M compressed kernel, 1M fdt, |
17d6ecea | 186 | * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. |
8c95c556 | 187 | */ |
c199489f | 188 | #ifndef CONFIG_MACH_SUN8I_V3S |
17d6ecea JS |
189 | #define BOOTM_SIZE __stringify(0xa000000) |
190 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(2000000)) | |
191 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(3000000)) | |
192 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(3100000)) | |
193 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(3200000)) | |
194 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(3300000)) | |
195 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(3400000)) | |
c199489f IZ |
196 | #else |
197 | /* | |
198 | * 64M RAM minus 2MB heap + 16MB for u-boot, stack, fb, etc. | |
199 | * 16M uncompressed kernel, 8M compressed kernel, 1M fdt, | |
17d6ecea | 200 | * 1M script, 1M pxe, 1M dt overlay and the ramdisk at the end. |
c199489f | 201 | */ |
17d6ecea JS |
202 | #define BOOTM_SIZE __stringify(0x2e00000) |
203 | #define KERNEL_ADDR_R __stringify(SDRAM_OFFSET(1000000)) | |
204 | #define FDT_ADDR_R __stringify(SDRAM_OFFSET(1800000)) | |
205 | #define SCRIPT_ADDR_R __stringify(SDRAM_OFFSET(1900000)) | |
206 | #define PXEFILE_ADDR_R __stringify(SDRAM_OFFSET(1A00000)) | |
207 | #define FDTOVERLAY_ADDR_R __stringify(SDRAM_OFFSET(1B00000)) | |
208 | #define RAMDISK_ADDR_R __stringify(SDRAM_OFFSET(1C00000)) | |
c199489f | 209 | #endif |
671f9ad8 | 210 | #endif |
2a909c5f | 211 | |
846e3254 | 212 | #define MEM_LAYOUT_ENV_SETTINGS \ |
c199489f | 213 | "bootm_size=" BOOTM_SIZE "\0" \ |
2a909c5f SS |
214 | "kernel_addr_r=" KERNEL_ADDR_R "\0" \ |
215 | "fdt_addr_r=" FDT_ADDR_R "\0" \ | |
216 | "scriptaddr=" SCRIPT_ADDR_R "\0" \ | |
217 | "pxefile_addr_r=" PXEFILE_ADDR_R "\0" \ | |
17d6ecea | 218 | "fdtoverlay_addr_r=" FDTOVERLAY_ADDR_R "\0" \ |
2a909c5f SS |
219 | "ramdisk_addr_r=" RAMDISK_ADDR_R "\0" |
220 | ||
747c2421 AF |
221 | #ifdef CONFIG_ARM64 |
222 | ||
223 | #define MEM_LAYOUT_ENV_EXTRA_SETTINGS \ | |
224 | "kernel_comp_addr_r=" KERNEL_COMP_ADDR_R "\0" \ | |
225 | "kernel_comp_size=" KERNEL_COMP_SIZE "\0" | |
226 | ||
227 | #else | |
228 | ||
229 | #define MEM_LAYOUT_ENV_EXTRA_SETTINGS "" | |
230 | ||
231 | #endif | |
232 | ||
2a909c5f SS |
233 | #define DFU_ALT_INFO_RAM \ |
234 | "dfu_alt_info_ram=" \ | |
235 | "kernel ram " KERNEL_ADDR_R " 0x1000000;" \ | |
236 | "fdt ram " FDT_ADDR_R " 0x100000;" \ | |
237 | "ramdisk ram " RAMDISK_ADDR_R " 0x4000000\0" | |
846e3254 | 238 | |
41f8e9f5 | 239 | #ifdef CONFIG_MMC |
5a37a400 | 240 | #if CONFIG_MMC_SUNXI_SLOT_EXTRA != -1 |
de86fc38 MR |
241 | #define BOOTENV_DEV_MMC_AUTO(devtypeu, devtypel, instance) \ |
242 | BOOTENV_DEV_MMC(MMC, mmc, 0) \ | |
243 | BOOTENV_DEV_MMC(MMC, mmc, 1) \ | |
244 | "bootcmd_mmc_auto=" \ | |
245 | "if test ${mmc_bootdev} -eq 1; then " \ | |
246 | "run bootcmd_mmc1; " \ | |
247 | "run bootcmd_mmc0; " \ | |
248 | "elif test ${mmc_bootdev} -eq 0; then " \ | |
249 | "run bootcmd_mmc0; " \ | |
250 | "run bootcmd_mmc1; " \ | |
251 | "fi\0" | |
252 | ||
253 | #define BOOTENV_DEV_NAME_MMC_AUTO(devtypeu, devtypel, instance) \ | |
254 | "mmc_auto " | |
255 | ||
256 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC_AUTO, mmc_auto, na) | |
5a37a400 | 257 | #else |
de86fc38 | 258 | #define BOOT_TARGET_DEVICES_MMC(func) func(MMC, mmc, 0) |
5a37a400 | 259 | #endif |
41f8e9f5 CYT |
260 | #else |
261 | #define BOOT_TARGET_DEVICES_MMC(func) | |
262 | #endif | |
263 | ||
2ec3a612 HG |
264 | #ifdef CONFIG_AHCI |
265 | #define BOOT_TARGET_DEVICES_SCSI(func) func(SCSI, scsi, 0) | |
266 | #else | |
267 | #define BOOT_TARGET_DEVICES_SCSI(func) | |
268 | #endif | |
269 | ||
2582ca0d | 270 | #ifdef CONFIG_USB_STORAGE |
859b3f14 CYT |
271 | #define BOOT_TARGET_DEVICES_USB(func) func(USB, usb, 0) |
272 | #else | |
273 | #define BOOT_TARGET_DEVICES_USB(func) | |
274 | #endif | |
275 | ||
0eabec14 OJ |
276 | #ifdef CONFIG_CMD_PXE |
277 | #define BOOT_TARGET_DEVICES_PXE(func) func(PXE, pxe, na) | |
278 | #else | |
279 | #define BOOT_TARGET_DEVICES_PXE(func) | |
280 | #endif | |
281 | ||
282 | #ifdef CONFIG_CMD_DHCP | |
283 | #define BOOT_TARGET_DEVICES_DHCP(func) func(DHCP, dhcp, na) | |
284 | #else | |
285 | #define BOOT_TARGET_DEVICES_DHCP(func) | |
286 | #endif | |
287 | ||
f3b589c0 BN |
288 | /* FEL boot support, auto-execute boot.scr if a script address was provided */ |
289 | #define BOOTENV_DEV_FEL(devtypeu, devtypel, instance) \ | |
290 | "bootcmd_fel=" \ | |
291 | "if test -n ${fel_booted} && test -n ${fel_scriptaddr}; then " \ | |
292 | "echo '(FEL boot)'; " \ | |
293 | "source ${fel_scriptaddr}; " \ | |
294 | "fi\0" | |
295 | #define BOOTENV_DEV_NAME_FEL(devtypeu, devtypel, instance) \ | |
296 | "fel " | |
297 | ||
2ec3a612 | 298 | #define BOOT_TARGET_DEVICES(func) \ |
f3b589c0 | 299 | func(FEL, fel, na) \ |
41f8e9f5 | 300 | BOOT_TARGET_DEVICES_MMC(func) \ |
2ec3a612 | 301 | BOOT_TARGET_DEVICES_SCSI(func) \ |
859b3f14 | 302 | BOOT_TARGET_DEVICES_USB(func) \ |
0eabec14 OJ |
303 | BOOT_TARGET_DEVICES_PXE(func) \ |
304 | BOOT_TARGET_DEVICES_DHCP(func) | |
2ec3a612 | 305 | |
3b824025 HG |
306 | #ifdef CONFIG_OLD_SUNXI_KERNEL_COMPAT |
307 | #define BOOTCMD_SUNXI_COMPAT \ | |
308 | "bootcmd_sunxi_compat=" \ | |
309 | "setenv root /dev/mmcblk0p3 rootwait; " \ | |
310 | "if ext2load mmc 0 0x44000000 uEnv.txt; then " \ | |
311 | "echo Loaded environment from uEnv.txt; " \ | |
312 | "env import -t 0x44000000 ${filesize}; " \ | |
313 | "fi; " \ | |
314 | "setenv bootargs console=${console} root=${root} ${extraargs}; " \ | |
315 | "ext2load mmc 0 0x43000000 script.bin && " \ | |
316 | "ext2load mmc 0 0x48000000 uImage && " \ | |
317 | "bootm 0x48000000\0" | |
318 | #else | |
319 | #define BOOTCMD_SUNXI_COMPAT | |
320 | #endif | |
321 | ||
2ec3a612 HG |
322 | #include <config_distro_bootcmd.h> |
323 | ||
86b49093 HG |
324 | #ifdef CONFIG_USB_KEYBOARD |
325 | #define CONSOLE_STDIN_SETTINGS \ | |
86b49093 HG |
326 | "stdin=serial,usbkbd\0" |
327 | #else | |
7f2c521f LV |
328 | #define CONSOLE_STDIN_SETTINGS \ |
329 | "stdin=serial\0" | |
86b49093 | 330 | #endif |
7f2c521f | 331 | |
5d235324 | 332 | #ifdef CONFIG_DM_VIDEO |
56009451 JS |
333 | #define CONSOLE_STDOUT_SETTINGS \ |
334 | "stdout=serial,vidconsole\0" \ | |
335 | "stderr=serial,vidconsole\0" | |
7f2c521f LV |
336 | #else |
337 | #define CONSOLE_STDOUT_SETTINGS \ | |
338 | "stdout=serial\0" \ | |
339 | "stderr=serial\0" | |
340 | #endif | |
341 | ||
c8564b24 MR |
342 | #ifdef CONFIG_MTDIDS_DEFAULT |
343 | #define SUNXI_MTDIDS_DEFAULT \ | |
344 | "mtdids=" CONFIG_MTDIDS_DEFAULT "\0" | |
345 | #else | |
346 | #define SUNXI_MTDIDS_DEFAULT | |
347 | #endif | |
348 | ||
349 | #ifdef CONFIG_MTDPARTS_DEFAULT | |
350 | #define SUNXI_MTDPARTS_DEFAULT \ | |
351 | "mtdparts=" CONFIG_MTDPARTS_DEFAULT "\0" | |
352 | #else | |
353 | #define SUNXI_MTDPARTS_DEFAULT | |
354 | #endif | |
355 | ||
c53654fc MR |
356 | #define PARTS_DEFAULT \ |
357 | "name=loader1,start=8k,size=32k,uuid=${uuid_gpt_loader1};" \ | |
358 | "name=loader2,size=984k,uuid=${uuid_gpt_loader2};" \ | |
359 | "name=esp,size=128M,bootable,uuid=${uuid_gpt_esp};" \ | |
360 | "name=system,size=-,uuid=${uuid_gpt_system};" | |
361 | ||
362 | #define UUID_GPT_ESP "c12a7328-f81f-11d2-ba4b-00a0c93ec93b" | |
363 | ||
364 | #ifdef CONFIG_ARM64 | |
365 | #define UUID_GPT_SYSTEM "b921b045-1df0-41c3-af44-4c6f280d3fae" | |
366 | #else | |
367 | #define UUID_GPT_SYSTEM "69dad710-2ce4-4e3c-b16c-21a1d49abed3" | |
368 | #endif | |
369 | ||
7f2c521f LV |
370 | #define CONSOLE_ENV_SETTINGS \ |
371 | CONSOLE_STDIN_SETTINGS \ | |
372 | CONSOLE_STDOUT_SETTINGS | |
373 | ||
2eff3b71 AF |
374 | #ifdef CONFIG_ARM64 |
375 | #define FDTFILE "allwinner/" CONFIG_DEFAULT_DEVICE_TREE ".dtb" | |
376 | #else | |
377 | #define FDTFILE CONFIG_DEFAULT_DEVICE_TREE ".dtb" | |
378 | #endif | |
379 | ||
2ec3a612 | 380 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
7f2c521f | 381 | CONSOLE_ENV_SETTINGS \ |
846e3254 | 382 | MEM_LAYOUT_ENV_SETTINGS \ |
747c2421 | 383 | MEM_LAYOUT_ENV_EXTRA_SETTINGS \ |
2a909c5f | 384 | DFU_ALT_INFO_RAM \ |
2eff3b71 | 385 | "fdtfile=" FDTFILE "\0" \ |
846e3254 | 386 | "console=ttyS0,115200\0" \ |
c8564b24 MR |
387 | SUNXI_MTDIDS_DEFAULT \ |
388 | SUNXI_MTDPARTS_DEFAULT \ | |
c53654fc MR |
389 | "uuid_gpt_esp=" UUID_GPT_ESP "\0" \ |
390 | "uuid_gpt_system=" UUID_GPT_SYSTEM "\0" \ | |
391 | "partitions=" PARTS_DEFAULT "\0" \ | |
3b824025 | 392 | BOOTCMD_SUNXI_COMPAT \ |
2ec3a612 HG |
393 | BOOTENV |
394 | ||
395 | #else /* ifndef CONFIG_SPL_BUILD */ | |
396 | #define CONFIG_EXTRA_ENV_SETTINGS | |
cba69eee IC |
397 | #endif |
398 | ||
399 | #endif /* _SUNXI_COMMON_CONFIG_H */ |