[thirdparty/u-boot.git] / include / configs / sunxi-common.h

/*
 * (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
 *
 * (C) Copyright 2007-2011
 * Allwinner Technology Co., Ltd. <www.allwinnertech.com>
 * Tom Cubie <tangliang@allwinnertech.com>
 *
 * Configuration settings for the Allwinner sunxi series of boards.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _SUNXI_COMMON_CONFIG_H
#define _SUNXI_COMMON_CONFIG_H

/*
 * High Level Configuration Options
 */
#define CONFIG_SUNXI		/* sunxi family */
#ifdef CONFIG_SPL_BUILD
#ifndef CONFIG_SPL_FEL
#define CONFIG_SYS_THUMB_BUILD	/* Thumbs mode to save space in SPL */
#endif
#endif

#include <asm/arch/cpu.h>	/* get chip and board defs */

#define CONFIG_SYS_TEXT_BASE		0x4a000000

/*
 * Display CPU information
 */
#define CONFIG_DISPLAY_CPUINFO

/* Serial & console */
#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
/* ns16550 reg in the low bits of cpu reg */
#define CONFIG_SYS_NS16550_REG_SIZE	-4
#define CONFIG_SYS_NS16550_CLK		24000000
#define CONFIG_SYS_NS16550_COM1		SUNXI_UART0_BASE
#define CONFIG_SYS_NS16550_COM2		SUNXI_UART1_BASE
#define CONFIG_SYS_NS16550_COM3		SUNXI_UART2_BASE
#define CONFIG_SYS_NS16550_COM4		SUNXI_UART3_BASE

/* DRAM Base */
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_INIT_RAM_ADDR	0x0
#define CONFIG_SYS_INIT_RAM_SIZE	0x8000	/* 32 KiB */

#define CONFIG_SYS_INIT_SP_OFFSET \
	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_ADDR \
	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)

#define CONFIG_NR_DRAM_BANKS		1
#define PHYS_SDRAM_0			CONFIG_SYS_SDRAM_BASE
#define PHYS_SDRAM_0_SIZE		0x80000000 /* 2 GiB */

#ifdef CONFIG_AHCI
#define CONFIG_LIBATA
#define CONFIG_SCSI_AHCI
#define CONFIG_SCSI_AHCI_PLAT
#define CONFIG_SUNXI_AHCI
#define CONFIG_SYS_SCSI_MAX_SCSI_ID	1
#define CONFIG_SYS_SCSI_MAX_LUN		1
#define CONFIG_SYS_SCSI_MAX_DEVICE	(CONFIG_SYS_SCSI_MAX_SCSI_ID * \
					 CONFIG_SYS_SCSI_MAX_LUN)
#define CONFIG_CMD_SCSI
#endif

#define CONFIG_CMD_MEMORY
#define CONFIG_CMD_SETEXPR

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_INITRD_TAG

/* mmc config */
#define CONFIG_MMC
#define CONFIG_GENERIC_MMC
#define CONFIG_CMD_MMC
#define CONFIG_MMC_SUNXI
#define CONFIG_MMC_SUNXI_SLOT		0
#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0	/* first detected MMC controller */

/* 4MB of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (4 << 20))

/*
 * Miscellaneous configurable options
 */
#define CONFIG_CMD_ECHO
#define CONFIG_SYS_CBSIZE	256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE	384	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS	16	/* max number of command args */
#define CONFIG_SYS_GENERIC_BOARD

/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE

#define CONFIG_SYS_LOAD_ADDR		0x48000000 /* default load address */

/* standalone support */
#define CONFIG_STANDALONE_LOAD_ADDR	0x48000000

#define CONFIG_SYS_HZ			1000

/* baudrate */
#define CONFIG_BAUDRATE			115200

/* The stack sizes are set up in start.S using the settings below */
#define CONFIG_STACKSIZE		(256 << 10)	/* 256 KiB */

/* FLASH and environment organization */

#define CONFIG_SYS_NO_FLASH

#define CONFIG_SYS_MONITOR_LEN		(512 << 10)	/* 512 KiB */
#define CONFIG_IDENT_STRING		" Allwinner Technology"

#define CONFIG_ENV_OFFSET		(544 << 10) /* (8 + 24 + 512) KiB */
#define CONFIG_ENV_SIZE			(128 << 10)	/* 128 KiB */

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootm_size=0x10000000\0"

#include <config_cmd_default.h>
#undef CONFIG_CMD_FPGA

#define CONFIG_FAT_WRITE	/* enable write access */

#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT

#ifdef CONFIG_SPL_FEL

#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
#define CONFIG_SPL_TEXT_BASE		0x2000
#define CONFIG_SPL_MAX_SIZE		0x4000		/* 16 KiB */

#else /* CONFIG_SPL */

#define CONFIG_SPL_BSS_START_ADDR	0x4ff80000
#define CONFIG_SPL_BSS_MAX_SIZE		0x80000		/* 512 KiB */

#define CONFIG_SPL_TEXT_BASE		0x20		/* sram start+header */
#define CONFIG_SPL_MAX_SIZE		0x5fe0		/* 24KB on sun4i/sun7i */

#define CONFIG_SPL_LIBDISK_SUPPORT
#define CONFIG_SPL_MMC_SUPPORT

#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"

#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR	80	/* 40KiB */
#define CONFIG_SPL_PAD_TO		32768		/* decimal for 'dd' */

#endif /* CONFIG_SPL */

/* end of 32 KiB in sram */
#define LOW_LEVEL_SRAM_STACK		0x00008000 /* End of sram */
#define CONFIG_SPL_STACK		LOW_LEVEL_SRAM_STACK
#define CONFIG_SYS_SPL_MALLOC_START	0x4ff00000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00080000	/* 512 KiB */

/* I2C */
#define CONFIG_SPL_I2C_SUPPORT
#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_MVTWSI
#define CONFIG_SYS_I2C_SPEED		400000
#define CONFIG_SYS_I2C_SLAVE		0x7f
#define CONFIG_CMD_I2C

/* PMU */
#if defined CONFIG_AXP152_POWER || defined CONFIG_AXP209_POWER || defined CONFIG_AXP221_POWER
#define CONFIG_SPL_POWER_SUPPORT
#endif

#ifndef CONFIG_CONS_INDEX
#define CONFIG_CONS_INDEX              1       /* UART0 */
#endif

/* GPIO */
#define CONFIG_SUNXI_GPIO
#define CONFIG_CMD_GPIO

/* Ethernet support */
#ifdef CONFIG_SUNXI_EMAC
#define CONFIG_MII			/* MII PHY management		*/
#endif

#ifdef CONFIG_SUNXI_GMAC
#define CONFIG_DESIGNWARE_ETH		/* GMAC can use designware driver */
#define CONFIG_DW_AUTONEG
#define CONFIG_PHY_GIGE			/* GMAC can use gigabit PHY	*/
#define CONFIG_PHY_ADDR		1
#define CONFIG_MII			/* MII PHY management		*/
#define CONFIG_PHYLIB
#endif

#ifdef CONFIG_USB_EHCI
#define CONFIG_CMD_USB
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
#define CONFIG_USB_STORAGE
#endif

#if !defined CONFIG_ENV_IS_IN_MMC && \
    !defined CONFIG_ENV_IS_IN_NAND && \
    !defined CONFIG_ENV_IS_IN_FAT && \
    !defined CONFIG_ENV_IS_IN_SPI_FLASH
#define CONFIG_ENV_IS_NOWHERE
#endif

#define CONFIG_MISC_INIT_R

#ifndef CONFIG_SPL_BUILD
#include <config_distro_defaults.h>
#endif

#endif /* _SUNXI_COMMON_CONFIG_H */
Commit	Line	Data
cba69eee IC	1	/*
	2	* (C) Copyright 2012-2012 Henrik Nordstrom <henrik@henriknordstrom.net>
	3	*
	4	* (C) Copyright 2007-2011
	5	* Allwinner Technology Co., Ltd. <www.allwinnertech.com>
	6	* Tom Cubie <tangliang@allwinnertech.com>
	7	*
	8	* Configuration settings for the Allwinner sunxi series of boards.
	9	*
	10	* SPDX-License-Identifier: GPL-2.0+
	11	*/
	12
	13	#ifndef _SUNXI_COMMON_CONFIG_H
	14	#define _SUNXI_COMMON_CONFIG_H
	15
	16	/*
	17	* High Level Configuration Options
	18	*/
	19	#define CONFIG_SUNXI /* sunxi family */
50827a59 IC	20	#ifdef CONFIG_SPL_BUILD
	21	#ifndef CONFIG_SPL_FEL
	22	#define CONFIG_SYS_THUMB_BUILD /* Thumbs mode to save space in SPL */
	23	#endif
	24	#endif
cba69eee IC	25
	26	#include <asm/arch/cpu.h> /* get chip and board defs */
	27
	28	#define CONFIG_SYS_TEXT_BASE 0x4a000000
	29
	30	/*
	31	* Display CPU information
	32	*/
	33	#define CONFIG_DISPLAY_CPUINFO
	34
	35	/* Serial & console */
	36	#define CONFIG_SYS_NS16550
	37	#define CONFIG_SYS_NS16550_SERIAL
	38	/* ns16550 reg in the low bits of cpu reg */
	39	#define CONFIG_SYS_NS16550_REG_SIZE -4
	40	#define CONFIG_SYS_NS16550_CLK 24000000
	41	#define CONFIG_SYS_NS16550_COM1 SUNXI_UART0_BASE
	42	#define CONFIG_SYS_NS16550_COM2 SUNXI_UART1_BASE
	43	#define CONFIG_SYS_NS16550_COM3 SUNXI_UART2_BASE
	44	#define CONFIG_SYS_NS16550_COM4 SUNXI_UART3_BASE
	45
	46	/* DRAM Base */
	47	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	48	#define CONFIG_SYS_INIT_RAM_ADDR 0x0
	49	#define CONFIG_SYS_INIT_RAM_SIZE 0x8000 /* 32 KiB */
	50
	51	#define CONFIG_SYS_INIT_SP_OFFSET \
	52	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
	53	#define CONFIG_SYS_INIT_SP_ADDR \
	54	(CONFIG_SYS_INIT_RAM_ADDR + CONFIG_SYS_INIT_SP_OFFSET)
	55
	56	#define CONFIG_NR_DRAM_BANKS 1
	57	#define PHYS_SDRAM_0 CONFIG_SYS_SDRAM_BASE
	58	#define PHYS_SDRAM_0_SIZE 0x80000000 /* 2 GiB */
	59
a6e50a88 IC	60	#ifdef CONFIG_AHCI
	61	#define CONFIG_LIBATA
	62	#define CONFIG_SCSI_AHCI
	63	#define CONFIG_SCSI_AHCI_PLAT
	64	#define CONFIG_SUNXI_AHCI
	65	#define CONFIG_SYS_SCSI_MAX_SCSI_ID 1
	66	#define CONFIG_SYS_SCSI_MAX_LUN 1
	67	#define CONFIG_SYS_SCSI_MAX_DEVICE (CONFIG_SYS_SCSI_MAX_SCSI_ID * \
	68	CONFIG_SYS_SCSI_MAX_LUN)
	69	#define CONFIG_CMD_SCSI
	70	#endif
	71
cba69eee IC	72	#define CONFIG_CMD_MEMORY
	73	#define CONFIG_CMD_SETEXPR
	74
	75	#define CONFIG_SETUP_MEMORY_TAGS
	76	#define CONFIG_CMDLINE_TAG
	77	#define CONFIG_INITRD_TAG
	78
e24ea55c IC	79	/* mmc config */
	80	#define CONFIG_MMC
	81	#define CONFIG_GENERIC_MMC
	82	#define CONFIG_CMD_MMC
	83	#define CONFIG_MMC_SUNXI
	84	#define CONFIG_MMC_SUNXI_SLOT 0
e24ea55c IC	85	#define CONFIG_ENV_IS_IN_MMC
	86	#define CONFIG_SYS_MMC_ENV_DEV 0 /* first detected MMC controller */
	87
cba69eee IC	88	/* 4MB of malloc() pool */
	89	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (4 << 20))
	90
	91	/*
	92	* Miscellaneous configurable options
	93	*/
	94	#define CONFIG_CMD_ECHO
	95	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	96	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	97	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	98	#define CONFIG_SYS_GENERIC_BOARD
	99
	100	/* Boot Argument Buffer Size */
	101	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	102
	103	#define CONFIG_SYS_LOAD_ADDR 0x48000000 /* default load address */
	104
	105	/* standalone support */
	106	#define CONFIG_STANDALONE_LOAD_ADDR 0x48000000
	107
	108	#define CONFIG_SYS_HZ 1000
	109
	110	/* baudrate */
	111	#define CONFIG_BAUDRATE 115200
	112
	113	/* The stack sizes are set up in start.S using the settings below */
	114	#define CONFIG_STACKSIZE (256 << 10) /* 256 KiB */
	115
	116	/* FLASH and environment organization */
	117
	118	#define CONFIG_SYS_NO_FLASH
	119
	120	#define CONFIG_SYS_MONITOR_LEN (512 << 10) /* 512 KiB */
	121	#define CONFIG_IDENT_STRING " Allwinner Technology"
	122
e24ea55c	123	#define CONFIG_ENV_OFFSET (544 << 10) /* (8 + 24 + 512) KiB */
cba69eee IC	124	#define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB */
	125
	126	#define CONFIG_EXTRA_ENV_SETTINGS \
	127	"bootm_size=0x10000000\0"
	128
cba69eee	129	#include <config_cmd_default.h>
b9fb3b94	130	#undef CONFIG_CMD_FPGA
cba69eee IC	131
	132	#define CONFIG_FAT_WRITE /* enable write access */
	133
	134	#define CONFIG_SPL_FRAMEWORK
	135	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	136	#define CONFIG_SPL_SERIAL_SUPPORT
	137	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	138
50827a59 IC	139	#ifdef CONFIG_SPL_FEL
50827a59 IC	140
cba69eee IC	141	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl-fel.lds"
	142	#define CONFIG_SPL_START_S_PATH "arch/arm/cpu/armv7/sunxi"
	143	#define CONFIG_SPL_TEXT_BASE 0x2000
	144	#define CONFIG_SPL_MAX_SIZE 0x4000 /* 16 KiB */
50827a59 IC	145
	146	#else /* CONFIG_SPL */
	147
	148	#define CONFIG_SPL_BSS_START_ADDR 0x4ff80000
	149	#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KiB */
	150
	151	#define CONFIG_SPL_TEXT_BASE 0x20 /* sram start+header */
	152	#define CONFIG_SPL_MAX_SIZE 0x5fe0 /* 24KB on sun4i/sun7i */
	153
	154	#define CONFIG_SPL_LIBDISK_SUPPORT
	155	#define CONFIG_SPL_MMC_SUPPORT
	156
	157	#define CONFIG_SPL_LDSCRIPT "arch/arm/cpu/armv7/sunxi/u-boot-spl.lds"
	158
	159	#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 80 /* 40KiB */
	160	#define CONFIG_SPL_PAD_TO 32768 /* decimal for 'dd' */
	161
	162	#endif /* CONFIG_SPL */
	163
cba69eee IC	164	/* end of 32 KiB in sram */
	165	#define LOW_LEVEL_SRAM_STACK 0x00008000 /* End of sram */
	166	#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK
	167	#define CONFIG_SYS_SPL_MALLOC_START 0x4ff00000
	168	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00080000 /* 512 KiB */
	169
6620377e HG	170	/* I2C */
	171	#define CONFIG_SPL_I2C_SUPPORT
	172	#define CONFIG_SYS_I2C
	173	#define CONFIG_SYS_I2C_MVTWSI
	174	#define CONFIG_SYS_I2C_SPEED 400000
	175	#define CONFIG_SYS_I2C_SLAVE 0x7f
	176	#define CONFIG_CMD_I2C
	177
14bc66bd HN	178	/* PMU */
	179	#if defined CONFIG_AXP152_POWER \|\| defined CONFIG_AXP209_POWER \|\| defined CONFIG_AXP221_POWER
	180	#define CONFIG_SPL_POWER_SUPPORT
	181	#endif
	182
f84269c5	183	#ifndef CONFIG_CONS_INDEX
cba69eee	184	#define CONFIG_CONS_INDEX 1 /* UART0 */
f84269c5	185	#endif
cba69eee	186
abce2c62 IC	187	/* GPIO */
	188	#define CONFIG_SUNXI_GPIO
	189	#define CONFIG_CMD_GPIO
	190
c26fb9db HG	191	/* Ethernet support */
	192	#ifdef CONFIG_SUNXI_EMAC
	193	#define CONFIG_MII /* MII PHY management */
	194	#endif
	195
5835823d IC	196	#ifdef CONFIG_SUNXI_GMAC
	197	#define CONFIG_DESIGNWARE_ETH /* GMAC can use designware driver */
	198	#define CONFIG_DW_AUTONEG
	199	#define CONFIG_PHY_GIGE /* GMAC can use gigabit PHY */
	200	#define CONFIG_PHY_ADDR 1
	201	#define CONFIG_MII /* MII PHY management */
	202	#define CONFIG_PHYLIB
	203	#endif
	204
3584f30c RB	205	#ifdef CONFIG_USB_EHCI
	206	#define CONFIG_CMD_USB
	207	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
	208	#define CONFIG_USB_STORAGE
	209	#endif
	210
cba69eee IC	211	#if !defined CONFIG_ENV_IS_IN_MMC && \
	212	!defined CONFIG_ENV_IS_IN_NAND && \
	213	!defined CONFIG_ENV_IS_IN_FAT && \
	214	!defined CONFIG_ENV_IS_IN_SPI_FLASH
	215	#define CONFIG_ENV_IS_NOWHERE
	216	#endif
	217
b41d7d05 JL	218	#define CONFIG_MISC_INIT_R
b41d7d05 JL	219
cba69eee IC	220	#ifndef CONFIG_SPL_BUILD
	221	#include <config_distro_defaults.h>
	222	#endif
	223
	224	#endif /* _SUNXI_COMMON_CONFIG_H */