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62ddcf05 HS |
1 | /* |
2 | * Copyright (C) 2006 Freescale Semiconductor, Inc. | |
3 | * Dave Liu <daveliu@freescale.com> | |
4 | * | |
5 | * Copyright (C) 2007 Logic Product Development, Inc. | |
6 | * Peter Barada <peterb@logicpd.com> | |
7 | * | |
8 | * Copyright (C) 2007 MontaVista Software, Inc. | |
9 | * Anton Vorontsov <avorontsov@ru.mvista.com> | |
10 | * | |
11 | * (C) Copyright 2010 | |
12 | * Heiko Schocher, DENX Software Engineering, hs@denx.de. | |
13 | * | |
1a459660 | 14 | * SPDX-License-Identifier: GPL-2.0+ |
62ddcf05 HS |
15 | */ |
16 | ||
17 | #ifndef __CONFIG_H | |
18 | #define __CONFIG_H | |
19 | ||
20 | /* | |
21 | * High Level Configuration Options | |
22 | */ | |
62ddcf05 | 23 | |
c4d22de8 | 24 | /* This needs to be set prior to including km/km83xx-common.h */ |
62ddcf05 | 25 | #define CONFIG_SYS_TEXT_BASE 0xF0000000 |
62ddcf05 | 26 | |
c4d22de8 GF |
27 | #if defined(CONFIG_SUVD3) /* SUVD3 board specific */ |
28 | #define CONFIG_HOSTNAME suvd3 | |
29 | #define CONFIG_KM_BOARD_NAME "suvd3" | |
8ed74341 | 30 | /* include common defines/options for all 8321 Keymile boards */ |
264eaa0e | 31 | #include "km/km8321-common.h" |
54119882 | 32 | |
c4d22de8 GF |
33 | #elif defined(CONFIG_KMVECT1) /* VECT1 board specific */ |
34 | #define CONFIG_HOSTNAME kmvect1 | |
35 | #define CONFIG_KM_BOARD_NAME "kmvect1" | |
54119882 VL |
36 | /* at end of uboot partition, before env */ |
37 | #define CONFIG_SYS_QE_FW_ADDR 0xF00B0000 | |
38 | /* include common defines/options for all 8309 Keymile boards */ | |
39 | #include "km/km8309-common.h" | |
40 | ||
41 | #elif defined(CONFIG_KMTEGR1) /* TEGR1 board specific */ | |
42 | #define CONFIG_HOSTNAME kmtegr1 | |
43 | #define CONFIG_KM_BOARD_NAME "kmtegr1" | |
44 | #define CONFIG_KM_UBI_PARTITION_NAME_BOOT "ubi0" | |
45 | #define CONFIG_KM_UBI_PARTITION_NAME_APP "ubi1" | |
54119882 VL |
46 | |
47 | #define CONFIG_ENV_ADDR 0xF0100000 | |
48 | #define CONFIG_ENV_OFFSET 0x100000 | |
49 | ||
54119882 | 50 | #define CONFIG_NAND_ECC_BCH |
54119882 VL |
51 | #define CONFIG_NAND_KMETER1 |
52 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
53 | #define NAND_MAX_CHIPS 1 | |
54 | ||
c4d22de8 GF |
55 | /* include common defines/options for all 8309 Keymile boards */ |
56 | #include "km/km8309-common.h" | |
54119882 VL |
57 | /* must be after the include because KMBEC_FPGA is otherwise undefined */ |
58 | #define CONFIG_SYS_NAND_BASE CONFIG_SYS_KMBEC_FPGA_BASE /* PRIO_BASE_ADDRESS */ | |
59 | ||
c4d22de8 | 60 | #else |
54119882 | 61 | #error Supported boards are: SUVD3, KMVECT1, KMTEGR1 |
c4d22de8 | 62 | #endif |
62ddcf05 | 63 | |
62ddcf05 | 64 | #define CONFIG_SYS_APP1_BASE 0xA0000000 |
91eb52ad | 65 | #define CONFIG_SYS_APP1_SIZE 256 /* Megabytes */ |
62ddcf05 | 66 | #define CONFIG_SYS_APP2_BASE 0xB0000000 |
91eb52ad | 67 | #define CONFIG_SYS_APP2_SIZE 256 /* Megabytes */ |
62ddcf05 HS |
68 | |
69 | /* EEprom support */ | |
70 | #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 | |
71 | ||
62ddcf05 HS |
72 | /* |
73 | * Init Local Bus Memory Controller: | |
74 | * | |
75 | * Bank Bus Machine PortSz Size Device | |
76 | * ---- --- ------- ------ ----- ------ | |
77 | * 2 Local UPMA 16 bit 256MB APP1 | |
78 | * 3 Local GPCM 16 bit 256MB APP2 | |
79 | * | |
80 | */ | |
81 | ||
54119882 | 82 | #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) |
62ddcf05 HS |
83 | /* |
84 | * APP1 on the local bus CS2 | |
85 | */ | |
86 | #define CONFIG_SYS_LBLAWBAR2_PRELIM CONFIG_SYS_APP1_BASE | |
87 | #define CONFIG_SYS_LBLAWAR2_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) | |
88 | ||
89 | #define CONFIG_SYS_BR2_PRELIM (CONFIG_SYS_APP1_BASE | \ | |
90 | BR_PS_16 | \ | |
91 | BR_MS_UPMA | \ | |
92 | BR_V) | |
93 | #define CONFIG_SYS_OR2_PRELIM (MEG_TO_AM(CONFIG_SYS_APP1_SIZE)) | |
94 | ||
95 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ | |
96 | BR_PS_16 | \ | |
97 | BR_V) | |
98 | ||
99 | #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ | |
100 | OR_GPCM_CSNT | \ | |
101 | OR_GPCM_ACS_DIV4 | \ | |
102 | OR_GPCM_SCY_3 | \ | |
7d6a0982 | 103 | OR_GPCM_TRLX_SET) |
62ddcf05 HS |
104 | |
105 | #define CONFIG_SYS_MAMR (MxMR_GPL_x4DIS | \ | |
106 | 0x0000c000 | \ | |
107 | MxMR_WLFx_2X) | |
108 | ||
54119882 VL |
109 | #elif defined(CONFIG_KMTEGR1) |
110 | #define CONFIG_SYS_BR3_PRELIM (CONFIG_SYS_APP2_BASE | \ | |
111 | BR_PS_16 | \ | |
112 | BR_MS_GPCM | \ | |
113 | BR_V) | |
114 | ||
115 | #define CONFIG_SYS_OR3_PRELIM (MEG_TO_AM(CONFIG_SYS_APP2_SIZE) | \ | |
116 | OR_GPCM_SCY_5 | \ | |
117 | OR_GPCM_TRLX_CLEAR | \ | |
118 | OR_GPCM_EHTR_CLEAR) | |
119 | ||
120 | #endif /* CONFIG_KMTEGR1 */ | |
121 | ||
62ddcf05 HS |
122 | #define CONFIG_SYS_LBLAWBAR3_PRELIM CONFIG_SYS_APP2_BASE |
123 | #define CONFIG_SYS_LBLAWAR3_PRELIM (LBLAWAR_EN | LBLAWAR_256MB) | |
124 | ||
125 | /* | |
126 | * MMU Setup | |
127 | */ | |
54119882 | 128 | #if defined(CONFIG_SUVD3) || defined(CONFIG_KMVECT1) |
62ddcf05 | 129 | /* APP1: icache cacheable, but dcache-inhibit and guarded */ |
72cd4087 | 130 | #define CONFIG_SYS_IBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ |
62ddcf05 HS |
131 | BATL_MEMCOHERENCE) |
132 | #define CONFIG_SYS_IBAT5U (CONFIG_SYS_APP1_BASE | BATU_BL_256M | \ | |
133 | BATU_VS | BATU_VP) | |
72cd4087 | 134 | #define CONFIG_SYS_DBAT5L (CONFIG_SYS_APP1_BASE | BATL_PP_RW | \ |
62ddcf05 HS |
135 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
136 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
137 | ||
54119882 VL |
138 | #elif defined(CONFIG_KMTEGR1) |
139 | #define CONFIG_SYS_IBAT5L (0) | |
140 | #define CONFIG_SYS_IBAT5U (0) | |
141 | #define CONFIG_SYS_DBAT5L CONFIG_SYS_IBAT5L | |
142 | #define CONFIG_SYS_DBAT5U CONFIG_SYS_IBAT5U | |
143 | #endif /* CONFIG_KMTEGR1 */ | |
144 | ||
72cd4087 | 145 | #define CONFIG_SYS_IBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ |
62ddcf05 HS |
146 | BATL_MEMCOHERENCE) |
147 | #define CONFIG_SYS_IBAT6U (CONFIG_SYS_APP2_BASE | BATU_BL_256M | \ | |
148 | BATU_VS | BATU_VP) | |
72cd4087 | 149 | #define CONFIG_SYS_DBAT6L (CONFIG_SYS_APP2_BASE | BATL_PP_RW | \ |
62ddcf05 HS |
150 | BATL_CACHEINHIBIT | BATL_GUARDEDSTORAGE) |
151 | #define CONFIG_SYS_DBAT6U CONFIG_SYS_IBAT6U | |
152 | ||
5bcd64cf KJ |
153 | /* |
154 | * QE UEC ethernet configuration | |
155 | */ | |
156 | #if defined(CONFIG_KMVECT1) | |
157 | #define CONFIG_MV88E6352_SWITCH | |
158 | #define CONFIG_KM_MVEXTSW_ADDR 0x10 | |
159 | ||
160 | /* ethernet port connected to simple switch 88e6122 (UEC0) */ | |
161 | #define CONFIG_UEC_ETH1 | |
162 | #define CONFIG_SYS_UEC1_UCC_NUM 0 /* UCC1 */ | |
163 | #define CONFIG_SYS_UEC1_RX_CLK QE_CLK9 | |
164 | #define CONFIG_SYS_UEC1_TX_CLK QE_CLK10 | |
165 | ||
166 | #define CONFIG_FIXED_PHY 0xFFFFFFFF | |
167 | #define CONFIG_SYS_FIXED_PHY_ADDR 0x1E /* unused address */ | |
168 | #define CONFIG_SYS_FIXED_PHY_PORT(devnum, speed, duplex) \ | |
169 | {devnum, speed, duplex} | |
170 | #define CONFIG_SYS_FIXED_PHY_PORTS \ | |
171 | CONFIG_SYS_FIXED_PHY_PORT("UEC0", SPEED_100, DUPLEX_FULL) | |
172 | ||
173 | #define CONFIG_SYS_UEC1_ETH_TYPE FAST_ETH | |
174 | #define CONFIG_SYS_UEC1_PHY_ADDR CONFIG_SYS_FIXED_PHY_ADDR | |
175 | #define CONFIG_SYS_UEC1_INTERFACE_TYPE PHY_INTERFACE_MODE_MII | |
176 | #define CONFIG_SYS_UEC1_INTERFACE_SPEED 100 | |
54119882 | 177 | #endif /* CONFIG_KMVECT1 */ |
5bcd64cf | 178 | |
54119882 | 179 | #if defined(CONFIG_KMVECT1) || defined(CONFIG_KMTEGR1) |
5bcd64cf KJ |
180 | /* ethernet port connected to piggy (UEC2) */ |
181 | #define CONFIG_HAS_ETH1 | |
182 | #define CONFIG_UEC_ETH2 | |
183 | #define CONFIG_SYS_UEC2_UCC_NUM 2 /* UCC3 */ | |
184 | #define CONFIG_SYS_UEC2_RX_CLK QE_CLK_NONE /* not used in RMII Mode */ | |
185 | #define CONFIG_SYS_UEC2_TX_CLK QE_CLK12 | |
186 | #define CONFIG_SYS_UEC2_ETH_TYPE FAST_ETH | |
187 | #define CONFIG_SYS_UEC2_PHY_ADDR 0 | |
188 | #define CONFIG_SYS_UEC2_INTERFACE_TYPE PHY_INTERFACE_MODE_RMII | |
189 | #define CONFIG_SYS_UEC2_INTERFACE_SPEED 100 | |
54119882 | 190 | #endif /* CONFIG_KMVECT1 || CONFIG_KMTEGR1 */ |
5bcd64cf | 191 | |
62ddcf05 | 192 | #endif /* __CONFIG_H */ |