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dc7c9a1a WD |
1 | /* |
2 | * (C) Copyright 2000, 2001, 2002 | |
3 | * Wolfgang Denk, DENX Software Engineering, wd@denx.de. | |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
24 | /* | |
25 | * board/config.h - configuration options, board specific, | |
26 | * for SinoVee Microsystems SC8xx series SBC | |
27 | * http://www.fel.com.cn (Chinese) | |
28 | * http://www.sinovee.com (English) | |
29 | */ | |
30 | ||
31 | #ifndef __CONFIG_H | |
32 | #define __CONFIG_H | |
33 | ||
2ae18241 WD |
34 | #define CONFIG_SYS_TEXT_BASE 0x40000000 |
35 | ||
dc7c9a1a WD |
36 | /* Custom configuration */ |
37 | /* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */ | |
38 | /* SC85T,SC860T, FEL8xx-AT(855T/860T) */ | |
39 | /*#define CONFIG_FEL8xx_AT */ | |
40 | /*#define CONFIG_LCD */ | |
41 | /* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */ | |
42 | /* #define CONFIG_50MHz */ | |
43 | /* #define CONFIG_66MHz */ | |
44 | /* #define CONFIG_75MHz */ | |
45 | #define CONFIG_80MHz | |
46 | /*#define CONFIG_100MHz */ | |
47 | /* #define CONFIG_BUS_DIV2 1 */ | |
48 | /* for BOOT device port size */ | |
49 | /* #define CONFIG_BOOT_8B */ | |
50 | #define CONFIG_BOOT_16B | |
51 | /* #define CONFIG_BOOT_32B */ | |
52 | /* #define CONFIG_CAN_DRIVER */ | |
53 | /* #define DEBUG */ | |
54 | #define CONFIG_FEC_ENET | |
55 | ||
56 | /* #define CONFIG_SDRAM_16M */ | |
57 | #define CONFIG_SDRAM_32M | |
58 | /* #define CONFIG_SDRAM_64M */ | |
6d0f6bcf | 59 | #define CONFIG_SYS_RESET_ADDRESS 0xffffffff |
dc7c9a1a WD |
60 | /* |
61 | * High Level Configuration Options | |
62 | * (easy to change) | |
63 | */ | |
64 | ||
65 | /* #define CONFIG_MPC823 1 */ | |
66 | /* #define CONFIG_MPC850 1 */ | |
67 | #define CONFIG_MPC855 1 | |
68 | /* #define CONFIG_MPC860 1 */ | |
69 | /* #define CONFIG_MPC860T 1 */ | |
70 | ||
71 | #undef CONFIG_WATCHDOG /* watchdog */ | |
72 | ||
53677ef1 | 73 | #define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */ |
dc7c9a1a WD |
74 | |
75 | #ifdef CONFIG_LCD /* with LCD controller ? */ | |
fd3103bb | 76 | /* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */ |
dc7c9a1a WD |
77 | #endif |
78 | ||
79 | #define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ | |
80 | #undef CONFIG_8xx_CONS_SMC2 | |
81 | #undef CONFIG_8xx_CONS_NONE | |
82 | #define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */ | |
83 | #if 0 | |
84 | #define CONFIG_BOOTDELAY -1 /* autoboot disabled */ | |
85 | #else | |
86 | #define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */ | |
87 | #endif | |
88 | ||
89 | #define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */ | |
90 | ||
91 | #define CONFIG_BOARD_TYPES 1 /* support board types */ | |
92 | ||
93 | #define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo" | |
94 | ||
95 | #undef CONFIG_BOOTARGS | |
96 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
8bde7f77 | 97 | "nfsargs=setenv bootargs root=/dev/nfs rw " \ |
fe126d8b | 98 | "nfsroot=${serverip}:${rootpath}\0" \ |
8bde7f77 | 99 | "ramargs=setenv bootargs root=/dev/ram rw\0" \ |
fe126d8b WD |
100 | "addip=setenv bootargs ${bootargs} " \ |
101 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ | |
102 | ":${hostname}:${netdev}:off panic=1\0" \ | |
8bde7f77 | 103 | "flash_nfs=run nfsargs addip;" \ |
fe126d8b | 104 | "bootm ${kernel_addr}\0" \ |
8bde7f77 | 105 | "flash_self=run ramargs addip;" \ |
fe126d8b WD |
106 | "bootm ${kernel_addr} ${ramdisk_addr}\0" \ |
107 | "net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \ | |
8bde7f77 WD |
108 | "rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \ |
109 | "bootfile=pImage-sc855t\0" \ | |
110 | "kernel_addr=48000000\0" \ | |
111 | "ramdisk_addr=48100000\0" \ | |
112 | "" | |
dc7c9a1a | 113 | #define CONFIG_BOOTCOMMAND \ |
53677ef1 WD |
114 | "setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \ |
115 | "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \ | |
dc7c9a1a WD |
116 | "tftpboot 0x210000 pImage-sc855t;bootm 0x210000" |
117 | ||
118 | #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ | |
6d0f6bcf | 119 | #undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */ |
dc7c9a1a WD |
120 | |
121 | ||
122 | #ifdef CONFIG_LCD | |
123 | # undef CONFIG_STATUS_LED /* disturbs display */ | |
124 | #else | |
125 | # define CONFIG_STATUS_LED 1 /* Status LED enabled */ | |
126 | #endif /* CONFIG_LCD */ | |
127 | ||
128 | #undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ | |
129 | ||
d3b8c1a7 JL |
130 | /* |
131 | * BOOTP options | |
132 | */ | |
133 | #define CONFIG_BOOTP_SUBNETMASK | |
134 | #define CONFIG_BOOTP_GATEWAY | |
135 | #define CONFIG_BOOTP_HOSTNAME | |
136 | #define CONFIG_BOOTP_BOOTPATH | |
137 | #define CONFIG_BOOTP_BOOTFILESIZE | |
dc7c9a1a WD |
138 | |
139 | #define CONFIG_MAC_PARTITION | |
140 | #define CONFIG_DOS_PARTITION | |
141 | ||
142 | #define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */ | |
143 | ||
46da1e96 JL |
144 | |
145 | /* | |
146 | * Command line configuration. | |
147 | */ | |
148 | #include <config_cmd_default.h> | |
149 | ||
150 | #define CONFIG_CMD_ASKENV | |
151 | #define CONFIG_CMD_DHCP | |
46da1e96 JL |
152 | #define CONFIG_CMD_DATE |
153 | ||
dc7c9a1a WD |
154 | /* |
155 | * Miscellaneous configurable options | |
156 | */ | |
6d0f6bcf JCPV |
157 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
158 | #define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */ | |
dc7c9a1a | 159 | |
6d0f6bcf JCPV |
160 | #ifdef CONFIG_SYS_HUSH_PARSER |
161 | #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " | |
dc7c9a1a WD |
162 | #endif |
163 | ||
46da1e96 | 164 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 165 | #define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */ |
dc7c9a1a | 166 | #else |
6d0f6bcf | 167 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ |
dc7c9a1a | 168 | #endif |
6d0f6bcf JCPV |
169 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ |
170 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args */ | |
171 | #define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ | |
dc7c9a1a | 172 | |
6d0f6bcf JCPV |
173 | #define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */ |
174 | #define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */ | |
dc7c9a1a | 175 | |
6d0f6bcf | 176 | #define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */ |
dc7c9a1a | 177 | |
6d0f6bcf | 178 | #define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */ |
dc7c9a1a | 179 | |
6d0f6bcf | 180 | #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } |
dc7c9a1a WD |
181 | |
182 | /* | |
183 | * Low Level Configuration Settings | |
184 | * (address mappings, register initial values, etc.) | |
185 | * You should know what you are doing if you make changes here. | |
186 | */ | |
187 | /*----------------------------------------------------------------------- | |
188 | * Internal Memory Mapped Register | |
189 | */ | |
6d0f6bcf | 190 | #define CONFIG_SYS_IMMR 0xFF000000 |
dc7c9a1a WD |
191 | |
192 | /*----------------------------------------------------------------------- | |
193 | * Definitions for initial stack pointer and data area (in DPRAM) | |
194 | */ | |
6d0f6bcf | 195 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR |
553f0982 | 196 | #define CONFIG_SYS_INIT_RAM_SIZE 0x2F00 /* Size of used area in DPRAM */ |
25ddd1fb | 197 | #define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE) |
6d0f6bcf | 198 | #define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET |
dc7c9a1a WD |
199 | |
200 | /*----------------------------------------------------------------------- | |
201 | * Start addresses for the final memory configuration | |
202 | * (Set up by the startup code) | |
6d0f6bcf | 203 | * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0 |
dc7c9a1a | 204 | */ |
6d0f6bcf JCPV |
205 | #define CONFIG_SYS_SDRAM_BASE 0x00000000 |
206 | #define CONFIG_SYS_FLASH_BASE 0x40000000 | |
207 | #define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */ | |
208 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
209 | #define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */ | |
dc7c9a1a WD |
210 | |
211 | /* | |
212 | * For booting Linux, the board info and command line data | |
213 | * have to be in the first 8 MB of memory, since this is | |
214 | * the maximum mapped by the Linux kernel during initialization. | |
215 | */ | |
6d0f6bcf | 216 | #define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ |
dc7c9a1a WD |
217 | |
218 | /*----------------------------------------------------------------------- | |
219 | * FLASH organization | |
220 | */ | |
6d0f6bcf JCPV |
221 | #define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */ |
222 | #define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */ | |
dc7c9a1a | 223 | |
6d0f6bcf JCPV |
224 | #define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ |
225 | #define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ | |
dc7c9a1a | 226 | |
5a1aceb0 | 227 | #define CONFIG_ENV_IS_IN_FLASH 1 |
dc7c9a1a WD |
228 | |
229 | #ifdef CONFIG_BOOT_8B | |
0e8d1586 JCPV |
230 | #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
231 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
dc7c9a1a | 232 | #elif defined (CONFIG_BOOT_16B) |
0e8d1586 JCPV |
233 | #define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */ |
234 | #define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ | |
dc7c9a1a | 235 | #elif defined (CONFIG_BOOT_32B) |
0e8d1586 JCPV |
236 | #define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */ |
237 | #define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */ | |
dc7c9a1a WD |
238 | #endif |
239 | ||
240 | /* Address and size of Redundant Environment Sector */ | |
0e8d1586 JCPV |
241 | #define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE) |
242 | #define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE) | |
dc7c9a1a WD |
243 | |
244 | ||
245 | /*----------------------------------------------------------------------- | |
246 | * Hardware Information Block | |
247 | */ | |
6d0f6bcf JCPV |
248 | #define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ |
249 | #define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */ | |
250 | #define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */ | |
dc7c9a1a WD |
251 | |
252 | /*----------------------------------------------------------------------- | |
253 | * Cache Configuration | |
254 | */ | |
6d0f6bcf | 255 | #define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ |
46da1e96 | 256 | #if defined(CONFIG_CMD_KGDB) |
6d0f6bcf | 257 | #define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */ |
dc7c9a1a WD |
258 | #endif |
259 | ||
260 | /*----------------------------------------------------------------------- | |
261 | * SYPCR - System Protection Control 11-9 | |
262 | * SYPCR can only be written once after reset! | |
263 | *----------------------------------------------------------------------- | |
264 | * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze | |
265 | */ | |
266 | #if defined(CONFIG_WATCHDOG) | |
6d0f6bcf | 267 | /*#define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ |
dc7c9a1a WD |
268 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
269 | */ | |
6d0f6bcf | 270 | #define CONFIG_SYS_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \ |
dc7c9a1a WD |
271 | SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) |
272 | #else | |
6d0f6bcf | 273 | #define CONFIG_SYS_SYPCR 0xffffff88 |
dc7c9a1a WD |
274 | #endif |
275 | ||
276 | /*----------------------------------------------------------------------- | |
277 | * SIUMCR - SIU Module Configuration 11-6 | |
278 | *----------------------------------------------------------------------- | |
279 | * PCMCIA config., multi-function pin tri-state | |
280 | */ | |
281 | #ifndef CONFIG_CAN_DRIVER | |
6d0f6bcf JCPV |
282 | /*#define CONFIG_SYS_SIUMCR 0x00610c00 */ |
283 | #define CONFIG_SYS_SIUMCR 0x00000000 | |
dc7c9a1a | 284 | #else /* we must activate GPL5 in the SIUMCR for CAN */ |
6d0f6bcf | 285 | #define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) |
dc7c9a1a WD |
286 | #endif /* CONFIG_CAN_DRIVER */ |
287 | ||
288 | /*----------------------------------------------------------------------- | |
289 | * TBSCR - Time Base Status and Control 11-26 | |
290 | *----------------------------------------------------------------------- | |
291 | * Clear Reference Interrupt Status, Timebase freezing enabled | |
292 | */ | |
6d0f6bcf | 293 | #define CONFIG_SYS_TBSCR 0x0001 |
dc7c9a1a WD |
294 | |
295 | /*----------------------------------------------------------------------- | |
296 | * RTCSC - Real-Time Clock Status and Control Register 11-27 | |
297 | *----------------------------------------------------------------------- | |
298 | */ | |
6d0f6bcf | 299 | #define CONFIG_SYS_RTCSC 0x00c3 |
dc7c9a1a WD |
300 | |
301 | /*----------------------------------------------------------------------- | |
302 | * PISCR - Periodic Interrupt Status and Control 11-31 | |
303 | *----------------------------------------------------------------------- | |
304 | * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled | |
305 | */ | |
6d0f6bcf | 306 | #define CONFIG_SYS_PISCR 0x0000 |
dc7c9a1a WD |
307 | |
308 | /*----------------------------------------------------------------------- | |
309 | * PLPRCR - PLL, Low-Power, and Reset Control Register 15-30 | |
310 | *----------------------------------------------------------------------- | |
311 | * Reset PLL lock status sticky bit, timer expired status bit and timer | |
312 | * interrupt status bit | |
313 | */ | |
314 | #if defined (CONFIG_100MHz) | |
6d0f6bcf | 315 | #define CONFIG_SYS_PLPRCR 0x06301000 |
dc7c9a1a WD |
316 | #define CONFIG_8xx_GCLK_FREQ 100000000 |
317 | #elif defined (CONFIG_80MHz) | |
6d0f6bcf | 318 | #define CONFIG_SYS_PLPRCR 0x04f01000 |
dc7c9a1a | 319 | #define CONFIG_8xx_GCLK_FREQ 80000000 |
8bde7f77 | 320 | #elif defined(CONFIG_75MHz) |
6d0f6bcf | 321 | #define CONFIG_SYS_PLPRCR 0x04a00100 |
dc7c9a1a | 322 | #define CONFIG_8xx_GCLK_FREQ 75000000 |
8bde7f77 | 323 | #elif defined(CONFIG_66MHz) |
6d0f6bcf | 324 | #define CONFIG_SYS_PLPRCR 0x04101000 |
dc7c9a1a | 325 | #define CONFIG_8xx_GCLK_FREQ 66000000 |
8bde7f77 | 326 | #elif defined(CONFIG_50MHz) |
6d0f6bcf | 327 | #define CONFIG_SYS_PLPRCR 0x03101000 |
dc7c9a1a | 328 | #define CONFIG_8xx_GCLK_FREQ 50000000 |
8bde7f77 | 329 | #endif |
dc7c9a1a WD |
330 | |
331 | /*----------------------------------------------------------------------- | |
332 | * SCCR - System Clock and reset Control Register 15-27 | |
333 | *----------------------------------------------------------------------- | |
334 | * Set clock output, timebase and RTC source and divider, | |
335 | * power management and some other internal clocks | |
336 | */ | |
337 | #define SCCR_MASK SCCR_EBDF11 | |
8bde7f77 | 338 | #ifdef CONFIG_BUS_DIV2 |
6d0f6bcf | 339 | #define CONFIG_SYS_SCCR 0x02020000 | SCCR_RTSEL |
dc7c9a1a | 340 | #else /* up to 50 MHz we use a 1:1 clock */ |
6d0f6bcf | 341 | #define CONFIG_SYS_SCCR 0x02000000 | SCCR_RTSEL |
8bde7f77 | 342 | #endif |
dc7c9a1a WD |
343 | |
344 | /*----------------------------------------------------------------------- | |
345 | * PCMCIA stuff | |
346 | *----------------------------------------------------------------------- | |
347 | * | |
348 | */ | |
6d0f6bcf JCPV |
349 | #define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000) |
350 | #define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 ) | |
351 | #define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000) | |
352 | #define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 ) | |
353 | #define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000) | |
354 | #define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 ) | |
355 | #define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000) | |
356 | #define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 ) | |
dc7c9a1a WD |
357 | |
358 | /*----------------------------------------------------------------------- | |
359 | * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) | |
360 | *----------------------------------------------------------------------- | |
361 | */ | |
362 | ||
53677ef1 | 363 | #undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */ |
dc7c9a1a WD |
364 | |
365 | #define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */ | |
366 | #undef CONFIG_IDE_LED /* LED for ide not supported */ | |
367 | #undef CONFIG_IDE_RESET /* reset for ide not supported */ | |
368 | ||
6d0f6bcf JCPV |
369 | #define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */ |
370 | #define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ | |
dc7c9a1a | 371 | |
6d0f6bcf JCPV |
372 | #define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010 |
373 | #define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000 | |
374 | /*#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 */ | |
375 | #define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O | |
dc7c9a1a | 376 | */ |
6d0f6bcf | 377 | #define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses |
dc7c9a1a | 378 | */ |
6d0f6bcf | 379 | #define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers |
dc7c9a1a | 380 | */ |
8bde7f77 | 381 | #define CONFIG_ATAPI |
6d0f6bcf | 382 | #define CONFIG_SYS_PIO_MODE 0 |
dc7c9a1a WD |
383 | |
384 | /*----------------------------------------------------------------------- | |
385 | * | |
386 | *----------------------------------------------------------------------- | |
387 | * | |
388 | */ | |
6d0f6bcf JCPV |
389 | /*#define CONFIG_SYS_DER 0x2002000F*/ |
390 | #define CONFIG_SYS_DER 0x0 | |
dc7c9a1a WD |
391 | |
392 | /* | |
393 | * Init Memory Controller: | |
394 | * | |
395 | * BR0/1 and OR0/1 (FLASH) | |
396 | */ | |
397 | ||
398 | #define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ | |
399 | #define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ | |
400 | ||
401 | /* used to re-map FLASH both when starting from SRAM or FLASH: | |
402 | * restrict access enough to keep SRAM working (if any) | |
403 | * but not too much to meddle with FLASH accesses | |
404 | */ | |
6d0f6bcf JCPV |
405 | #define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */ |
406 | #define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ | |
dc7c9a1a WD |
407 | |
408 | /* | |
409 | * FLASH timing: | |
410 | */ | |
8bde7f77 | 411 | #if defined(CONFIG_100MHz) |
6d0f6bcf JCPV |
412 | #define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4 |
413 | #define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 | |
414 | #define CONFIG_SYS_MxMR_PTx 0x61000000 | |
415 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
416 | |
417 | #elif defined(CONFIG_80MHz) | |
6d0f6bcf JCPV |
418 | #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 |
419 | #define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 | |
420 | #define CONFIG_SYS_MxMR_PTx 0x4e000000 | |
421 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a | 422 | |
8bde7f77 | 423 | #elif defined(CONFIG_75MHz) |
6d0f6bcf JCPV |
424 | #define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4 |
425 | #define CONFIG_SYS_OR_TIMING_DOC 0x000002f4 | |
426 | #define CONFIG_SYS_MxMR_PTx 0x49000000 | |
427 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
428 | |
429 | #elif defined(CONFIG_66MHz) | |
6d0f6bcf | 430 | #define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 | OR_TRLX | OR_CSNT_SAM | \ |
8bde7f77 | 431 | OR_SCY_3_CLK | OR_EHTR | OR_BI) |
6d0f6bcf JCPV |
432 | /*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */ |
433 | #define CONFIG_SYS_OR_TIMING_DOC 0x000003f4 | |
434 | #define CONFIG_SYS_MxMR_PTx 0x40000000 | |
435 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
436 | |
437 | #else /* 50 MHz */ | |
6d0f6bcf JCPV |
438 | #define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4 |
439 | #define CONFIG_SYS_OR_TIMING_DOC 0x000001f4 | |
440 | #define CONFIG_SYS_MxMR_PTx 0x30000000 | |
441 | #define CONFIG_SYS_MPTPR 0x400 | |
dc7c9a1a WD |
442 | #endif /*CONFIG_??MHz */ |
443 | ||
444 | ||
445 | #if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */ | |
6d0f6bcf JCPV |
446 | #define CONFIG_SYS_OR0_PRELIM (0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH) |
447 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8) | |
dc7c9a1a | 448 | #elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */ |
6d0f6bcf JCPV |
449 | #define CONFIG_SYS_OR0_PRELIM (0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH) |
450 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16) | |
dc7c9a1a | 451 | #elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */ |
6d0f6bcf JCPV |
452 | #define CONFIG_SYS_OR0_PRELIM (0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH) |
453 | #define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) | |
dc7c9a1a WD |
454 | #else |
455 | #error Boot device port size missing. | |
456 | #endif | |
457 | ||
458 | /* | |
459 | * Disk-On-Chip configuration | |
460 | */ | |
461 | ||
6d0f6bcf JCPV |
462 | #define CONFIG_SYS_DOC_SHORT_TIMEOUT |
463 | #define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */ | |
dc7c9a1a | 464 | |
6d0f6bcf JCPV |
465 | #define CONFIG_SYS_DOC_SUPPORT_2000 |
466 | #define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM | |
467 | #define CONFIG_SYS_DOC_BASE 0x80000000 | |
dc7c9a1a | 468 | |
dc7c9a1a | 469 | #endif /* __CONFIG_H */ |