[people/ms/u-boot.git] / include / configs / svm_sc8xx.h

/*
 * (C) Copyright 2000, 2001, 2002
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

/*
 * board/config.h - configuration options, board specific,
 *                  for SinoVee Microsystems SC8xx series SBC
 *                  http://www.fel.com.cn (Chinese)
 *                  http://www.sinovee.com (English)
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/* Custom configuration */
/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
/*#define CONFIG_FEL8xx_AT */
/*#define CONFIG_LCD */
/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
/* #define CONFIG_50MHz */
/* #define CONFIG_66MHz */
/* #define CONFIG_75MHz */
#define CONFIG_80MHz
/*#define CONFIG_100MHz */
/* #define CONFIG_BUS_DIV2	1 */
/* for BOOT device port size */
/* #define CONFIG_BOOT_8B */
#define CONFIG_BOOT_16B
/* #define CONFIG_BOOT_32B */
/* #define CONFIG_CAN_DRIVER */
/* #define DEBUG */
#define CONFIG_FEC_ENET

/* #define CONFIG_SDRAM_16M */
#define CONFIG_SDRAM_32M
/* #define CONFIG_SDRAM_64M */
#define CONFIG_SYS_RESET_ADDRESS 0xffffffff
/*
 * High Level Configuration Options
 * (easy to change)
 */

/* #define CONFIG_MPC823		1 */
/* #define CONFIG_MPC850		1 */
#define CONFIG_MPC855		1
/* #define CONFIG_MPC860		1 */
/* #define CONFIG_MPC860T		1 */

#undef	CONFIG_WATCHDOG			/* watchdog */

#define CONFIG_SVM_SC8xx		1	/* ...on SVM SC8xx series	*/

#ifdef	CONFIG_LCD			/* with LCD controller ?	*/
/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display	*/
#endif

#define	CONFIG_8xx_CONS_SMC1	1	/* Console is on SMC1		*/
#undef	CONFIG_8xx_CONS_SMC2
#undef	CONFIG_8xx_CONS_NONE
#define CONFIG_BAUDRATE		19200	/* console baudrate = 115kbps	*/
#if 0
#define CONFIG_BOOTDELAY	-1	/* autoboot disabled		*/
#else
#define CONFIG_BOOTDELAY	1	/* autoboot after 5 seconds	*/
#endif

#define	CONFIG_CLOCKS_IN_MHZ	1	/* clocks passsed to Linux in MHz */

#define CONFIG_BOARD_TYPES      1       /* support board types          */

#define CONFIG_PREBOOT	"echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"

#undef	CONFIG_BOOTARGS
#define CONFIG_EXTRA_ENV_SETTINGS                                       \
	"nfsargs=setenv bootargs root=/dev/nfs rw "                     \
	 "nfsroot=${serverip}:${rootpath}\0"                     \
	"ramargs=setenv bootargs root=/dev/ram rw\0"                    \
	"addip=setenv bootargs ${bootargs} "                            \
	       "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}"      \
		":${hostname}:${netdev}:off panic=1\0"                  \
		"flash_nfs=run nfsargs addip;"                                  \
	     "bootm ${kernel_addr}\0"                                \
	"flash_self=run ramargs addip;"                                 \
	       "bootm ${kernel_addr} ${ramdisk_addr}\0"                \
	"net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0"     \
	"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0"                                  \
	"bootfile=pImage-sc855t\0"                           \
	"kernel_addr=48000000\0"                                        \
	"ramdisk_addr=48100000\0"                                       \
	""
#define CONFIG_BOOTCOMMAND							\
	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} "	\
	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; "	\
	"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"

#define CONFIG_LOADS_ECHO	1	/* echo on for serial download	*/
#undef	CONFIG_SYS_LOADS_BAUD_CHANGE		/* don't allow baudrate change	*/


#ifdef CONFIG_LCD
# undef	 CONFIG_STATUS_LED		/* disturbs display		*/
#else
# define CONFIG_STATUS_LED	1	/* Status LED enabled		*/
#endif	/* CONFIG_LCD */

#undef	CONFIG_CAN_DRIVER		/* CAN Driver support disabled	*/

/*
 * BOOTP options
 */
#define CONFIG_BOOTP_SUBNETMASK
#define CONFIG_BOOTP_GATEWAY
#define CONFIG_BOOTP_HOSTNAME
#define CONFIG_BOOTP_BOOTPATH
#define CONFIG_BOOTP_BOOTFILESIZE

#define CONFIG_MAC_PARTITION
#define CONFIG_DOS_PARTITION

#define	CONFIG_RTC_MPC8xx		/* use internal RTC of MPC8xx	*/


/*
 * Command line configuration.
 */
#include <config_cmd_default.h>

#define CONFIG_CMD_ASKENV
#define CONFIG_CMD_DHCP
#define CONFIG_CMD_DOC
#define CONFIG_CMD_DATE


#define CONFIG_NAND_LEGACY

/*
 * Miscellaneous configurable options
 */
#define	CONFIG_SYS_LONGHELP			/* undef to save memory		*/
#define	CONFIG_SYS_PROMPT	"=> "		/* Monitor Command Prompt	*/

#ifdef  CONFIG_SYS_HUSH_PARSER
#define CONFIG_SYS_PROMPT_HUSH_PS2     "> "
#endif

#if defined(CONFIG_CMD_KGDB)
#define	CONFIG_SYS_CBSIZE	1024		/* Console I/O Buffer Size	*/
#else
#define	CONFIG_SYS_CBSIZE	256		/* Console I/O Buffer Size	*/
#endif
#define	CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
#define	CONFIG_SYS_MAXARGS	16		/* max number of command args	*/
#define CONFIG_SYS_BARGSIZE	CONFIG_SYS_CBSIZE	/* Boot Argument Buffer Size	*/

#define CONFIG_SYS_MEMTEST_START	0x0400000	/* memtest works on	*/
#define CONFIG_SYS_MEMTEST_END		0x0C00000	/* 4 ... 12 MB in DRAM	*/

#define	CONFIG_SYS_LOAD_ADDR		0x100000	/* default load address	*/

#define	CONFIG_SYS_HZ		1000		/* decrementer freq: 1 ms ticks	*/

#define CONFIG_SYS_BAUDRATE_TABLE	{ 9600, 19200, 38400, 57600, 115200 }

/*
 * Low Level Configuration Settings
 * (address mappings, register initial values, etc.)
 * You should know what you are doing if you make changes here.
 */
/*-----------------------------------------------------------------------
 * Internal Memory Mapped Register
 */
#define CONFIG_SYS_IMMR		0xFF000000

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in DPRAM)
 */
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_IMMR
#define	CONFIG_SYS_INIT_RAM_END	0x2F00	/* End of used area in DPRAM	*/
#define	CONFIG_SYS_GBL_DATA_SIZE	64  /* size in bytes reserved for initial data */
#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
#define	CONFIG_SYS_INIT_SP_OFFSET	CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 * Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
 */
#define	CONFIG_SYS_SDRAM_BASE		0x00000000
#define CONFIG_SYS_FLASH_BASE		0x40000000
#define	CONFIG_SYS_MONITOR_LEN		(384 << 10)	/* Reserve 192 kB for Monitor	*/
#define CONFIG_SYS_MONITOR_BASE	CONFIG_SYS_FLASH_BASE
#define	CONFIG_SYS_MALLOC_LEN		(128 << 10)	/* Reserve 128 kB for malloc()	*/

/*
 * For booting Linux, the board info and command line data
 * have to be in the first 8 MB of memory, since this is
 * the maximum mapped by the Linux kernel during initialization.
 */
#define	CONFIG_SYS_BOOTMAPSZ		(8 << 20)	/* Initial Memory map for Linux	*/

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	67	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define	CONFIG_ENV_IS_IN_FLASH	1

#ifdef CONFIG_BOOT_8B
#define	CONFIG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
#elif defined (CONFIG_BOOT_16B)
#define	CONFIG_ENV_OFFSET		0x10000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x10000	/* Total Size of Environment Sector	*/
#elif defined (CONFIG_BOOT_32B)
#define	CONFIG_ENV_OFFSET		0x8000	/*   Offset   of Environment Sector	*/
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/
#endif

/* Address and size of Redundant Environment Sector     */
#define CONFIG_ENV_OFFSET_REDUND   (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
#define CONFIG_ENV_SIZE_REDUND     (CONFIG_ENV_SIZE)


/*-----------------------------------------------------------------------
 * Hardware Information Block
 */
#define CONFIG_SYS_HWINFO_OFFSET	0x0003FFC0	/* offset of HW Info block */
#define CONFIG_SYS_HWINFO_SIZE		0x00000040	/* size   of HW Info block */
#define CONFIG_SYS_HWINFO_MAGIC	0x46454C38	/* 'SVM8' */

/*-----------------------------------------------------------------------
 * Cache Configuration
 */
#define CONFIG_SYS_CACHELINE_SIZE	16	/* For all MPC8xx CPUs			*/
#if defined(CONFIG_CMD_KGDB)
#define CONFIG_SYS_CACHELINE_SHIFT	4	/* log base 2 of the above value	*/
#endif

/*-----------------------------------------------------------------------
 * SYPCR - System Protection Control				11-9
 * SYPCR can only be written once after reset!
 *-----------------------------------------------------------------------
 * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
 */
#if defined(CONFIG_WATCHDOG)
/*#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
*/
#define CONFIG_SYS_SYPCR	(SYPCR_SWTC | SYPCR_BMT | SYPCR_SWF | \
			 SYPCR_SWE  | SYPCR_SWRI| SYPCR_SWP)
#else
#define CONFIG_SYS_SYPCR 0xffffff88
#endif

/*-----------------------------------------------------------------------
 * SIUMCR - SIU Module Configuration				11-6
 *-----------------------------------------------------------------------
 * PCMCIA config., multi-function pin tri-state
 */
#ifndef	CONFIG_CAN_DRIVER
/*#define CONFIG_SYS_SIUMCR 0x00610c00	*/
#define CONFIG_SYS_SIUMCR 0x00000000
#else	/* we must activate GPL5 in the SIUMCR for CAN */
#define CONFIG_SYS_SIUMCR	(SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01)
#endif	/* CONFIG_CAN_DRIVER */

/*-----------------------------------------------------------------------
 * TBSCR - Time Base Status and Control				11-26
 *-----------------------------------------------------------------------
 * Clear Reference Interrupt Status, Timebase freezing enabled
 */
#define CONFIG_SYS_TBSCR	0x0001

/*-----------------------------------------------------------------------
 * RTCSC - Real-Time Clock Status and Control Register		11-27
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_RTCSC	0x00c3

/*-----------------------------------------------------------------------
 * PISCR - Periodic Interrupt Status and Control		11-31
 *-----------------------------------------------------------------------
 * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
 */
#define CONFIG_SYS_PISCR	0x0000

/*-----------------------------------------------------------------------
 * PLPRCR - PLL, Low-Power, and Reset Control Register		15-30
 *-----------------------------------------------------------------------
 * Reset PLL lock status sticky bit, timer expired status bit and timer
 * interrupt status bit
 */
#if defined (CONFIG_100MHz)
#define CONFIG_SYS_PLPRCR 0x06301000
#define CONFIG_8xx_GCLK_FREQ 100000000
#elif defined (CONFIG_80MHz)
#define CONFIG_SYS_PLPRCR 0x04f01000
#define CONFIG_8xx_GCLK_FREQ 80000000
#elif defined(CONFIG_75MHz)
#define CONFIG_SYS_PLPRCR 0x04a00100
#define CONFIG_8xx_GCLK_FREQ 75000000
#elif defined(CONFIG_66MHz)
#define CONFIG_SYS_PLPRCR 0x04101000
#define CONFIG_8xx_GCLK_FREQ 66000000
#elif defined(CONFIG_50MHz)
#define CONFIG_SYS_PLPRCR 0x03101000
#define CONFIG_8xx_GCLK_FREQ 50000000
#endif

/*-----------------------------------------------------------------------
 * SCCR - System Clock and reset Control Register		15-27
 *-----------------------------------------------------------------------
 * Set clock output, timebase and RTC source and divider,
 * power management and some other internal clocks
 */
#define SCCR_MASK	SCCR_EBDF11
#ifdef	CONFIG_BUS_DIV2
#define CONFIG_SYS_SCCR	0x02020000 | SCCR_RTSEL
#else			/* up to 50 MHz we use a 1:1 clock */
#define CONFIG_SYS_SCCR    0x02000000 | SCCR_RTSEL
#endif

/*-----------------------------------------------------------------------
 * PCMCIA stuff
 *-----------------------------------------------------------------------
 *
 */
#define CONFIG_SYS_PCMCIA_MEM_ADDR	(0xE0000000)
#define CONFIG_SYS_PCMCIA_MEM_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_DMA_ADDR	(0xE4000000)
#define CONFIG_SYS_PCMCIA_DMA_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_ATTRB_ADDR	(0xE8000000)
#define CONFIG_SYS_PCMCIA_ATTRB_SIZE	( 64 << 20 )
#define CONFIG_SYS_PCMCIA_IO_ADDR	(0xEC000000)
#define CONFIG_SYS_PCMCIA_IO_SIZE	( 64 << 20 )

/*-----------------------------------------------------------------------
 * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
 *-----------------------------------------------------------------------
 */

#undef	CONFIG_IDE_8xx_PCCARD		/* Use IDE with PC Card	Adapter	*/

#define	CONFIG_IDE_8xx_DIRECT	1	/* Direct IDE    not supported	*/
#undef	CONFIG_IDE_LED			/* LED   for ide not supported	*/
#undef	CONFIG_IDE_RESET		/* reset for ide not supported	*/

#define CONFIG_SYS_IDE_MAXBUS		1	/* max. 1 IDE bus		*/
#define CONFIG_SYS_IDE_MAXDEVICE	1	/* max. 1 drive per IDE bus	*/

#define CONFIG_SYS_ATA_BASE_ADDR       0xFE100010
#define CONFIG_SYS_ATA_IDE0_OFFSET     0x0000
/*#define CONFIG_SYS_ATA_IDE1_OFFSET     0x0C00 */
#define CONFIG_SYS_ATA_DATA_OFFSET     0x0000  /* Offset for data I/O
					   */
#define CONFIG_SYS_ATA_REG_OFFSET      0x0200  /* Offset for normal register accesses
					   */
#define CONFIG_SYS_ATA_ALT_OFFSET      0x0210  /* Offset for alternate registers
					   */
#define CONFIG_ATAPI
#define CONFIG_SYS_PIO_MODE 0

/*-----------------------------------------------------------------------
 *
 *-----------------------------------------------------------------------
 *
 */
/*#define	CONFIG_SYS_DER	0x2002000F*/
#define CONFIG_SYS_DER	0x0

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM	0x40000000	/* FLASH bank #0	*/
#define FLASH_BASE1_PRELIM	0x60000000	/* FLASH bank #0	*/

/* used to re-map FLASH both when starting from SRAM or FLASH:
 * restrict access enough to keep SRAM working (if any)
 * but not too much to meddle with FLASH accesses
 */
#define CONFIG_SYS_REMAP_OR_AM		0x80000000	/* OR addr mask */
#define CONFIG_SYS_PRELIM_OR_AM	0xE0000000	/* OR addr mask */

/*
 * FLASH timing:
 */
#if defined(CONFIG_100MHz)
#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4
#define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
#define CONFIG_SYS_MxMR_PTx 0x61000000
#define CONFIG_SYS_MPTPR 0x400

#elif  defined(CONFIG_80MHz)
#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
#define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
#define CONFIG_SYS_MxMR_PTx 0x4e000000
#define CONFIG_SYS_MPTPR 0x400

#elif defined(CONFIG_75MHz)
#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4
#define CONFIG_SYS_OR_TIMING_DOC   0x000002f4
#define CONFIG_SYS_MxMR_PTx 0x49000000
#define CONFIG_SYS_MPTPR 0x400

#elif defined(CONFIG_66MHz)
#define CONFIG_SYS_OR_TIMING_FLASH     (OR_ACS_DIV1  | OR_TRLX | OR_CSNT_SAM | \
	OR_SCY_3_CLK | OR_EHTR | OR_BI)
/*#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 */
#define CONFIG_SYS_OR_TIMING_DOC   0x000003f4
#define CONFIG_SYS_MxMR_PTx  0x40000000
#define CONFIG_SYS_MPTPR 0x400

#else		/*   50 MHz */
#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
#define CONFIG_SYS_OR_TIMING_DOC   0x000001f4
#define CONFIG_SYS_MxMR_PTx  0x30000000
#define CONFIG_SYS_MPTPR 0x400
#endif	/*CONFIG_??MHz */


#if  defined (CONFIG_BOOT_8B)   /* 512K X 8 ,29F040 , 2MB space */
#define CONFIG_SYS_OR0_PRELIM	(0xffe00000 | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_8)
#elif  defined (CONFIG_BOOT_16B)   /* 29lv160 X 16 , 4MB space */
#define CONFIG_SYS_OR0_PRELIM	(0xffc00000 | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V | BR_PS_16)
#elif defined( CONFIG_BOOT_32B )  /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
#define CONFIG_SYS_OR0_PRELIM	(0xfc000000 | CONFIG_SYS_OR_TIMING_FLASH)
#define CONFIG_SYS_BR0_PRELIM	((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V )
#else
#error Boot device port size missing.
#endif

/*
 * Disk-On-Chip configuration
 */

#define CONFIG_SYS_DOC_SHORT_TIMEOUT
#define CONFIG_SYS_MAX_DOC_DEVICE      1       /* Max number of DOC devices    */

#define CONFIG_SYS_DOC_SUPPORT_2000
#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
#define CONFIG_SYS_DOC_BASE 0x80000000


/*
 * Internal Definitions
 *
 * Boot Flags
 */
#define	BOOTFLAG_COLD	0x01		/* Normal Power-On: Boot from FLASH	*/
#define BOOTFLAG_WARM	0x02		/* Software reboot			*/

#endif	/* __CONFIG_H */
Commit	Line	Data
dc7c9a1a WD	1	/*
	2	* (C) Copyright 2000, 2001, 2002
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	/*
	25	* board/config.h - configuration options, board specific,
	26	* for SinoVee Microsystems SC8xx series SBC
	27	* http://www.fel.com.cn (Chinese)
	28	* http://www.sinovee.com (English)
	29	*/
	30
	31	#ifndef __CONFIG_H
	32	#define __CONFIG_H
	33
	34	/* Custom configuration */
	35	/* SC823,SC850,SC860SAR, FEL8xx-AT(823/850/860) */
	36	/* SC85T,SC860T, FEL8xx-AT(855T/860T) */
	37	/#define CONFIG_FEL8xx_AT /
	38	/#define CONFIG_LCD /
	39	/* if core > 50MHz , un-comment CONFIG_BUS_DIV2 */
	40	/* #define CONFIG_50MHz */
	41	/* #define CONFIG_66MHz */
	42	/* #define CONFIG_75MHz */
	43	#define CONFIG_80MHz
	44	/#define CONFIG_100MHz /
	45	/* #define CONFIG_BUS_DIV2 1 */
	46	/* for BOOT device port size */
	47	/* #define CONFIG_BOOT_8B */
	48	#define CONFIG_BOOT_16B
	49	/* #define CONFIG_BOOT_32B */
	50	/* #define CONFIG_CAN_DRIVER */
	51	/* #define DEBUG */
	52	#define CONFIG_FEC_ENET
	53
	54	/* #define CONFIG_SDRAM_16M */
	55	#define CONFIG_SDRAM_32M
	56	/* #define CONFIG_SDRAM_64M */
6d0f6bcf	57	#define CONFIG_SYS_RESET_ADDRESS 0xffffffff
dc7c9a1a WD	58	/*
	59	* High Level Configuration Options
	60	* (easy to change)
	61	*/
	62
	63	/* #define CONFIG_MPC823 1 */
	64	/* #define CONFIG_MPC850 1 */
	65	#define CONFIG_MPC855 1
	66	/* #define CONFIG_MPC860 1 */
	67	/* #define CONFIG_MPC860T 1 */
	68
	69	#undef CONFIG_WATCHDOG /* watchdog */
	70
53677ef1	71	#define CONFIG_SVM_SC8xx 1 /* ...on SVM SC8xx series */
dc7c9a1a WD	72
dc7c9a1a WD	73	#ifdef CONFIG_LCD /* with LCD controller ? */
fd3103bb	74	/* #define CONFIG_NEC_NL6448BC20 1 / * use NEC NL6448BC20 display */
dc7c9a1a WD	75	#endif
	76
	77	#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */
	78	#undef CONFIG_8xx_CONS_SMC2
	79	#undef CONFIG_8xx_CONS_NONE
	80	#define CONFIG_BAUDRATE 19200 /* console baudrate = 115kbps */
	81	#if 0
	82	#define CONFIG_BOOTDELAY -1 /* autoboot disabled */
	83	#else
	84	#define CONFIG_BOOTDELAY 1 /* autoboot after 5 seconds */
	85	#endif
	86
	87	#define CONFIG_CLOCKS_IN_MHZ 1 /* clocks passsed to Linux in MHz */
	88
	89	#define CONFIG_BOARD_TYPES 1 /* support board types */
	90
	91	#define CONFIG_PREBOOT "echo;echo Welcome to U-Boot SVM port;echo;echo Type \"? or help\" to get on-line help;echo"
	92
	93	#undef CONFIG_BOOTARGS
	94	#define CONFIG_EXTRA_ENV_SETTINGS \
8bde7f77	95	"nfsargs=setenv bootargs root=/dev/nfs rw " \
fe126d8b	96	"nfsroot=${serverip}:${rootpath}\0" \
8bde7f77	97	"ramargs=setenv bootargs root=/dev/ram rw\0" \
fe126d8b WD	98	"addip=setenv bootargs ${bootargs} " \
	99	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \
	100	":${hostname}:${netdev}:off panic=1\0" \
8bde7f77	101	"flash_nfs=run nfsargs addip;" \
fe126d8b	102	"bootm ${kernel_addr}\0" \
8bde7f77	103	"flash_self=run ramargs addip;" \
fe126d8b WD	104	"bootm ${kernel_addr} ${ramdisk_addr}\0" \
fe126d8b WD	105	"net_nfs=tftp 0x210000 ${bootfile};run nfsargs addip;bootm\0" \
8bde7f77 WD	106	"rootpath=/opt/sinovee/ppc8xx-linux-2.0/target\0" \
	107	"bootfile=pImage-sc855t\0" \
	108	"kernel_addr=48000000\0" \
	109	"ramdisk_addr=48100000\0" \
	110	""
dc7c9a1a	111	#define CONFIG_BOOTCOMMAND \
53677ef1 WD	112	"setenv bootargs root=/dev/nfs rw nfsroot=${serverip}:${rootpath} " \
53677ef1 WD	113	"ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}:${hostname}::off; " \
dc7c9a1a WD	114	"tftpboot 0x210000 pImage-sc855t;bootm 0x210000"
	115
	116	#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */
6d0f6bcf	117	#undef CONFIG_SYS_LOADS_BAUD_CHANGE /* don't allow baudrate change */
dc7c9a1a WD	118
	119
	120	#ifdef CONFIG_LCD
	121	# undef CONFIG_STATUS_LED /* disturbs display */
	122	#else
	123	# define CONFIG_STATUS_LED 1 /* Status LED enabled */
	124	#endif /* CONFIG_LCD */
	125
	126	#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */
	127
d3b8c1a7 JL	128	/*
	129	* BOOTP options
	130	*/
	131	#define CONFIG_BOOTP_SUBNETMASK
	132	#define CONFIG_BOOTP_GATEWAY
	133	#define CONFIG_BOOTP_HOSTNAME
	134	#define CONFIG_BOOTP_BOOTPATH
	135	#define CONFIG_BOOTP_BOOTFILESIZE
dc7c9a1a WD	136
	137	#define CONFIG_MAC_PARTITION
	138	#define CONFIG_DOS_PARTITION
	139
	140	#define CONFIG_RTC_MPC8xx /* use internal RTC of MPC8xx */
	141
46da1e96 JL	142
	143	/*
	144	* Command line configuration.
	145	*/
	146	#include <config_cmd_default.h>
	147
	148	#define CONFIG_CMD_ASKENV
	149	#define CONFIG_CMD_DHCP
	150	#define CONFIG_CMD_DOC
	151	#define CONFIG_CMD_DATE
	152
	153
cc4a0cee	154	#define CONFIG_NAND_LEGACY
dc7c9a1a WD	155
	156	/*
	157	* Miscellaneous configurable options
	158	*/
6d0f6bcf JCPV	159	#define CONFIG_SYS_LONGHELP /* undef to save memory */
6d0f6bcf JCPV	160	#define CONFIG_SYS_PROMPT "=> " /* Monitor Command Prompt */
dc7c9a1a	161
6d0f6bcf JCPV	162	#ifdef CONFIG_SYS_HUSH_PARSER
6d0f6bcf JCPV	163	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
dc7c9a1a WD	164	#endif
dc7c9a1a WD	165
46da1e96	166	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	167	#define CONFIG_SYS_CBSIZE 1024 /* Console I/O Buffer Size */
dc7c9a1a	168	#else
6d0f6bcf	169	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
dc7c9a1a	170	#endif
6d0f6bcf JCPV	171	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */
	172	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	173	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */
dc7c9a1a	174
6d0f6bcf JCPV	175	#define CONFIG_SYS_MEMTEST_START 0x0400000 /* memtest works on */
6d0f6bcf JCPV	176	#define CONFIG_SYS_MEMTEST_END 0x0C00000 /* 4 ... 12 MB in DRAM */
dc7c9a1a	177
6d0f6bcf	178	#define CONFIG_SYS_LOAD_ADDR 0x100000 /* default load address */
dc7c9a1a	179
6d0f6bcf	180	#define CONFIG_SYS_HZ 1000 /* decrementer freq: 1 ms ticks */
dc7c9a1a	181
6d0f6bcf	182	#define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
dc7c9a1a WD	183
	184	/*
	185	* Low Level Configuration Settings
	186	* (address mappings, register initial values, etc.)
	187	* You should know what you are doing if you make changes here.
	188	*/
	189	/*-----------------------------------------------------------------------
	190	* Internal Memory Mapped Register
	191	*/
6d0f6bcf	192	#define CONFIG_SYS_IMMR 0xFF000000
dc7c9a1a WD	193
	194	/*-----------------------------------------------------------------------
	195	* Definitions for initial stack pointer and data area (in DPRAM)
	196	*/
6d0f6bcf JCPV	197	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_IMMR
	198	#define CONFIG_SYS_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */
	199	#define CONFIG_SYS_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */
	200	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_END - CONFIG_SYS_GBL_DATA_SIZE)
	201	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
dc7c9a1a WD	202
	203	/*-----------------------------------------------------------------------
	204	* Start addresses for the final memory configuration
	205	* (Set up by the startup code)
6d0f6bcf	206	* Please note that CONFIG_SYS_SDRAM_BASE _must_ start at 0
dc7c9a1a	207	*/
6d0f6bcf JCPV	208	#define CONFIG_SYS_SDRAM_BASE 0x00000000
	209	#define CONFIG_SYS_FLASH_BASE 0x40000000
	210	#define CONFIG_SYS_MONITOR_LEN (384 << 10) /* Reserve 192 kB for Monitor */
	211	#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
	212	#define CONFIG_SYS_MALLOC_LEN (128 << 10) /* Reserve 128 kB for malloc() */
dc7c9a1a WD	213
	214	/*
	215	* For booting Linux, the board info and command line data
	216	* have to be in the first 8 MB of memory, since this is
	217	* the maximum mapped by the Linux kernel during initialization.
	218	*/
6d0f6bcf	219	#define CONFIG_SYS_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */
dc7c9a1a WD	220
	221	/*-----------------------------------------------------------------------
	222	* FLASH organization
	223	*/
6d0f6bcf JCPV	224	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	225	#define CONFIG_SYS_MAX_FLASH_SECT 67 /* max number of sectors on one chip */
dc7c9a1a	226
6d0f6bcf JCPV	227	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	228	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
dc7c9a1a	229
5a1aceb0	230	#define CONFIG_ENV_IS_IN_FLASH 1
dc7c9a1a WD	231
dc7c9a1a WD	232	#ifdef CONFIG_BOOT_8B
0e8d1586 JCPV	233	#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
0e8d1586 JCPV	234	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
dc7c9a1a	235	#elif defined (CONFIG_BOOT_16B)
0e8d1586 JCPV	236	#define CONFIG_ENV_OFFSET 0x10000 /* Offset of Environment Sector */
0e8d1586 JCPV	237	#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */
dc7c9a1a	238	#elif defined (CONFIG_BOOT_32B)
0e8d1586 JCPV	239	#define CONFIG_ENV_OFFSET 0x8000 /* Offset of Environment Sector */
0e8d1586 JCPV	240	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
dc7c9a1a WD	241	#endif
	242
	243	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	244	#define CONFIG_ENV_OFFSET_REDUND (CONFIG_ENV_OFFSET+CONFIG_ENV_SIZE)
0e8d1586 JCPV	245	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
dc7c9a1a WD	246
	247
	248	/*-----------------------------------------------------------------------
	249	* Hardware Information Block
	250	*/
6d0f6bcf JCPV	251	#define CONFIG_SYS_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */
	252	#define CONFIG_SYS_HWINFO_SIZE 0x00000040 /* size of HW Info block */
	253	#define CONFIG_SYS_HWINFO_MAGIC 0x46454C38 /* 'SVM8' */
dc7c9a1a WD	254
	255	/*-----------------------------------------------------------------------
	256	* Cache Configuration
	257	*/
6d0f6bcf	258	#define CONFIG_SYS_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */
46da1e96	259	#if defined(CONFIG_CMD_KGDB)
6d0f6bcf	260	#define CONFIG_SYS_CACHELINE_SHIFT 4 /* log base 2 of the above value */
dc7c9a1a WD	261	#endif
	262
	263	/*-----------------------------------------------------------------------
	264	* SYPCR - System Protection Control 11-9
	265	* SYPCR can only be written once after reset!
	266	*-----------------------------------------------------------------------
	267	* Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze
	268	*/
	269	#if defined(CONFIG_WATCHDOG)
6d0f6bcf	270	/*#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_BME \| SYPCR_SWF \| \
dc7c9a1a WD	271	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
dc7c9a1a WD	272	*/
6d0f6bcf	273	#define CONFIG_SYS_SYPCR (SYPCR_SWTC \| SYPCR_BMT \| SYPCR_SWF \| \
dc7c9a1a WD	274	SYPCR_SWE \| SYPCR_SWRI\| SYPCR_SWP)
dc7c9a1a WD	275	#else
6d0f6bcf	276	#define CONFIG_SYS_SYPCR 0xffffff88
dc7c9a1a WD	277	#endif
	278
	279	/*-----------------------------------------------------------------------
	280	* SIUMCR - SIU Module Configuration 11-6
	281	*-----------------------------------------------------------------------
	282	* PCMCIA config., multi-function pin tri-state
	283	*/
	284	#ifndef CONFIG_CAN_DRIVER
6d0f6bcf JCPV	285	/#define CONFIG_SYS_SIUMCR 0x00610c00 /
6d0f6bcf JCPV	286	#define CONFIG_SYS_SIUMCR 0x00000000
dc7c9a1a	287	#else /* we must activate GPL5 in the SIUMCR for CAN */
6d0f6bcf	288	#define CONFIG_SYS_SIUMCR (SIUMCR_DBGC11 \| SIUMCR_DBPC00 \| SIUMCR_MLRC01)
dc7c9a1a WD	289	#endif /* CONFIG_CAN_DRIVER */
	290
	291	/*-----------------------------------------------------------------------
	292	* TBSCR - Time Base Status and Control 11-26
	293	*-----------------------------------------------------------------------
	294	* Clear Reference Interrupt Status, Timebase freezing enabled
	295	*/
6d0f6bcf	296	#define CONFIG_SYS_TBSCR 0x0001
dc7c9a1a WD	297
	298	/*-----------------------------------------------------------------------
	299	* RTCSC - Real-Time Clock Status and Control Register 11-27
	300	*-----------------------------------------------------------------------
	301	*/
6d0f6bcf	302	#define CONFIG_SYS_RTCSC 0x00c3
dc7c9a1a WD	303
	304	/*-----------------------------------------------------------------------
	305	* PISCR - Periodic Interrupt Status and Control 11-31
	306	*-----------------------------------------------------------------------
	307	* Clear Periodic Interrupt Status, Interrupt Timer freezing enabled
	308	*/
6d0f6bcf	309	#define CONFIG_SYS_PISCR 0x0000
dc7c9a1a WD	310
	311	/*-----------------------------------------------------------------------
	312	* PLPRCR - PLL, Low-Power, and Reset Control Register 15-30
	313	*-----------------------------------------------------------------------
	314	* Reset PLL lock status sticky bit, timer expired status bit and timer
	315	* interrupt status bit
	316	*/
	317	#if defined (CONFIG_100MHz)
6d0f6bcf	318	#define CONFIG_SYS_PLPRCR 0x06301000
dc7c9a1a WD	319	#define CONFIG_8xx_GCLK_FREQ 100000000
dc7c9a1a WD	320	#elif defined (CONFIG_80MHz)
6d0f6bcf	321	#define CONFIG_SYS_PLPRCR 0x04f01000
dc7c9a1a	322	#define CONFIG_8xx_GCLK_FREQ 80000000
8bde7f77	323	#elif defined(CONFIG_75MHz)
6d0f6bcf	324	#define CONFIG_SYS_PLPRCR 0x04a00100
dc7c9a1a	325	#define CONFIG_8xx_GCLK_FREQ 75000000
8bde7f77	326	#elif defined(CONFIG_66MHz)
6d0f6bcf	327	#define CONFIG_SYS_PLPRCR 0x04101000
dc7c9a1a	328	#define CONFIG_8xx_GCLK_FREQ 66000000
8bde7f77	329	#elif defined(CONFIG_50MHz)
6d0f6bcf	330	#define CONFIG_SYS_PLPRCR 0x03101000
dc7c9a1a	331	#define CONFIG_8xx_GCLK_FREQ 50000000
8bde7f77	332	#endif
dc7c9a1a WD	333
	334	/*-----------------------------------------------------------------------
	335	* SCCR - System Clock and reset Control Register 15-27
	336	*-----------------------------------------------------------------------
	337	* Set clock output, timebase and RTC source and divider,
	338	* power management and some other internal clocks
	339	*/
	340	#define SCCR_MASK SCCR_EBDF11
8bde7f77	341	#ifdef CONFIG_BUS_DIV2
6d0f6bcf	342	#define CONFIG_SYS_SCCR 0x02020000 \| SCCR_RTSEL
dc7c9a1a	343	#else /* up to 50 MHz we use a 1:1 clock */
6d0f6bcf	344	#define CONFIG_SYS_SCCR 0x02000000 \| SCCR_RTSEL
8bde7f77	345	#endif
dc7c9a1a WD	346
	347	/*-----------------------------------------------------------------------
	348	* PCMCIA stuff
	349	*-----------------------------------------------------------------------
	350	*
	351	*/
6d0f6bcf JCPV	352	#define CONFIG_SYS_PCMCIA_MEM_ADDR (0xE0000000)
	353	#define CONFIG_SYS_PCMCIA_MEM_SIZE ( 64 << 20 )
	354	#define CONFIG_SYS_PCMCIA_DMA_ADDR (0xE4000000)
	355	#define CONFIG_SYS_PCMCIA_DMA_SIZE ( 64 << 20 )
	356	#define CONFIG_SYS_PCMCIA_ATTRB_ADDR (0xE8000000)
	357	#define CONFIG_SYS_PCMCIA_ATTRB_SIZE ( 64 << 20 )
	358	#define CONFIG_SYS_PCMCIA_IO_ADDR (0xEC000000)
	359	#define CONFIG_SYS_PCMCIA_IO_SIZE ( 64 << 20 )
dc7c9a1a WD	360
	361	/*-----------------------------------------------------------------------
	362	* IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter)
	363	*-----------------------------------------------------------------------
	364	*/
	365
53677ef1	366	#undef CONFIG_IDE_8xx_PCCARD /* Use IDE with PC Card Adapter */
dc7c9a1a WD	367
	368	#define CONFIG_IDE_8xx_DIRECT 1 /* Direct IDE not supported */
	369	#undef CONFIG_IDE_LED /* LED for ide not supported */
	370	#undef CONFIG_IDE_RESET /* reset for ide not supported */
	371
6d0f6bcf JCPV	372	#define CONFIG_SYS_IDE_MAXBUS 1 /* max. 1 IDE bus */
6d0f6bcf JCPV	373	#define CONFIG_SYS_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */
dc7c9a1a	374
6d0f6bcf JCPV	375	#define CONFIG_SYS_ATA_BASE_ADDR 0xFE100010
	376	#define CONFIG_SYS_ATA_IDE0_OFFSET 0x0000
	377	/#define CONFIG_SYS_ATA_IDE1_OFFSET 0x0C00 /
	378	#define CONFIG_SYS_ATA_DATA_OFFSET 0x0000 /* Offset for data I/O
dc7c9a1a	379	*/
6d0f6bcf	380	#define CONFIG_SYS_ATA_REG_OFFSET 0x0200 /* Offset for normal register accesses
dc7c9a1a	381	*/
6d0f6bcf	382	#define CONFIG_SYS_ATA_ALT_OFFSET 0x0210 /* Offset for alternate registers
dc7c9a1a	383	*/
8bde7f77	384	#define CONFIG_ATAPI
6d0f6bcf	385	#define CONFIG_SYS_PIO_MODE 0
dc7c9a1a WD	386
	387	/*-----------------------------------------------------------------------
	388	*
	389	*-----------------------------------------------------------------------
	390	*
	391	*/
6d0f6bcf JCPV	392	/#define CONFIG_SYS_DER 0x2002000F/
6d0f6bcf JCPV	393	#define CONFIG_SYS_DER 0x0
dc7c9a1a WD	394
	395	/*
	396	* Init Memory Controller:
	397	*
	398	* BR0/1 and OR0/1 (FLASH)
	399	*/
	400
	401	#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */
	402	#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */
	403
	404	/* used to re-map FLASH both when starting from SRAM or FLASH:
	405	* restrict access enough to keep SRAM working (if any)
	406	* but not too much to meddle with FLASH accesses
	407	*/
6d0f6bcf JCPV	408	#define CONFIG_SYS_REMAP_OR_AM 0x80000000 /* OR addr mask */
6d0f6bcf JCPV	409	#define CONFIG_SYS_PRELIM_OR_AM 0xE0000000 /* OR addr mask */
dc7c9a1a WD	410
	411	/*
	412	* FLASH timing:
	413	*/
8bde7f77	414	#if defined(CONFIG_100MHz)
6d0f6bcf JCPV	415	#define CONFIG_SYS_OR_TIMING_FLASH 0x000002f4
	416	#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4
	417	#define CONFIG_SYS_MxMR_PTx 0x61000000
	418	#define CONFIG_SYS_MPTPR 0x400
dc7c9a1a WD	419
dc7c9a1a WD	420	#elif defined(CONFIG_80MHz)
6d0f6bcf JCPV	421	#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
	422	#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4
	423	#define CONFIG_SYS_MxMR_PTx 0x4e000000
	424	#define CONFIG_SYS_MPTPR 0x400
dc7c9a1a	425
8bde7f77	426	#elif defined(CONFIG_75MHz)
6d0f6bcf JCPV	427	#define CONFIG_SYS_OR_TIMING_FLASH 0x000008f4
	428	#define CONFIG_SYS_OR_TIMING_DOC 0x000002f4
	429	#define CONFIG_SYS_MxMR_PTx 0x49000000
	430	#define CONFIG_SYS_MPTPR 0x400
dc7c9a1a WD	431
dc7c9a1a WD	432	#elif defined(CONFIG_66MHz)
6d0f6bcf	433	#define CONFIG_SYS_OR_TIMING_FLASH (OR_ACS_DIV1 \| OR_TRLX \| OR_CSNT_SAM \| \
8bde7f77	434	OR_SCY_3_CLK \| OR_EHTR \| OR_BI)
6d0f6bcf JCPV	435	/#define CONFIG_SYS_OR_TIMING_FLASH 0x000001f4 /
	436	#define CONFIG_SYS_OR_TIMING_DOC 0x000003f4
	437	#define CONFIG_SYS_MxMR_PTx 0x40000000
	438	#define CONFIG_SYS_MPTPR 0x400
dc7c9a1a WD	439
dc7c9a1a WD	440	#else /* 50 MHz */
6d0f6bcf JCPV	441	#define CONFIG_SYS_OR_TIMING_FLASH 0x00000ff4
	442	#define CONFIG_SYS_OR_TIMING_DOC 0x000001f4
	443	#define CONFIG_SYS_MxMR_PTx 0x30000000
	444	#define CONFIG_SYS_MPTPR 0x400
dc7c9a1a WD	445	#endif /CONFIG_??MHz /
	446
	447
	448	#if defined (CONFIG_BOOT_8B) /* 512K X 8 ,29F040 , 2MB space */
6d0f6bcf JCPV	449	#define CONFIG_SYS_OR0_PRELIM (0xffe00000 \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	450	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V \| BR_PS_8)
dc7c9a1a	451	#elif defined (CONFIG_BOOT_16B) /* 29lv160 X 16 , 4MB space */
6d0f6bcf JCPV	452	#define CONFIG_SYS_OR0_PRELIM (0xffc00000 \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	453	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V \| BR_PS_16)
dc7c9a1a	454	#elif defined( CONFIG_BOOT_32B ) /* 29lv160 X 2 X 32, 4/8/16MB , 64MB space */
6d0f6bcf JCPV	455	#define CONFIG_SYS_OR0_PRELIM (0xfc000000 \| CONFIG_SYS_OR_TIMING_FLASH)
6d0f6bcf JCPV	456	#define CONFIG_SYS_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) \| BR_V )
dc7c9a1a WD	457	#else
	458	#error Boot device port size missing.
	459	#endif
	460
	461	/*
	462	* Disk-On-Chip configuration
	463	*/
	464
6d0f6bcf JCPV	465	#define CONFIG_SYS_DOC_SHORT_TIMEOUT
6d0f6bcf JCPV	466	#define CONFIG_SYS_MAX_DOC_DEVICE 1 /* Max number of DOC devices */
dc7c9a1a	467
6d0f6bcf JCPV	468	#define CONFIG_SYS_DOC_SUPPORT_2000
	469	#define CONFIG_SYS_DOC_SUPPORT_MILLENNIUM
	470	#define CONFIG_SYS_DOC_BASE 0x80000000
dc7c9a1a WD	471
	472
	473	/*
	474	* Internal Definitions
	475	*
	476	* Boot Flags
	477	*/
	478	#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */
	479	#define BOOTFLAG_WARM 0x02 /* Software reboot */
	480
	481	#endif /* __CONFIG_H */