[people/ms/u-boot.git] / include / configs / taihu.h

/*
 * (C) Copyright 2000-2005
 * Wolfgang Denk, DENX Software Engineering, wd@denx.de.
 *
 * (C) Copyright 2005-2007
 * Beijing UD Technology Co., Ltd., taihusupport@amcc.com
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_H
#define __CONFIG_H


#define CONFIG_405EP		1	/* this is a PPC405 CPU */
#define CONFIG_TAIHU	        1	/*  on a taihu board */

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		taihu
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1	/* call board_early_init_f */

#define CONFIG_SYS_CLK_FREQ     33000000 /* external frequency to pll   */

#define CONFIG_NO_SERIAL_EEPROM

/*----------------------------------------------------------------------------*/
#ifdef CONFIG_NO_SERIAL_EEPROM

/*
!-------------------------------------------------------------------------------
! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
! assuming a 33MHz input clock to the 405EP from the C9531.
!-------------------------------------------------------------------------------
*/
#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
			      PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			      PLL_MALDIV_1 | PLL_PCIDIV_3)
#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10  |  \
			      PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			      PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)
#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 | PLL_PLBDIV_3 |  \
			       PLL_OPBDIV_2 | PLL_EXTBUSDIV_2 |  \
			       PLL_MALDIV_1 | PLL_PCIDIV_1)
#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10  |  \
			       PLL_FWDDIVA_3 | PLL_FWDDIVB_3 |  \
			       PLL_TUNE_15_M_40 | PLL_TUNE_VCO_HI)

#define PLLMR0_DEFAULT		PLLMR0_333_111_55_37
#define PLLMR1_DEFAULT		PLLMR1_333_111_55_37
#define PLLMR0_DEFAULT_PCI66	PLLMR0_333_111_55_111
#define PLLMR1_DEFAULT_PCI66	PLLMR1_333_111_55_111

#endif
/*----------------------------------------------------------------------------*/

#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars */

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_PPC						\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=FC000000\0"					\
	"ramdisk_addr=FC180000\0"					\
	""

#define CONFIG_PHY_ADDR		0x14	/* PHY address			*/
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_PHY1_ADDR	0x10	/* EMAC1 PHY address		*/
#define CONFIG_PHY_RESET	1

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_CACHE
#define CONFIG_CMD_PCI
#define CONFIG_CMD_SDRAM
#define CONFIG_CMD_SPI

#undef CONFIG_SPD_EEPROM		/* use SPD EEPROM for setup */
#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
#define CONFIG_SYS_SDRAM_BANKS	        2

/*
 * SDRAM configuration (please see cpu/ppc/sdram.[ch])
 */
#define CONFIG_SDRAM_BANK0	1	/* init onboard SDRAM bank 0 */
#define CONFIG_SDRAM_BANK1	1	/* init onboard SDRAM bank 1 */

/* SDRAM timings used in datasheet */
#define CONFIG_SYS_SDRAM_CL            3	/* CAS latency */
#define CONFIG_SYS_SDRAM_tRP           20	/* PRECHARGE command period */
#define CONFIG_SYS_SDRAM_tRC           66	/* ACTIVE-to-ACTIVE command period */
#define CONFIG_SYS_SDRAM_tRCD          20	/* ACTIVE-to-READ delay */
#define CONFIG_SYS_SDRAM_tRFC		66	/* Auto refresh period */

/*
 * If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
 * If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
 * Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
 * The Linux BASE_BAUD define should match this configuration.
 *    baseBaud = cpuClock/(uartDivisor*16)
 * If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
 * set Linux BASE_BAUD to 403200.
 */
#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
#undef  CONFIG_SYS_EXT_SERIAL_CLOCK           /* external serial clock */
#undef  CONFIG_SYS_405_UART_ERRATA_59         /* 405GP/CR Rev. D silicon */
#define CONFIG_SYS_BASE_BAUD		691200

/*-----------------------------------------------------------------------
 * I2C stuff
 *-----------------------------------------------------------------------
 */
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000

#define CONFIG_SYS_I2C_NOPROBES	{ {0, 0x69} } /* avoid i2c probe hangup (?) */
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS	6 /* 24C02 requires 5ms delay */

#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50	/* I2C boot EEPROM (24C02W)	*/
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN	1	/* Bytes of address		*/

#define CONFIG_SOFT_SPI
#define SPI_SCL  spi_scl
#define SPI_SDA  spi_sda
#define SPI_READ spi_read()
#define SPI_DELAY udelay(2)
#ifndef __ASSEMBLY__
void spi_scl(int);
void spi_sda(int);
unsigned char spi_read(void);
#endif

/* standard dtt sensor configuration */
#define CONFIG_DTT_DS1775	1
#define CONFIG_DTT_SENSORS	{ 0 }
#define CONFIG_SYS_I2C_DTT_ADDR	0x49

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
#define PCI_HOST_ADAPTER 0		/* configure ar pci adapter    */
#define PCI_HOST_FORCE   1		/* configure as pci host       */
#define PCI_HOST_AUTO    2		/* detected via arbiter enable */

#define CONFIG_PCI			/* include pci support	       */
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_HOST	PCI_HOST_FORCE  /* select pci host function    */
#define CONFIG_PCI_PNP			/* do pci plug-and-play        */
					/* resource configuration      */
#define CONFIG_PCI_SCAN_SHOW            /* show pci devices on startup */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */
#define CONFIG_SYS_PCI_CLASSCODE       0x0600  /* PCI Class Code: bridge/host */
#define CONFIG_SYS_PCI_PTM1LA	    0x00000000	/* point to sdram              */
#define CONFIG_SYS_PCI_PTM1MS      0x80000001	/* 2GB, enable hard-wired to 1 */
#define CONFIG_SYS_PCI_PTM1PCI     0x00000000	/* Host: use this pci address  */
#define CONFIG_SYS_PCI_PTM2LA      0x00000000	/* disabled                    */
#define CONFIG_SYS_PCI_PTM2MS	    0x00000000	/* disabled                    */
#define CONFIG_SYS_PCI_PTM2PCI     0x04000000	/* Host: use this pci address  */
#define CONFIG_EEPRO100		1

/*-----------------------------------------------------------------------
 * Start addresses for the final memory configuration
 * (Set up by the startup code)
 */
#define CONFIG_SYS_FLASH_BASE		0xFFE00000

/*-----------------------------------------------------------------------
 * FLASH organization
 */
#define CONFIG_SYS_MAX_FLASH_BANKS	2	/* max number of memory banks		*/
#define CONFIG_SYS_MAX_FLASH_SECT	256	/* max number of sectors on one chip	*/

#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_SYS_FLASH_ADDR0         0x555
#define CONFIG_SYS_FLASH_ADDR1         0x2aa
#define CONFIG_SYS_FLASH_WORD_SIZE     unsigned short

#ifdef CONFIG_ENV_IS_IN_FLASH
#define CONFIG_ENV_SECT_SIZE	0x10000	/* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)
#endif /* CONFIG_ENV_IS_IN_FLASH */

/*-----------------------------------------------------------------------
 * NVRAM organization
 */
#define CONFIG_SYS_NVRAM_BASE_ADDR	0xf0000000	/* NVRAM base address */
#define CONFIG_SYS_NVRAM_SIZE		0x1ff8		/* NVRAM size */

#ifdef CONFIG_ENV_IS_IN_NVRAM
#define CONFIG_ENV_SIZE		0x0ff8		/* Size of Environment vars */
#define CONFIG_ENV_ADDR		\
	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE)	/* Env*/
#endif

/*-----------------------------------------------------------------------
 * PPC405 GPIO Configuration
 */
#define CONFIG_SYS_4xx_GPIO_TABLE { /*				GPIO	Alternate1		*/	\
{												\
/* GPIO Core 0 */										\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO0	PerBLast    SPI CS	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1	TS1E			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2	TS2E			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3	TS1O			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4	TS2O			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5	TS3			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6	TS4			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7	TS5			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8	TS6			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9	TrcClk			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10	PerCS1			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11	PerCS2			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12	PerCS3			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13	PerCS4			*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO14	PerAddr03   SPI SCLK	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO15	PerAddr04   SPI DI	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO16	PerAddr05   SPI DO	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17	IRQ0	    PCI INTA	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18	IRQ1	    PCI INTB	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19	IRQ2	    PCI INTC	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20	IRQ3	    PCI INTD	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21	IRQ4	    USB		*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22	IRQ5	    EBC		*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO23	IRQ6	    unused	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24	UART0_DCD   UART1	*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25	UART0_DSR		*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26	UART0_RI		*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27	UART0_DTR		*/	\
{ GPIO_BASE, GPIO_IN,  GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28	UART1_Rx    UART0	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29	UART1_Tx		*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO30	RejectPkt0  User LED1	*/	\
{ GPIO_BASE, GPIO_OUT, GPIO_SEL,  GPIO_OUT_NO_CHG }, /* GPIO31	RejectPkt1  User LED2	*/	\
}												\
}

/*
 * Init Memory Controller:
 *
 * BR0/1 and OR0/1 (FLASH)
 */

#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
#define FLASH_BASE1_PRELIM  0xFC000000	/* FLASH bank #1 */

/*-----------------------------------------------------------------------
 * Definitions for initial stack pointer and data area (in data cache)
 */
/* use on chip memory (OCM) for temperary stack until sdram is tested */
#define CONFIG_SYS_TEMP_STACK_OCM        1

/* On Chip Memory location */
#define CONFIG_SYS_OCM_DATA_ADDR	0xF8000000
#define CONFIG_SYS_OCM_DATA_SIZE	0x1000
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM		*/
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM	*/

#define CONFIG_SYS_GBL_DATA_OFFSET    (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET      CONFIG_SYS_GBL_DATA_OFFSET

/*-----------------------------------------------------------------------
 * External Bus Controller (EBC) Setup
 */

/* Memory Bank 0 (Flash/SRAM) initialization */
#define CONFIG_SYS_EBC_PB0AP           0x03815600
#define CONFIG_SYS_EBC_PB0CR           0xFFE3A000  /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */

/* Memory Bank 1 (NVRAM/RTC) initialization */
#define CONFIG_SYS_EBC_PB1AP           0x05815600
#define CONFIG_SYS_EBC_PB1CR           0xFC0BA000  /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */

/* Memory Bank 2 (USB device) initialization */
#define CONFIG_SYS_EBC_PB2AP           0x03016600
#define CONFIG_SYS_EBC_PB2CR           0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */

/* Memory Bank 3 (LCM and D-flip-flop) initialization */
#define CONFIG_SYS_EBC_PB3AP           0x158FF600
#define CONFIG_SYS_EBC_PB3CR           0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */

/* Memory Bank 4 (not install) initialization */
#define CONFIG_SYS_EBC_PB4AP           0x158FF600
#define CONFIG_SYS_EBC_PB4CR           0x5021A000

#define CPLD_REG0_ADDR	0x50100000
#define CPLD_REG1_ADDR	0x50100001

#endif	/* __CONFIG_H */
Commit	Line	Data
d4024bb7 JO	1	/*
	2	* (C) Copyright 2000-2005
	3	* Wolfgang Denk, DENX Software Engineering, wd@denx.de.
	4	*
	5	* (C) Copyright 2005-2007
	6	* Beijing UD Technology Co., Ltd., taihusupport@amcc.com
	7	*
3765b3e7	8	* SPDX-License-Identifier: GPL-2.0+
d4024bb7 JO	9	*/
	10
	11	#ifndef __CONFIG_H
	12	#define __CONFIG_H
	13
	14
	15	#define CONFIG_405EP 1 /* this is a PPC405 CPU */
d4024bb7 JO	16	#define CONFIG_TAIHU 1 /* on a taihu board */
d4024bb7 JO	17
2ae18241 WD	18	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	19
72675dc6 SR	20	/*
	21	* Include common defines/options for all AMCC eval boards
	22	*/
	23	#define CONFIG_HOSTNAME taihu
	24	#include "amcc-common.h"
	25
d4024bb7 JO	26	#define CONFIG_BOARD_EARLY_INIT_F 1 /* call board_early_init_f */
	27
	28	#define CONFIG_SYS_CLK_FREQ 33000000 /* external frequency to pll */
	29
	30	#define CONFIG_NO_SERIAL_EEPROM
	31
	32	/----------------------------------------------------------------------------/
	33	#ifdef CONFIG_NO_SERIAL_EEPROM
	34
	35	/*
	36	!-------------------------------------------------------------------------------
	37	! PLL settings for 333MHz CPU, 111MHz PLB/SDRAM, 55MHz EBC, 33MHz PCI,
	38	! assuming a 33MHz input clock to the 405EP from the C9531.
	39	!-------------------------------------------------------------------------------
	40	*/
	41	#define PLLMR0_333_111_55_37 (PLL_CPUDIV_1 \| PLL_PLBDIV_3 \| \
	42	PLL_OPBDIV_2 \| PLL_EXTBUSDIV_2 \| \
	43	PLL_MALDIV_1 \| PLL_PCIDIV_3)
	44	#define PLLMR1_333_111_55_37 (PLL_FBKDIV_10 \| \
	45	PLL_FWDDIVA_3 \| PLL_FWDDIVB_3 \| \
	46	PLL_TUNE_15_M_40 \| PLL_TUNE_VCO_HI)
	47	#define PLLMR0_333_111_55_111 (PLL_CPUDIV_1 \| PLL_PLBDIV_3 \| \
	48	PLL_OPBDIV_2 \| PLL_EXTBUSDIV_2 \| \
	49	PLL_MALDIV_1 \| PLL_PCIDIV_1)
	50	#define PLLMR1_333_111_55_111 (PLL_FBKDIV_10 \| \
	51	PLL_FWDDIVA_3 \| PLL_FWDDIVB_3 \| \
	52	PLL_TUNE_15_M_40 \| PLL_TUNE_VCO_HI)
	53
	54	#define PLLMR0_DEFAULT PLLMR0_333_111_55_37
	55	#define PLLMR1_DEFAULT PLLMR1_333_111_55_37
	56	#define PLLMR0_DEFAULT_PCI66 PLLMR0_333_111_55_111
	57	#define PLLMR1_DEFAULT_PCI66 PLLMR1_333_111_55_111
	58
	59	#endif
	60	/----------------------------------------------------------------------------/
	61
5a1aceb0	62	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
d4024bb7	63
72675dc6 SR	64	/*
	65	* Default environment variables
	66	*/
	67	#define CONFIG_EXTRA_ENV_SETTINGS \
	68	CONFIG_AMCC_DEF_ENV \
	69	CONFIG_AMCC_DEF_ENV_PPC \
	70	CONFIG_AMCC_DEF_ENV_NOR_UPD \
d4024bb7 JO	71	"kernel_addr=FC000000\0" \
d4024bb7 JO	72	"ramdisk_addr=FC180000\0" \
d4024bb7	73	""
d4024bb7	74
d4024bb7	75	#define CONFIG_PHY_ADDR 0x14 /* PHY address */
a00eccfe	76	#define CONFIG_HAS_ETH0
d4024bb7 JO	77	#define CONFIG_HAS_ETH1
d4024bb7 JO	78	#define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */
d4024bb7 JO	79	#define CONFIG_PHY_RESET 1
d4024bb7 JO	80
3b3bff4c	81	/*
72675dc6	82	* Commands additional to the ones defined in amcc-common.h
3b3bff4c	83	*/
3b3bff4c	84	#define CONFIG_CMD_CACHE
3b3bff4c	85	#define CONFIG_CMD_PCI
3b3bff4c SR	86	#define CONFIG_CMD_SDRAM
3b3bff4c SR	87	#define CONFIG_CMD_SPI
d4024bb7	88
d4024bb7	89	#undef CONFIG_SPD_EEPROM /* use SPD EEPROM for setup */
6d0f6bcf JCPV	90	#define CONFIG_SYS_SDRAM_SIZE_PER_BANK 0x04000000 /* 64MB */
6d0f6bcf JCPV	91	#define CONFIG_SYS_SDRAM_BANKS 2
d4024bb7 JO	92
	93	/*
	94	* SDRAM configuration (please see cpu/ppc/sdram.[ch])
	95	*/
	96	#define CONFIG_SDRAM_BANK0 1 /* init onboard SDRAM bank 0 */
	97	#define CONFIG_SDRAM_BANK1 1 /* init onboard SDRAM bank 1 */
	98
	99	/* SDRAM timings used in datasheet */
6d0f6bcf JCPV	100	#define CONFIG_SYS_SDRAM_CL 3 /* CAS latency */
	101	#define CONFIG_SYS_SDRAM_tRP 20 /* PRECHARGE command period */
	102	#define CONFIG_SYS_SDRAM_tRC 66 /* ACTIVE-to-ACTIVE command period */
	103	#define CONFIG_SYS_SDRAM_tRCD 20 /* ACTIVE-to-READ delay */
	104	#define CONFIG_SYS_SDRAM_tRFC 66 /* Auto refresh period */
d4024bb7	105
d4024bb7	106	/*
6d0f6bcf JCPV	107	* If CONFIG_SYS_EXT_SERIAL_CLOCK, then the UART divisor is 1.
	108	* If CONFIG_SYS_405_UART_ERRATA_59, then UART divisor is 31.
	109	* Otherwise, UART divisor is determined by CPU Clock and CONFIG_SYS_BASE_BAUD value.
d4024bb7 JO	110	* The Linux BASE_BAUD define should match this configuration.
d4024bb7 JO	111	* baseBaud = cpuClock/(uartDivisor*16)
6d0f6bcf	112	* If CONFIG_SYS_405_UART_ERRATA_59 and 200MHz CPU clock,
d4024bb7 JO	113	* set Linux BASE_BAUD to 403200.
d4024bb7 JO	114	*/
550650dd	115	#define CONFIG_CONS_INDEX 2 /* Use UART1 */
6d0f6bcf JCPV	116	#undef CONFIG_SYS_EXT_SERIAL_CLOCK /* external serial clock */
	117	#undef CONFIG_SYS_405_UART_ERRATA_59 /* 405GP/CR Rev. D silicon */
	118	#define CONFIG_SYS_BASE_BAUD 691200
d4024bb7	119
d4024bb7 JO	120	/*-----------------------------------------------------------------------
	121	* I2C stuff
	122	*-----------------------------------------------------------------------
	123	*/
880540de	124	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
d4024bb7	125
880540de	126	#define CONFIG_SYS_I2C_NOPROBES { {0, 0x69} } /* avoid i2c probe hangup (?) */
6d0f6bcf	127	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 6 /* 24C02 requires 5ms delay */
d4024bb7	128
6d0f6bcf JCPV	129	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 /* I2C boot EEPROM (24C02W) */
6d0f6bcf JCPV	130	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1 /* Bytes of address */
d4024bb7 JO	131
	132	#define CONFIG_SOFT_SPI
	133	#define SPI_SCL spi_scl
	134	#define SPI_SDA spi_sda
	135	#define SPI_READ spi_read()
	136	#define SPI_DELAY udelay(2)
	137	#ifndef __ASSEMBLY__
	138	void spi_scl(int);
	139	void spi_sda(int);
	140	unsigned char spi_read(void);
	141	#endif
	142
	143	/* standard dtt sensor configuration */
	144	#define CONFIG_DTT_DS1775 1
	145	#define CONFIG_DTT_SENSORS { 0 }
6d0f6bcf	146	#define CONFIG_SYS_I2C_DTT_ADDR 0x49
d4024bb7 JO	147
	148	/*-----------------------------------------------------------------------
	149	* PCI stuff
	150	*-----------------------------------------------------------------------
	151	*/
	152	#define PCI_HOST_ADAPTER 0 /* configure ar pci adapter */
	153	#define PCI_HOST_FORCE 1 /* configure as pci host */
	154	#define PCI_HOST_AUTO 2 /* detected via arbiter enable */
	155
	156	#define CONFIG_PCI /* include pci support */
842033e6	157	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
d4024bb7 JO	158	#define CONFIG_PCI_HOST PCI_HOST_FORCE /* select pci host function */
	159	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	160	/* resource configuration */
	161	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
	162
6d0f6bcf JCPV	163	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
	164	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
	165	#define CONFIG_SYS_PCI_CLASSCODE 0x0600 /* PCI Class Code: bridge/host */
	166	#define CONFIG_SYS_PCI_PTM1LA 0x00000000 /* point to sdram */
	167	#define CONFIG_SYS_PCI_PTM1MS 0x80000001 /* 2GB, enable hard-wired to 1 */
	168	#define CONFIG_SYS_PCI_PTM1PCI 0x00000000 /* Host: use this pci address */
	169	#define CONFIG_SYS_PCI_PTM2LA 0x00000000 /* disabled */
	170	#define CONFIG_SYS_PCI_PTM2MS 0x00000000 /* disabled */
	171	#define CONFIG_SYS_PCI_PTM2PCI 0x04000000 /* Host: use this pci address */
d4024bb7 JO	172	#define CONFIG_EEPRO100 1
	173
	174	/*-----------------------------------------------------------------------
	175	* Start addresses for the final memory configuration
	176	* (Set up by the startup code)
d4024bb7	177	*/
6d0f6bcf	178	#define CONFIG_SYS_FLASH_BASE 0xFFE00000
d4024bb7 JO	179
	180	/*-----------------------------------------------------------------------
	181	* FLASH organization
	182	*/
6d0f6bcf JCPV	183	#define CONFIG_SYS_MAX_FLASH_BANKS 2 /* max number of memory banks */
6d0f6bcf JCPV	184	#define CONFIG_SYS_MAX_FLASH_SECT 256 /* max number of sectors on one chip */
d4024bb7	185
6d0f6bcf JCPV	186	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
6d0f6bcf JCPV	187	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
d4024bb7	188
6d0f6bcf JCPV	189	#define CONFIG_SYS_FLASH_ADDR0 0x555
	190	#define CONFIG_SYS_FLASH_ADDR1 0x2aa
	191	#define CONFIG_SYS_FLASH_WORD_SIZE unsigned short
d4024bb7	192
5a1aceb0	193	#ifdef CONFIG_ENV_IS_IN_FLASH
0e8d1586	194	#define CONFIG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */
6d0f6bcf	195	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	196	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
d4024bb7 JO	197
d4024bb7 JO	198	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	199	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	200	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
5a1aceb0	201	#endif /* CONFIG_ENV_IS_IN_FLASH */
d4024bb7 JO	202
	203	/*-----------------------------------------------------------------------
	204	* NVRAM organization
	205	*/
6d0f6bcf JCPV	206	#define CONFIG_SYS_NVRAM_BASE_ADDR 0xf0000000 /* NVRAM base address */
6d0f6bcf JCPV	207	#define CONFIG_SYS_NVRAM_SIZE 0x1ff8 /* NVRAM size */
d4024bb7	208
9314cee6	209	#ifdef CONFIG_ENV_IS_IN_NVRAM
0e8d1586 JCPV	210	#define CONFIG_ENV_SIZE 0x0ff8 /* Size of Environment vars */
0e8d1586 JCPV	211	#define CONFIG_ENV_ADDR \
6d0f6bcf	212	(CONFIG_SYS_NVRAM_BASE_ADDR+CONFIG_SYS_NVRAM_SIZE-CONFIG_ENV_SIZE) /* Env*/
d4024bb7 JO	213	#endif
	214
	215	/*-----------------------------------------------------------------------
	216	* PPC405 GPIO Configuration
	217	*/
6d0f6bcf	218	#define CONFIG_SYS_4xx_GPIO_TABLE { /* GPIO Alternate1 */ \
d4024bb7 JO	219	{ \
	220	/* GPIO Core 0 */ \
	221	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO0 PerBLast SPI CS */ \
	222	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO1 TS1E */ \
	223	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO2 TS2E */ \
	224	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO3 TS1O */ \
	225	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO4 TS2O */ \
	226	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO5 TS3 */ \
	227	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO6 TS4 */ \
	228	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO7 TS5 */ \
	229	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO8 TS6 */ \
	230	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO9 TrcClk */ \
	231	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO10 PerCS1 */ \
	232	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO11 PerCS2 */ \
	233	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO12 PerCS3 */ \
	234	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO13 PerCS4 */ \
	235	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO14 PerAddr03 SPI SCLK */ \
	236	{ GPIO_BASE, GPIO_IN, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO15 PerAddr04 SPI DI */ \
	237	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO16 PerAddr05 SPI DO */ \
	238	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO17 IRQ0 PCI INTA */ \
	239	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO18 IRQ1 PCI INTB */ \
	240	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO19 IRQ2 PCI INTC */ \
	241	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO20 IRQ3 PCI INTD */ \
	242	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO21 IRQ4 USB */ \
	243	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO22 IRQ5 EBC */ \
	244	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO23 IRQ6 unused */ \
	245	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO24 UART0_DCD UART1 */ \
	246	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO25 UART0_DSR */ \
	247	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO26 UART0_RI */ \
	248	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO27 UART0_DTR */ \
53677ef1	249	{ GPIO_BASE, GPIO_IN, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO28 UART1_Rx UART0 */ \
d4024bb7 JO	250	{ GPIO_BASE, GPIO_OUT, GPIO_ALT1, GPIO_OUT_NO_CHG }, /* GPIO29 UART1_Tx */ \
	251	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO30 RejectPkt0 User LED1 */ \
	252	{ GPIO_BASE, GPIO_OUT, GPIO_SEL, GPIO_OUT_NO_CHG }, /* GPIO31 RejectPkt1 User LED2 */ \
	253	} \
	254	}
	255
d4024bb7 JO	256	/*
	257	* Init Memory Controller:
	258	*
	259	* BR0/1 and OR0/1 (FLASH)
	260	*/
	261
6d0f6bcf	262	#define FLASH_BASE0_PRELIM CONFIG_SYS_FLASH_BASE /* FLASH bank #0 */
d4024bb7 JO	263	#define FLASH_BASE1_PRELIM 0xFC000000 /* FLASH bank #1 */
	264
	265	/*-----------------------------------------------------------------------
	266	* Definitions for initial stack pointer and data area (in data cache)
	267	*/
	268	/* use on chip memory (OCM) for temperary stack until sdram is tested */
6d0f6bcf	269	#define CONFIG_SYS_TEMP_STACK_OCM 1
d4024bb7 JO	270
d4024bb7 JO	271	/* On Chip Memory location */
6d0f6bcf JCPV	272	#define CONFIG_SYS_OCM_DATA_ADDR 0xF8000000
	273	#define CONFIG_SYS_OCM_DATA_SIZE 0x1000
	274	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_OCM_DATA_ADDR /* inside of SDRAM */
553f0982	275	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_OCM_DATA_SIZE /* Size of used area in RAM */
d4024bb7	276
25ddd1fb	277	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
6d0f6bcf	278	#define CONFIG_SYS_INIT_SP_OFFSET CONFIG_SYS_GBL_DATA_OFFSET
d4024bb7 JO	279
	280	/*-----------------------------------------------------------------------
	281	* External Bus Controller (EBC) Setup
	282	*/
	283
	284	/* Memory Bank 0 (Flash/SRAM) initialization */
6d0f6bcf JCPV	285	#define CONFIG_SYS_EBC_PB0AP 0x03815600
6d0f6bcf JCPV	286	#define CONFIG_SYS_EBC_PB0CR 0xFFE3A000 /* BAS=0xFFE,BS=2MB,BU=R/W,BW=16bit */
d4024bb7 JO	287
d4024bb7 JO	288	/* Memory Bank 1 (NVRAM/RTC) initialization */
6d0f6bcf JCPV	289	#define CONFIG_SYS_EBC_PB1AP 0x05815600
6d0f6bcf JCPV	290	#define CONFIG_SYS_EBC_PB1CR 0xFC0BA000 /* BAS=0xFc0,BS=32MB,BU=R/W,BW=16bit */
d4024bb7 JO	291
d4024bb7 JO	292	/* Memory Bank 2 (USB device) initialization */
6d0f6bcf JCPV	293	#define CONFIG_SYS_EBC_PB2AP 0x03016600
6d0f6bcf JCPV	294	#define CONFIG_SYS_EBC_PB2CR 0x50018000 /* BAS=0x500,BS=1MB,BU=R/W,BW=8bit */
d4024bb7 JO	295
d4024bb7 JO	296	/* Memory Bank 3 (LCM and D-flip-flop) initialization */
6d0f6bcf JCPV	297	#define CONFIG_SYS_EBC_PB3AP 0x158FF600
6d0f6bcf JCPV	298	#define CONFIG_SYS_EBC_PB3CR 0x50118000 /* BAS=0x501,BS=1MB,BU=R/W,BW=8bit */
d4024bb7 JO	299
d4024bb7 JO	300	/* Memory Bank 4 (not install) initialization */
6d0f6bcf JCPV	301	#define CONFIG_SYS_EBC_PB4AP 0x158FF600
6d0f6bcf JCPV	302	#define CONFIG_SYS_EBC_PB4CR 0x5021A000
d4024bb7	303
d4024bb7 JO	304	#define CPLD_REG0_ADDR 0x50100000
d4024bb7 JO	305	#define CPLD_REG1_ADDR 0x50100001
a00eccfe	306
d4024bb7	307	#endif /* __CONFIG_H */