[people/ms/u-boot.git] / include / configs / taishan.h

/*
 * (C) Copyright 2007
 * Stefan Roese, DENX Software Engineering, sr@denx.de.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

/************************************************************************
 * TAISHAN.h - configuration for AMCC 440GX Ref
 ***********************************************************************/

#ifndef __CONFIG_H
#define __CONFIG_H

/*-----------------------------------------------------------------------
 * High Level Configuration Options
 *----------------------------------------------------------------------*/
#define CONFIG_TAISHAN		1	/* Board is taishan		*/
#define CONFIG_440GX		1	/* Specifc GX support		*/
#define CONFIG_440		1	/* ... PPC440 family		*/
#define CONFIG_4xx		1	/* ... PPC4xx family		*/
#define CONFIG_SYS_CLK_FREQ	33333333 /* external freq to pll	*/

#define	CONFIG_SYS_TEXT_BASE	0xFFFC0000

/*
 * Include common defines/options for all AMCC eval boards
 */
#define CONFIG_HOSTNAME		taishan
#define CONFIG_USE_TTY		ttyS1
#include "amcc-common.h"

#define CONFIG_BOARD_EARLY_INIT_F 1	/* Call board_pre_init		*/
#define CONFIG_MISC_INIT_R	1	/* Call misc_init_r		*/

/*-----------------------------------------------------------------------
 * Base addresses -- Note these are effective addresses where the
 * actual resources get mapped (not physical addresses)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_BASE		0xfc000000	/* start of FLASH	*/
#define CONFIG_SYS_PCI_MEMBASE		0x80000000	/* mapped pci memory	*/
#define CONFIG_SYS_ISRAM_BASE		0xc0000000	/* internal SRAM	*/
#define CONFIG_SYS_PCI_BASE		0xd0000000	/* internal PCI regs	*/

#define CONFIG_SYS_EBC0_FLASH_BASE	CONFIG_SYS_FLASH_BASE
#define CONFIG_SYS_EBC1_FPGA_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x01000000)
#define CONFIG_SYS_EBC2_LCM_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x02000000)
#define CONFIG_SYS_EBC3_CONN_BASE	(CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)

#define CONFIG_SYS_GPIO_BASE		(CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)

/*-----------------------------------------------------------------------
 * Initial RAM & stack pointer (placed in internal SRAM)
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_TEMP_STACK_OCM	1
#define CONFIG_SYS_OCM_DATA_ADDR	CONFIG_SYS_ISRAM_BASE
#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_SYS_ISRAM_BASE  /* Initial RAM address	*/
#define CONFIG_SYS_INIT_RAM_SIZE	0x2000		/* Size of used area in RAM*/

#define CONFIG_SYS_GBL_DATA_OFFSET	(CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_INIT_SP_OFFSET	(CONFIG_SYS_GBL_DATA_OFFSET - 0x4)

/*-----------------------------------------------------------------------
 * Serial Port
 *----------------------------------------------------------------------*/
#define CONFIG_CONS_INDEX	2	/* Use UART1			*/
#define CONFIG_SYS_EXT_SERIAL_CLOCK	(1843200 * 6)	/* Ext clk @ 11.059 MHz */

/*-----------------------------------------------------------------------
 * Environment
 *----------------------------------------------------------------------*/
#define CONFIG_ENV_IS_IN_FLASH     1	/* use FLASH for environment vars	*/

/*-----------------------------------------------------------------------
 * FLASH related
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_FLASH_CFI
#define CONFIG_FLASH_CFI_DRIVER
#define CONFIG_SYS_FLASH_EMPTY_INFO		/* print 'E' for empty sector on flinfo */
#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1	/* use buffered writes (20x faster)	*/

#define CONFIG_SYS_FLASH_BANKS_LIST    {CONFIG_SYS_FLASH_BASE}
#define CONFIG_SYS_MAX_FLASH_BANKS     1		    /* number of banks	    */
#define CONFIG_SYS_MAX_FLASH_SECT	1024		    /* sectors per device   */

#undef	CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT	120000	/* Timeout for Flash Erase (in ms)	*/
#define CONFIG_SYS_FLASH_WRITE_TOUT	500	/* Timeout for Flash Write (in ms)	*/

#define CONFIG_ENV_SECT_SIZE	0x40000 /* size of one complete sector	*/
#define CONFIG_ENV_ADDR		(CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
#define	CONFIG_ENV_SIZE		0x4000	/* Total Size of Environment Sector	*/

/* Address and size of Redundant Environment Sector	*/
#define CONFIG_ENV_ADDR_REDUND	(CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
#define CONFIG_ENV_SIZE_REDUND	(CONFIG_ENV_SIZE)

/*-----------------------------------------------------------------------
 * E2PROM bootstrap configure value
 *----------------------------------------------------------------------*/

/*
 * 800/133/66
 * IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
 */

/*
 * 800/160/80
 * IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
 */

/*-----------------------------------------------------------------------
 * DDR SDRAM
 *----------------------------------------------------------------------*/
#undef CONFIG_SPD_EEPROM		/* Don't use SPD EEPROM for setup	*/
#define CONFIG_SDRAM_BANK0	1	/* init onboard DDR SDRAM bank 0	*/
#define	CONFIG_SYS_SDRAM0_TR0		0xC10A401A
#undef CONFIG_SDRAM_ECC			/* enable ECC support			*/

/*-----------------------------------------------------------------------
 * I2C
 *----------------------------------------------------------------------*/
#define CONFIG_SYS_I2C_PPC4XX_SPEED_0		400000

#undef CONFIG_SYS_I2C_MULTI_EEPROMS
#define CONFIG_SYS_I2C_EEPROM_ADDR	0x50
#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10

#define CONFIG_SYS_BOOTSTRAP_IIC_ADDR	0x50

/* I2C SYSMON (LM75, AD7414 is almost compatible)			*/
#define CONFIG_DTT_LM75		1		/* ON Semi's LM75	*/
#define CONFIG_DTT_SENSORS	{0}		/* Sensor addresses	*/
#define CONFIG_SYS_DTT_MAX_TEMP	70
#define CONFIG_SYS_DTT_LOW_TEMP	-30
#define CONFIG_SYS_DTT_HYSTERESIS	3

/*
 * Default environment variables
 */
#define	CONFIG_EXTRA_ENV_SETTINGS					\
	CONFIG_AMCC_DEF_ENV						\
	CONFIG_AMCC_DEF_ENV_POWERPC					\
	CONFIG_AMCC_DEF_ENV_PPC_OLD					\
	CONFIG_AMCC_DEF_ENV_NOR_UPD					\
	"kernel_addr=fc000000\0"					\
	"ramdisk_addr=fc180000\0"					\
	"kozio=bootm 0xffe00000\0"					\
	""

/*-----------------------------------------------------------------------
 * Networking
 *----------------------------------------------------------------------*/
#define CONFIG_EMAC_NR_START	2	/* start with EMAC 2 (skip 0&1)	*/
#define CONFIG_PHY_ADDR		0xff	     /* no phy on EMAC0		*/
#define CONFIG_PHY1_ADDR	0xff	     /* no phy on EMAC1		*/
#define CONFIG_PHY2_ADDR	0x1
#define CONFIG_PHY3_ADDR	0x3
#define CONFIG_ET1011C_PHY	1
#define CONFIG_HAS_ETH0
#define CONFIG_HAS_ETH1
#define CONFIG_HAS_ETH2
#define CONFIG_HAS_ETH3
#define CONFIG_PHY_GIGE		1	/* Include GbE speed/duplex detection */
#define CONFIG_PHY_RESET        1       /* reset phy upon startup         */
#define CONFIG_PHY_RESET_DELAY	1000

/*
 * Commands additional to the ones defined in amcc-common.h
 */
#define CONFIG_CMD_DTT
#define CONFIG_CMD_PCI

/*-----------------------------------------------------------------------
 * PCI stuff
 *-----------------------------------------------------------------------
 */
/* General PCI */
#define CONFIG_PCI			/* include pci support		*/
#define CONFIG_PCI_INDIRECT_BRIDGE	/* indirect PCI bridge support */
#define CONFIG_PCI_PNP			/* do pci plug-and-play		*/
#define CONFIG_EEPRO100       1		/* include PCI EEPRO100		*/
#define CONFIG_PCI_SCAN_SHOW		/* show pci devices on startup	*/
#define CONFIG_SYS_PCI_TARGBASE    0x80000000	/* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */

/* Board-specific PCI */
#define CONFIG_SYS_PCI_TARGET_INIT		/* let board init pci target    */

#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8	/* AMCC */
#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe	/* Whatever */

#endif	/* __CONFIG_H */
Commit	Line	Data
34167a36 SR	1	/*
	2	* (C) Copyright 2007
	3	* Stefan Roese, DENX Software Engineering, sr@denx.de.
	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
34167a36 SR	6	*/
	7
	8	/************************************************************************
	9	* TAISHAN.h - configuration for AMCC 440GX Ref
	10	***********************************************************************/
	11
	12	#ifndef __CONFIG_H
	13	#define __CONFIG_H
	14
	15	/*-----------------------------------------------------------------------
	16	* High Level Configuration Options
	17	----------------------------------------------------------------------/
	18	#define CONFIG_TAISHAN 1 /* Board is taishan */
	19	#define CONFIG_440GX 1 /* Specifc GX support */
efa35cf1	20	#define CONFIG_440 1 /* ... PPC440 family */
34167a36	21	#define CONFIG_4xx 1 /* ... PPC4xx family */
34167a36 SR	22	#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */
34167a36 SR	23
2ae18241 WD	24	#define CONFIG_SYS_TEXT_BASE 0xFFFC0000
2ae18241 WD	25
72675dc6 SR	26	/*
	27	* Include common defines/options for all AMCC eval boards
	28	*/
	29	#define CONFIG_HOSTNAME taishan
	30	#define CONFIG_USE_TTY ttyS1
	31	#include "amcc-common.h"
	32
34167a36 SR	33	#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */
	34	#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */
	35
	36	/*-----------------------------------------------------------------------
	37	* Base addresses -- Note these are effective addresses where the
	38	* actual resources get mapped (not physical addresses)
	39	----------------------------------------------------------------------/
6d0f6bcf JCPV	40	#define CONFIG_SYS_FLASH_BASE 0xfc000000 /* start of FLASH */
6d0f6bcf JCPV	41	#define CONFIG_SYS_PCI_MEMBASE 0x80000000 /* mapped pci memory */
6d0f6bcf JCPV	42	#define CONFIG_SYS_ISRAM_BASE 0xc0000000 /* internal SRAM */
6d0f6bcf JCPV	43	#define CONFIG_SYS_PCI_BASE 0xd0000000 /* internal PCI regs */
34167a36	44
6d0f6bcf JCPV	45	#define CONFIG_SYS_EBC0_FLASH_BASE CONFIG_SYS_FLASH_BASE
	46	#define CONFIG_SYS_EBC1_FPGA_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x01000000)
	47	#define CONFIG_SYS_EBC2_LCM_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x02000000)
	48	#define CONFIG_SYS_EBC3_CONN_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x08000000)
34167a36	49
6d0f6bcf	50	#define CONFIG_SYS_GPIO_BASE (CONFIG_SYS_PERIPHERAL_BASE + 0x00000700)
34167a36 SR	51
	52	/*-----------------------------------------------------------------------
	53	* Initial RAM & stack pointer (placed in internal SRAM)
	54	----------------------------------------------------------------------/
6d0f6bcf JCPV	55	#define CONFIG_SYS_TEMP_STACK_OCM 1
	56	#define CONFIG_SYS_OCM_DATA_ADDR CONFIG_SYS_ISRAM_BASE
	57	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_SYS_ISRAM_BASE /* Initial RAM address */
553f0982	58	#define CONFIG_SYS_INIT_RAM_SIZE 0x2000 /* Size of used area in RAM*/
34167a36	59
25ddd1fb	60	#define CONFIG_SYS_GBL_DATA_OFFSET (CONFIG_SYS_INIT_RAM_SIZE - GENERATED_GBL_DATA_SIZE)
800eb096	61	#define CONFIG_SYS_INIT_SP_OFFSET (CONFIG_SYS_GBL_DATA_OFFSET - 0x4)
34167a36	62
34167a36 SR	63	/*-----------------------------------------------------------------------
	64	* Serial Port
	65	----------------------------------------------------------------------/
550650dd	66	#define CONFIG_CONS_INDEX 2 /* Use UART1 */
6d0f6bcf	67	#define CONFIG_SYS_EXT_SERIAL_CLOCK (1843200 * 6) /* Ext clk @ 11.059 MHz */
34167a36 SR	68
	69	/*-----------------------------------------------------------------------
	70	* Environment
	71	----------------------------------------------------------------------/
5a1aceb0	72	#define CONFIG_ENV_IS_IN_FLASH 1 /* use FLASH for environment vars */
34167a36 SR	73
	74	/*-----------------------------------------------------------------------
	75	* FLASH related
	76	----------------------------------------------------------------------/
6d0f6bcf	77	#define CONFIG_SYS_FLASH_CFI
00b1883a	78	#define CONFIG_FLASH_CFI_DRIVER
6d0f6bcf JCPV	79	#define CONFIG_SYS_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */
6d0f6bcf JCPV	80	#define CONFIG_SYS_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */
34167a36	81
6d0f6bcf JCPV	82	#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE}
	83	#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* number of banks */
	84	#define CONFIG_SYS_MAX_FLASH_SECT 1024 /* sectors per device */
34167a36	85
6d0f6bcf JCPV	86	#undef CONFIG_SYS_FLASH_CHECKSUM
	87	#define CONFIG_SYS_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */
	88	#define CONFIG_SYS_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */
34167a36	89
0e8d1586	90	#define CONFIG_ENV_SECT_SIZE 0x40000 /* size of one complete sector */
6d0f6bcf	91	#define CONFIG_ENV_ADDR (CONFIG_SYS_MONITOR_BASE-CONFIG_ENV_SECT_SIZE)
0e8d1586	92	#define CONFIG_ENV_SIZE 0x4000 /* Total Size of Environment Sector */
34167a36 SR	93
34167a36 SR	94	/* Address and size of Redundant Environment Sector */
0e8d1586 JCPV	95	#define CONFIG_ENV_ADDR_REDUND (CONFIG_ENV_ADDR-CONFIG_ENV_SECT_SIZE)
0e8d1586 JCPV	96	#define CONFIG_ENV_SIZE_REDUND (CONFIG_ENV_SIZE)
34167a36 SR	97
	98	/*-----------------------------------------------------------------------
	99	* E2PROM bootstrap configure value
	100	----------------------------------------------------------------------/
	101
	102	/*
	103	* 800/133/66
	104	* IIC 0~15: 86 78 11 6a 61 A7 04 62 00 00 00 00 00 00 00 00
	105	*/
	106
	107	/*
	108	* 800/160/80
	109	* IIC 0~15: 86 78 c1 a6 09 67 04 63 00 00 00 00 00 00 00 00
	110	*/
	111
	112	/*-----------------------------------------------------------------------
	113	* DDR SDRAM
	114	----------------------------------------------------------------------/
	115	#undef CONFIG_SPD_EEPROM /* Don't use SPD EEPROM for setup */
	116	#define CONFIG_SDRAM_BANK0 1 /* init onboard DDR SDRAM bank 0 */
6d0f6bcf	117	#define CONFIG_SYS_SDRAM0_TR0 0xC10A401A
34167a36 SR	118	#undef CONFIG_SDRAM_ECC /* enable ECC support */
	119
	120	/*-----------------------------------------------------------------------
	121	* I2C
	122	----------------------------------------------------------------------/
880540de	123	#define CONFIG_SYS_I2C_PPC4XX_SPEED_0 400000
34167a36	124
6d0f6bcf JCPV	125	#undef CONFIG_SYS_I2C_MULTI_EEPROMS
	126	#define CONFIG_SYS_I2C_EEPROM_ADDR 0x50
	127	#define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 1
	128	#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 3
	129	#define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
34167a36	130
6d0f6bcf	131	#define CONFIG_SYS_BOOTSTRAP_IIC_ADDR 0x50
34167a36 SR	132
	133	/* I2C SYSMON (LM75, AD7414 is almost compatible) */
	134	#define CONFIG_DTT_LM75 1 /* ON Semi's LM75 */
	135	#define CONFIG_DTT_SENSORS {0} /* Sensor addresses */
6d0f6bcf JCPV	136	#define CONFIG_SYS_DTT_MAX_TEMP 70
	137	#define CONFIG_SYS_DTT_LOW_TEMP -30
	138	#define CONFIG_SYS_DTT_HYSTERESIS 3
34167a36	139
72675dc6 SR	140	/*
	141	* Default environment variables
	142	*/
34167a36	143	#define CONFIG_EXTRA_ENV_SETTINGS \
72675dc6 SR	144	CONFIG_AMCC_DEF_ENV \
	145	CONFIG_AMCC_DEF_ENV_POWERPC \
	146	CONFIG_AMCC_DEF_ENV_PPC_OLD \
	147	CONFIG_AMCC_DEF_ENV_NOR_UPD \
34167a36 SR	148	"kernel_addr=fc000000\0" \
34167a36 SR	149	"ramdisk_addr=fc180000\0" \
34167a36 SR	150	"kozio=bootm 0xffe00000\0" \
34167a36 SR	151	""
34167a36 SR	152
	153	/*-----------------------------------------------------------------------
	154	* Networking
	155	----------------------------------------------------------------------/
	156	#define CONFIG_EMAC_NR_START 2 /* start with EMAC 2 (skip 0&1) */
1636d1c8 WD	157	#define CONFIG_PHY_ADDR 0xff /* no phy on EMAC0 */
1636d1c8 WD	158	#define CONFIG_PHY1_ADDR 0xff /* no phy on EMAC1 */
34167a36 SR	159	#define CONFIG_PHY2_ADDR 0x1
	160	#define CONFIG_PHY3_ADDR 0x3
	161	#define CONFIG_ET1011C_PHY 1
	162	#define CONFIG_HAS_ETH0
	163	#define CONFIG_HAS_ETH1
	164	#define CONFIG_HAS_ETH2
	165	#define CONFIG_HAS_ETH3
	166	#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */
	167	#define CONFIG_PHY_RESET 1 /* reset phy upon startup */
	168	#define CONFIG_PHY_RESET_DELAY 1000
079a136c	169
6c18eb98	170	/*
72675dc6	171	* Commands additional to the ones defined in amcc-common.h
6c18eb98	172	*/
6c18eb98	173	#define CONFIG_CMD_DTT
6c18eb98	174	#define CONFIG_CMD_PCI
34167a36 SR	175
	176	/*-----------------------------------------------------------------------
	177	* PCI stuff
	178	*-----------------------------------------------------------------------
	179	*/
	180	/* General PCI */
	181	#define CONFIG_PCI /* include pci support */
842033e6	182	#define CONFIG_PCI_INDIRECT_BRIDGE /* indirect PCI bridge support */
34167a36 SR	183	#define CONFIG_PCI_PNP /* do pci plug-and-play */
	184	#define CONFIG_EEPRO100 1 /* include PCI EEPRO100 */
	185	#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */
6d0f6bcf	186	#define CONFIG_SYS_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CONFIG_SYS_PCI_MEMBASE */
34167a36 SR	187
34167a36 SR	188	/* Board-specific PCI */
6d0f6bcf	189	#define CONFIG_SYS_PCI_TARGET_INIT /* let board init pci target */
34167a36	190
6d0f6bcf JCPV	191	#define CONFIG_SYS_PCI_SUBSYS_VENDORID 0x10e8 /* AMCC */
6d0f6bcf JCPV	192	#define CONFIG_SYS_PCI_SUBSYS_DEVICEID 0xcafe /* Whatever */
34167a36	193
34167a36	194	#endif /* __CONFIG_H */