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550e3756 TU |
1 | /* |
2 | * Configuration settings for the TechNexion TAO-3530 SOM | |
3 | * equipped on Thunder baseboard. | |
4 | * | |
5 | * Edward Lin <linuxfae@technexion.com> | |
6 | * Tapani Utriainen <linuxfae@technexion.com> | |
7 | * | |
a9f52490 SR |
8 | * Copyright (C) 2013 Stefan Roese <sr@denx.de> |
9 | * | |
550e3756 TU |
10 | * SPDX-License-Identifier: GPL-2.0+ |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_H | |
14 | #define __CONFIG_H | |
15 | ||
16 | /* | |
17 | * High Level Configuration Options | |
18 | */ | |
550e3756 | 19 | |
550e3756 | 20 | #include <asm/arch/cpu.h> /* get chip and board defs */ |
987ec585 | 21 | #include <asm/arch/omap.h> |
550e3756 | 22 | |
550e3756 TU |
23 | /* Clock Defines */ |
24 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
25 | #define V_SCLK (V_OSCK >> 1) | |
26 | ||
27 | #define CONFIG_MISC_INIT_R | |
28 | ||
550e3756 TU |
29 | #define CONFIG_CMDLINE_TAG |
30 | #define CONFIG_SETUP_MEMORY_TAGS | |
31 | #define CONFIG_INITRD_TAG | |
32 | #define CONFIG_REVISION_TAG | |
33 | ||
34 | /* | |
35 | * Size of malloc() pool | |
36 | */ | |
37 | #define CONFIG_SYS_MALLOC_LEN (4 << 20) | |
38 | #define CONFIG_ENV_SIZE (128 << 10) /* 128 KiB sector */ | |
39 | ||
40 | /* | |
41 | * Hardware drivers | |
42 | */ | |
43 | ||
44 | /* | |
45 | * NS16550 Configuration | |
46 | */ | |
47 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
48 | ||
550e3756 TU |
49 | #define CONFIG_SYS_NS16550_SERIAL |
50 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
51 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK | |
52 | ||
53 | /* | |
54 | * select serial console configuration | |
55 | */ | |
56 | #define CONFIG_CONS_INDEX 3 | |
57 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 | |
58 | ||
59 | /* allow to overwrite serial and ethaddr */ | |
60 | #define CONFIG_ENV_OVERWRITE | |
550e3756 TU |
61 | |
62 | /* commands to include */ | |
550e3756 | 63 | #define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ |
550e3756 | 64 | |
550e3756 | 65 | #define CONFIG_SYS_I2C |
550e3756 TU |
66 | #define CONFIG_I2C_MULTI_BUS |
67 | ||
68 | /* | |
69 | * TWL4030 | |
70 | */ | |
550e3756 TU |
71 | #define CONFIG_TWL4030_LED |
72 | ||
73 | /* | |
74 | * Board NAND Info. | |
75 | */ | |
550e3756 TU |
76 | #define CONFIG_SYS_NAND_ADDR NAND_BASE /* physical address */ |
77 | /* to access nand */ | |
78 | #define CONFIG_SYS_NAND_BASE NAND_BASE /* physical address */ | |
79 | /* to access nand at */ | |
80 | /* CS0 */ | |
550e3756 TU |
81 | |
82 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 /* Max number of NAND */ | |
83 | /* devices */ | |
84 | /* Environment information */ | |
550e3756 TU |
85 | |
86 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
87 | "loadaddr=0x82000000\0" \ | |
88 | "console=ttyO2,115200n8\0" \ | |
89 | "mpurate=600\0" \ | |
90 | "dvi_mode=omapfb.mode=dvi:1280x720-24@60\0" \ | |
91 | "tv_mode=omapfb.mode=tv:ntsc\0" \ | |
92 | "video_mode=omapdss.def_disp=lcd vram=6M omapfb.vram=0:2M,1:2M,2:2M\0" \ | |
93 | "lcd_mode=omapfb.mode=lcd:800x480@60 \0" \ | |
94 | "extra_options= \0" \ | |
550e3756 TU |
95 | "mmcdev=0\0" \ |
96 | "mmcroot=/dev/mmcblk0p2 rw\0" \ | |
97 | "mmcrootfstype=ext3 rootwait\0" \ | |
98 | "nandroot=ubi0:rootfs ubi.mtd=4\0" \ | |
99 | "nandrootfstype=ubifs\0" \ | |
100 | "mmcargs=setenv bootargs console=${console} " \ | |
550e3756 TU |
101 | "mpurate=${mpurate} " \ |
102 | "${video_mode} " \ | |
103 | "root=${mmcroot} " \ | |
104 | "rootfstype=${mmcrootfstype} " \ | |
105 | "${extra_options}\0" \ | |
106 | "nandargs=setenv bootargs console=${console} " \ | |
550e3756 TU |
107 | "mpurate=${mpurate} " \ |
108 | "${video_mode} " \ | |
109 | "${network_setting} " \ | |
110 | "root=${nandroot} " \ | |
111 | "rootfstype=${nandrootfstype} "\ | |
112 | "${extra_options}\0" \ | |
113 | "loadbootscript=fatload mmc ${mmcdev} ${loadaddr} boot.scr\0" \ | |
114 | "bootscript=echo Running bootscript from mmc ...; " \ | |
115 | "source ${loadaddr}\0" \ | |
116 | "loaduimage=fatload mmc ${mmcdev} ${loadaddr} uImage\0" \ | |
117 | "mmcboot=echo Booting from mmc ...; " \ | |
118 | "run mmcargs; " \ | |
119 | "bootm ${loadaddr}\0" \ | |
120 | "nandboot=echo Booting from nand ...; " \ | |
121 | "run nandargs; " \ | |
122 | "nand read ${loadaddr} 280000 400000; " \ | |
123 | "bootm ${loadaddr}\0" \ | |
124 | ||
125 | #define CONFIG_BOOTCOMMAND \ | |
126 | "if mmc rescan ${mmcdev}; then " \ | |
127 | "if run loadbootscript; then " \ | |
128 | "run bootscript; " \ | |
129 | "else " \ | |
130 | "if run loaduimage; then " \ | |
131 | "run mmcboot; " \ | |
132 | "else run nandboot; " \ | |
133 | "fi; " \ | |
134 | "fi; " \ | |
135 | "else run nandboot; fi" | |
136 | ||
137 | /* | |
138 | * Miscellaneous configurable options | |
139 | */ | |
140 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ | |
550e3756 TU |
141 | |
142 | /* turn on command-line edit/hist/auto */ | |
143 | #define CONFIG_CMDLINE_EDITING | |
550e3756 TU |
144 | #define CONFIG_AUTO_COMPLETE |
145 | ||
550e3756 TU |
146 | #define CONFIG_SYS_ALT_MEMTEST 1 |
147 | #define CONFIG_SYS_MEMTEST_START (0x82000000) /* memtest */ | |
148 | /* defaults */ | |
149 | #define CONFIG_SYS_MEMTEST_END (0x83FFFFFF) /* 64MB */ | |
150 | #define CONFIG_SYS_MEMTEST_SCRATCH (0x81000000) /* dummy address */ | |
151 | ||
152 | #define CONFIG_SYS_LOAD_ADDR (OMAP34XX_SDRC_CS0) /* default */ | |
153 | /* load address */ | |
550e3756 TU |
154 | |
155 | /* | |
156 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
157 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
158 | * This rate is divided by a local divisor. | |
159 | */ | |
160 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
161 | #define CONFIG_SYS_PTV 2 /* Divisor: 2^(PTV+1) => 8 */ | |
162 | ||
550e3756 TU |
163 | /* |
164 | * Physical Memory Map | |
165 | */ | |
166 | #define CONFIG_NR_DRAM_BANKS 2 /* CS1 may or may not be populated */ | |
167 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
168 | #define PHYS_SDRAM_1_SIZE (32 << 20) /* at least 32 MiB */ | |
169 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
170 | ||
171 | /* | |
172 | * FLASH and environment organization | |
173 | */ | |
174 | ||
175 | /* **** PISMO SUPPORT *** */ | |
550e3756 | 176 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */ |
222a3113 | 177 | #define CONFIG_SYS_FLASH_BASE NAND_BASE |
550e3756 TU |
178 | |
179 | /* Monitor at start of flash */ | |
180 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE | |
181 | #define CONFIG_SYS_ONENAND_BASE ONENAND_MAP | |
182 | ||
550e3756 | 183 | #define ONENAND_ENV_OFFSET 0x260000 /* environment starts here */ |
550e3756 TU |
184 | |
185 | #define CONFIG_SYS_ENV_SECT_SIZE (128 << 10) | |
7672d9d5 | 186 | #define CONFIG_ENV_OFFSET 0x260000 |
550e3756 TU |
187 | #define CONFIG_ENV_ADDR CONFIG_ENV_OFFSET |
188 | ||
189 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 | |
190 | #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 | |
191 | #define CONFIG_SYS_INIT_RAM_SIZE 0x800 | |
192 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
193 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
194 | GENERATED_GBL_DATA_SIZE) | |
195 | ||
550e3756 TU |
196 | /* |
197 | * USB | |
198 | * | |
199 | * Currently only EHCI is enabled, the MUSB OTG controller | |
200 | * is not enabled. | |
201 | */ | |
202 | ||
203 | /* USB EHCI */ | |
550e3756 TU |
204 | #define CONFIG_OMAP_EHCI_PHY1_RESET_GPIO 162 |
205 | ||
a9f52490 | 206 | /* Defines for SPL */ |
a9f52490 | 207 | |
e2ccdf89 | 208 | #define CONFIG_SYS_MMCSD_FS_BOOT_PARTITION 1 |
205b4f33 | 209 | #define CONFIG_SPL_FS_LOAD_PAYLOAD_NAME "u-boot.img" |
a9f52490 | 210 | |
a9f52490 SR |
211 | #define CONFIG_SPL_NAND_BASE |
212 | #define CONFIG_SPL_NAND_DRIVERS | |
213 | #define CONFIG_SPL_NAND_ECC | |
a9f52490 SR |
214 | |
215 | /* NAND boot config */ | |
216 | #define CONFIG_SYS_NAND_5_ADDR_CYCLE | |
217 | #define CONFIG_SYS_NAND_PAGE_COUNT 64 | |
218 | #define CONFIG_SYS_NAND_PAGE_SIZE 2048 | |
219 | #define CONFIG_SYS_NAND_OOBSIZE 64 | |
220 | #define CONFIG_SYS_NAND_BLOCK_SIZE (128 * 1024) | |
221 | #define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS | |
222 | /* | |
223 | * Use the ECC/OOB layout from omap_gpmc.h that matches your chip: | |
224 | * SP vs LP, 8bit vs 16bit: GPMC_NAND_HW_ECC_LAYOUT | |
225 | */ | |
226 | #define CONFIG_SYS_NAND_ECCPOS { 2, 3, 4, 5, 6, 7, 8, 9, \ | |
227 | 10, 11, 12, 13 } | |
228 | #define CONFIG_SYS_NAND_ECCSIZE 512 | |
229 | #define CONFIG_SYS_NAND_ECCBYTES 3 | |
230 | #define CONFIG_NAND_OMAP_ECCSCHEME OMAP_ECC_HAM1_CODE_HW | |
231 | ||
232 | #define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE | |
233 | #define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 | |
234 | ||
235 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
fa2f81b0 TR |
236 | #define CONFIG_SPL_MAX_SIZE (SRAM_SCRATCH_SPACE_ADDR - \ |
237 | CONFIG_SPL_TEXT_BASE) | |
a9f52490 SR |
238 | |
239 | /* | |
240 | * Use 0x80008000 as TEXT_BASE here for compatibility reasons with the | |
241 | * older x-loader implementations. And move the BSS area so that it | |
242 | * doesn't overlap with TEXT_BASE. | |
243 | */ | |
a9f52490 SR |
244 | #define CONFIG_SPL_BSS_START_ADDR 0x80100000 |
245 | #define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ | |
246 | ||
247 | #define CONFIG_SYS_SPL_MALLOC_START 0x80208000 | |
248 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 | |
249 | ||
550e3756 | 250 | #endif /* __CONFIG_H */ |