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f4863a7a WD |
1 | /* |
2 | * (C) Copyright 2003 | |
3 | * Masami Komiya <mkomiya@sonare.it> | |
4 | * | |
1a459660 | 5 | * SPDX-License-Identifier: GPL-2.0+ |
f4863a7a WD |
6 | */ |
7 | ||
8 | /* | |
9 | * Config header file for TANBAC TB0229 board using an VR4131 CPU module | |
10 | */ | |
11 | ||
12 | #ifndef __CONFIG_H | |
13 | #define __CONFIG_H | |
14 | ||
15 | #define CONFIG_MIPS32 1 /* MIPS 4Kc CPU core */ | |
16 | #define CONFIG_TB0229 1 /* on a TB0229 Board */ | |
17 | ||
18 | #ifndef CPU_CLOCK_RATE | |
19 | #define CPU_CLOCK_RATE 200000000 /* 200 MHz clock for the MIPS core */ | |
20 | #endif | |
21 | #define CPU_TCLOCK_RATE 16588800 /* 16.5888 MHz for TClock */ | |
22 | ||
23 | #define CONFIG_CONS_INDEX 1 | |
24 | #define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ | |
25 | ||
26 | #define CONFIG_BAUDRATE 115200 | |
27 | ||
f4863a7a WD |
28 | #define CONFIG_TIMESTAMP /* Print image info with timestamp */ |
29 | ||
30 | #define CONFIG_PREBOOT "echo;" \ | |
32bf3d14 WD |
31 | "echo Type \\\"boot\\\" for the network boot using DHCP, TFTP and NFS;" \ |
32 | "echo Type \\\"run netboot_initrd\\\" for the network boot with initrd;" \ | |
33 | "echo Type \\\"run flash_nfs\\\" to mount root filesystem over NFS;" \ | |
34 | "echo Type \\\"run flash_local\\\" to mount local root filesystem;" \ | |
f4863a7a WD |
35 | "echo" |
36 | ||
37 | #undef CONFIG_BOOTARGS | |
38 | ||
39 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
40 | "netboot=dhcp;tftp;run netargs; bootm\0" \ | |
41 | "nfsargs=setenv bootargs root=/dev/nfs ip=dhcp\0" \ | |
42 | "localargs=setenv bootargs root=1F02 ip=dhcp\0" \ | |
fe126d8b WD |
43 | "addmisc=setenv bootargs ${bootargs} " \ |
44 | "console=ttyS0,${baudrate} " \ | |
f4863a7a WD |
45 | "read-only=readonly\0" \ |
46 | "netargs=run nfsargs addmisc\0" \ | |
47 | "flash_nfs=run nfsargs addmisc;" \ | |
fe126d8b | 48 | "bootm ${kernel_addr}\0" \ |
f4863a7a | 49 | "flash_local=run localargs addmisc;" \ |
fe126d8b | 50 | "bootm ${kernel_addr}\0" \ |
f4863a7a WD |
51 | "netboot_initrd=dhcp;tftp;tftp 80600000 initrd;" \ |
52 | "setenv bootargs root=/dev/ram ramdisk_size=8192 ip=dhcp;"\ | |
53 | "run addmisc;" \ | |
54 | "bootm 80400000 80600000\0" \ | |
55 | "rootpath=/export/miniroot-mipsel\0" \ | |
56 | "autoload=no\0" \ | |
57 | "kernel_addr=BFC60000\0" \ | |
58 | "ramdisk_addr=B0100000\0" \ | |
59 | "u-boot=u-boot.bin\0" \ | |
60 | "bootfile=uImage\0" \ | |
fe126d8b WD |
61 | "load=dhcp;tftp 80400000 ${u-boot}\0" \ |
62 | "load_kernel=dhcp;tftp 80400000 ${bootfile}\0" \ | |
f4863a7a WD |
63 | "update_uboot=run load;" \ |
64 | "protect off BFC00000 BFC3FFFF;" \ | |
65 | "erase BFC00000 BFC3FFFF;" \ | |
fe126d8b | 66 | "cp.b 80400000 BFC00000 ${filesize}\0" \ |
f4863a7a WD |
67 | "update_kernel=run load_kernel;" \ |
68 | "erase BFC60000 BFD5FFFF;" \ | |
fe126d8b | 69 | "cp.b 80400000 BFC60000 ${filesize}\0" \ |
f4863a7a WD |
70 | "initenv=erase bfc40000 bfc5ffff\0" \ |
71 | "" | |
cd37d9e6 | 72 | /*#define CONFIG_BOOTCOMMAND "run flash_local" */ |
f4863a7a WD |
73 | #define CONFIG_BOOTCOMMAND "run netboot" |
74 | ||
6c18eb98 | 75 | |
079a136c JL |
76 | /* |
77 | * BOOTP options | |
78 | */ | |
79 | #define CONFIG_BOOTP_BOOTFILESIZE | |
80 | #define CONFIG_BOOTP_BOOTPATH | |
81 | #define CONFIG_BOOTP_GATEWAY | |
82 | #define CONFIG_BOOTP_HOSTNAME | |
83 | ||
84 | ||
6c18eb98 JL |
85 | /* |
86 | * Command line configuration. | |
87 | */ | |
88 | #include <config_cmd_default.h> | |
89 | ||
90 | #define CONFIG_CMD_ASKENV | |
91 | #define CONFIG_CMD_DHCP | |
92 | #define CONFIG_CMD_PING | |
93 | #define CONFIG_CMD_PCI | |
94 | #define CONFIG_CMD_ELF | |
95 | ||
f4863a7a WD |
96 | |
97 | /* | |
98 | * Miscellaneous configurable options | |
99 | */ | |
6d0f6bcf JCPV |
100 | #define CONFIG_SYS_LONGHELP /* undef to save memory */ |
101 | #define CONFIG_SYS_PROMPT "# " /* Monitor Command Prompt */ | |
102 | #define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ | |
103 | #define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ | |
104 | #define CONFIG_SYS_MAXARGS 16 /* max number of command args*/ | |
f4863a7a | 105 | |
6d0f6bcf | 106 | #define CONFIG_SYS_MALLOC_LEN 128*1024 |
f4863a7a | 107 | |
6d0f6bcf | 108 | #define CONFIG_SYS_BOOTPARAMS_LEN 128*1024 |
f4863a7a | 109 | |
6d0f6bcf | 110 | #define CONFIG_SYS_MIPS_TIMER_FREQ (CPU_TCLOCK_RATE/4) |
a55d4817 | 111 | |
6d0f6bcf | 112 | #define CONFIG_SYS_HZ 1000 |
f4863a7a | 113 | |
6d0f6bcf | 114 | #define CONFIG_SYS_SDRAM_BASE 0x80000000 |
f4863a7a | 115 | |
6d0f6bcf | 116 | #define CONFIG_SYS_LOAD_ADDR 0x80400000 /* default load address */ |
f4863a7a | 117 | |
6d0f6bcf JCPV |
118 | #define CONFIG_SYS_MEMTEST_START 0x80000000 |
119 | #define CONFIG_SYS_MEMTEST_END 0x80800000 | |
f4863a7a WD |
120 | |
121 | /*----------------------------------------------------------------------- | |
122 | * FLASH and environment organization | |
123 | */ | |
6d0f6bcf JCPV |
124 | #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ |
125 | #define CONFIG_SYS_MAX_FLASH_SECT (128) /* max number of sectors on one chip */ | |
f4863a7a WD |
126 | |
127 | #define PHYS_FLASH_1 0xbfc00000 /* Flash Bank #1 */ | |
128 | ||
129 | /* The following #defines are needed to get flash environment right */ | |
14d0a02a | 130 | #define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_TEXT_BASE |
6d0f6bcf | 131 | #define CONFIG_SYS_MONITOR_LEN (192 << 10) |
f4863a7a | 132 | |
6d0f6bcf | 133 | #define CONFIG_SYS_INIT_SP_OFFSET 0x400000 |
f4863a7a | 134 | |
6d0f6bcf | 135 | #define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 |
f4863a7a WD |
136 | |
137 | /* timeout values are in ticks */ | |
6d0f6bcf JCPV |
138 | #define CONFIG_SYS_FLASH_ERASE_TOUT (20 * CONFIG_SYS_HZ) /* Timeout for Flash Erase */ |
139 | #define CONFIG_SYS_FLASH_WRITE_TOUT (2 * CONFIG_SYS_HZ) /* Timeout for Flash Write */ | |
f4863a7a | 140 | |
5a1aceb0 | 141 | #define CONFIG_ENV_IS_IN_FLASH 1 |
f4863a7a WD |
142 | |
143 | /* Address and size of Primary Environment Sector */ | |
0e8d1586 JCPV |
144 | #define CONFIG_ENV_ADDR 0xBFC40000 |
145 | #define CONFIG_ENV_SIZE 0x20000 | |
f4863a7a | 146 | |
6d0f6bcf | 147 | #define CONFIG_SYS_DIRECT_FLASH_TFTP |
f4863a7a WD |
148 | |
149 | #define CONFIG_NR_DRAM_BANKS 1 | |
150 | ||
151 | /*----------------------------------------------------------------------- | |
152 | * Cache Configuration | |
153 | */ | |
6d0f6bcf JCPV |
154 | #define CONFIG_SYS_DCACHE_SIZE 16384 |
155 | #define CONFIG_SYS_ICACHE_SIZE 16384 | |
156 | #define CONFIG_SYS_CACHELINE_SIZE 16 | |
f4863a7a WD |
157 | |
158 | /*----------------------------------------------------------------------- | |
159 | * Serial Configuration | |
160 | */ | |
6d0f6bcf JCPV |
161 | #define CONFIG_SYS_NS16550 |
162 | #define CONFIG_SYS_NS16550_SERIAL | |
163 | #define CONFIG_SYS_NS16550_REG_SIZE 1 | |
164 | #define CONFIG_SYS_NS16550_CLK 18432000 | |
165 | #define CONFIG_SYS_NS16550_COM1 0xaf000800 | |
f4863a7a WD |
166 | |
167 | /*----------------------------------------------------------------------- | |
168 | * PCI stuff | |
169 | */ | |
170 | #define CONFIG_PCI | |
171 | #define CONFIG_PCI_PNP | |
f4863a7a | 172 | #define CONFIG_EEPRO100 |
6d0f6bcf | 173 | #define CONFIG_SYS_RX_ETH_BUFFER 8 /* use 8 rx buffer on eepro100 */ |
f4863a7a WD |
174 | |
175 | #define CONFIG_RTL8139 | |
176 | ||
177 | #endif /* __CONFIG_H */ |