projects / thirdparty / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
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2 | /* |
| 3 | * (C) Copyright 2010-2012 | |
| 4 | * NVIDIA Corporation <www.nvidia.com> | |
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5 | */ |
| 6 | ||
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7 | #ifndef _TEGRA_COMMON_H_ |
| 8 | #define _TEGRA_COMMON_H_ | |
| 1ace4022 | 9 | #include <linux/sizes.h> |
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10 | #include <linux/stringify.h> |
| 11 | ||
| 12 | /* | |
| 13 | * High Level Configuration Options | |
| 14 | */ | |
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15 | #define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */ |
| 16 | ||
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17 | #include <asm/arch/tegra.h> /* get chip and board defs */ |
| 18 | ||
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19 | /* Use the Tegra US timer on ARMv7, but the architected timer on ARMv8. */ |
| 20 | #ifndef CONFIG_ARM64 | |
| 31df9893 RH |
21 | #define CONFIG_SYS_TIMER_RATE 1000000 |
| 22 | #define CONFIG_SYS_TIMER_COUNTER NV_PA_TMRUS_BASE | |
| f41f0a19 | 23 | #endif |
| 31df9893 | 24 | |
| f01b631f | 25 | #define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ |
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26 | |
| 27 | /* Environment */ | |
| f01b631f | 28 | |
| f01b631f | 29 | /* |
| bfcf46db | 30 | * NS16550 Configuration |
| f01b631f | 31 | */ |
| 1874626b | 32 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
| f01b631f | 33 | |
| f175603f SW |
34 | /* |
| 35 | * Common HW configuration. | |
| 36 | * If this varies between SoCs later, move to tegraNN-common.h | |
| 37 | * Note: This is number of devices, not max device ID. | |
| 38 | */ | |
| 39 | #define CONFIG_SYS_MMC_MAX_DEVICE 4 | |
| 40 | ||
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41 | /* allow to overwrite serial and ethaddr */ |
| 42 | #define CONFIG_ENV_OVERWRITE | |
| f01b631f | 43 | |
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44 | /* |
| 45 | * Increasing the size of the IO buffer as default nfsargs size is more | |
| 46 | * than 256 and so it is not possible to edit it | |
| 47 | */ | |
| 64a4fe74 | 48 | #define CONFIG_SYS_CBSIZE (1024 * 2) /* Console I/O Buffer Size */ |
| f01b631f | 49 | /* Print Buffer Size */ |
| 64a4fe74 BW |
50 | #define CONFIG_SYS_MAXARGS 64 /* max number of command args */ |
| 51 | ||
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52 | /* Boot Argument Buffer Size */ |
| 53 | #define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE) | |
| 54 | ||
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55 | /*----------------------------------------------------------------------- |
| 56 | * Physical Memory Map | |
| 57 | */ | |
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58 | #define PHYS_SDRAM_1 NV_PA_SDRC_CS0 |
| 59 | #define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */ | |
| 60 | ||
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61 | #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 |
| 62 | ||
| 63 | #define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */ | |
| 64 | ||
| f097532d | 65 | #ifndef CONFIG_ARM64 |
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66 | #define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE |
| 67 | #define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN | |
| 68 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \ | |
| 69 | CONFIG_SYS_INIT_RAM_SIZE - \ | |
| 70 | GENERATED_GBL_DATA_SIZE) | |
| f097532d | 71 | #endif |
| f01b631f | 72 | |
| 0d1bd150 | 73 | #ifndef CONFIG_ARM64 |
| f01b631f | 74 | /* Defines for SPL */ |
| 6ebc3461 | 75 | #define CONFIG_SPL_MAX_FOOTPRINT (CONFIG_SYS_TEXT_BASE - \ |
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76 | CONFIG_SPL_TEXT_BASE) |
| 77 | #define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000 | |
| 0d1bd150 | 78 | #endif |
| f01b631f | 79 | |
| f01b631f | 80 | #endif /* _TEGRA_COMMON_H_ */ |