projects / people / ms / u-boot.git / blame
| Commit | Line | Data |
|---|---|---|
| 07067145 TW |
1 | /* |
| 2 | * Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved. | |
| 3 | * | |
| 4 | * This program is free software; you can redistribute it and/or modify it | |
| 5 | * under the terms and conditions of the GNU General Public License, | |
| 6 | * version 2, as published by the Free Software Foundation. | |
| 7 | * | |
| 8 | * This program is distributed in the hope it will be useful, but WITHOUT | |
| 9 | * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or | |
| 10 | * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for | |
| 11 | * more details. | |
| 12 | * | |
| 13 | * You should have received a copy of the GNU General Public License | |
| 14 | * along with this program. If not, see <http://www.gnu.org/licenses/>. | |
| 15 | */ | |
| 16 | ||
| 17 | #ifndef _TEGRA114_COMMON_H_ | |
| 18 | #define _TEGRA114_COMMON_H_ | |
| 19 | #include "tegra-common.h" | |
| 20 | ||
| 0d79f4f4 TR |
21 | /* Cortex-A15 uses a cache line size of 64 bytes */ |
| 22 | #define CONFIG_SYS_CACHELINE_SIZE 64 | |
| 23 | ||
| 07067145 TW |
24 | /* |
| 25 | * NS16550 Configuration | |
| 26 | */ | |
| 27 | #define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */ | |
| 28 | ||
| 07067145 TW |
29 | /* |
| 30 | * Miscellaneous configurable options | |
| 31 | */ | |
| 07067145 TW |
32 | #define CONFIG_STACKBASE 0x82800000 /* 40MB */ |
| 33 | ||
| 34 | /*----------------------------------------------------------------------- | |
| 35 | * Physical Memory Map | |
| 36 | */ | |
| 37 | #define CONFIG_SYS_TEXT_BASE 0x8010E000 | |
| 38 | ||
| 39 | /* | |
| 40 | * Memory layout for where various images get loaded by boot scripts: | |
| 41 | * | |
| 42 | * scriptaddr can be pretty much anywhere that doesn't conflict with something | |
| 43 | * else. Put it above BOOTMAPSZ to eliminate conflicts. | |
| 44 | * | |
| f940c72e SW |
45 | * pxefile_addr_r can be pretty much anywhere that doesn't conflict with |
| 46 | * something else. Put it above BOOTMAPSZ to eliminate conflicts. | |
| 47 | * | |
| 07067145 TW |
48 | * kernel_addr_r must be within the first 128M of RAM in order for the |
| 49 | * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will | |
| 50 | * decompress itself to 0x8000 after the start of RAM, kernel_addr_r | |
| 51 | * should not overlap that area, or the kernel will have to copy itself | |
| 52 | * somewhere else before decompression. Similarly, the address of any other | |
| 53 | * data passed to the kernel shouldn't overlap the start of RAM. Pushing | |
| 54 | * this up to 16M allows for a sizable kernel to be decompressed below the | |
| 55 | * compressed load address. | |
| 56 | * | |
| 57 | * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for | |
| 58 | * the compressed kernel to be up to 16M too. | |
| 59 | * | |
| 60 | * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows | |
| 61 | * for the FDT/DTB to be up to 1M, which is hopefully plenty. | |
| 62 | */ | |
| 48cfca24 | 63 | #define CONFIG_LOADADDR 0x81000000 |
| 07067145 TW |
64 | #define MEM_LAYOUT_ENV_SETTINGS \ |
| 65 | "scriptaddr=0x90000000\0" \ | |
| f940c72e | 66 | "pxefile_addr_r=0x90100000\0" \ |
| 48cfca24 | 67 | "kernel_addr_r=" __stringify(CONFIG_LOADADDR) "\0" \ |
| 07067145 TW |
68 | "fdt_addr_r=0x82000000\0" \ |
| 69 | "ramdisk_addr_r=0x82100000\0" | |
| 70 | ||
| 71 | /* Defines for SPL */ | |
| 72 | #define CONFIG_SPL_TEXT_BASE 0x80108000 | |
| 73 | #define CONFIG_SYS_SPL_MALLOC_START 0x80090000 | |
| 74 | #define CONFIG_SPL_STACK 0x800ffffc | |
| 75 | ||
| d6cf707e JL |
76 | /* For USB EHCI controller */ |
| 77 | #define CONFIG_EHCI_IS_TDI | |
| 81d21e98 | 78 | #define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10 |
| f75dc784 | 79 | #define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1 |
| d6cf707e | 80 | |
| 07067145 | 81 | #endif /* _TEGRA114_COMMON_H_ */ |