[people/ms/u-boot.git] / include / configs / tegra114-common.h

/*
 * Copyright (c) 2010-2013, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#ifndef _TEGRA114_COMMON_H_
#define _TEGRA114_COMMON_H_
#include "tegra-common.h"

/* Cortex-A15 uses a cache line size of 64 bytes */
#define CONFIG_SYS_CACHELINE_SIZE	64

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK		408000000	/* 408MHz (pllp_out0) */

/* Environment information, boards can override if required */
#define CONFIG_LOADADDR		0x80408000	/* def. location for kernel */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x80A00800	/* default */
#define CONFIG_STACKBASE	0x82800000	/* 40MB */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_SYS_TEXT_BASE	0x8010E000

/*
 * Memory layout for where various images get loaded by boot scripts:
 *
 * scriptaddr can be pretty much anywhere that doesn't conflict with something
 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
 *
 * pxefile_addr_r can be pretty much anywhere that doesn't conflict with
 *   something else. Put it above BOOTMAPSZ to eliminate conflicts.
 *
 * kernel_addr_r must be within the first 128M of RAM in order for the
 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
 *   should not overlap that area, or the kernel will have to copy itself
 *   somewhere else before decompression. Similarly, the address of any other
 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
 *   this up to 16M allows for a sizable kernel to be decompressed below the
 *   compressed load address.
 *
 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
 *   the compressed kernel to be up to 16M too.
 *
 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
 */
#define MEM_LAYOUT_ENV_SETTINGS \
	"scriptaddr=0x90000000\0" \
	"pxefile_addr_r=0x90100000\0" \
	"kernel_addr_r=0x81000000\0" \
	"fdt_addr_r=0x82000000\0" \
	"ramdisk_addr_r=0x82100000\0"

/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x80108000
#define CONFIG_SYS_SPL_MALLOC_START	0x80090000
#define CONFIG_SPL_STACK		0x800ffffc

/* Total I2C ports on Tegra114 */
#define TEGRA_I2C_NUM_CONTROLLERS	5

/* For USB EHCI controller */
#define CONFIG_EHCI_IS_TDI
#define CONFIG_USB_EHCI_TXFIFO_THRESH	0x10
#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1

#endif /* _TEGRA114_COMMON_H_ */
Commit	Line	Data
07067145 TW	1	/*
	2	* Copyright (c) 2010-2013, NVIDIA CORPORATION. All rights reserved.
	3	*
	4	* This program is free software; you can redistribute it and/or modify it
	5	* under the terms and conditions of the GNU General Public License,
	6	* version 2, as published by the Free Software Foundation.
	7	*
	8	* This program is distributed in the hope it will be useful, but WITHOUT
	9	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	10	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	11	* more details.
	12	*
	13	* You should have received a copy of the GNU General Public License
	14	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	15	*/
	16
	17	#ifndef _TEGRA114_COMMON_H_
	18	#define _TEGRA114_COMMON_H_
	19	#include "tegra-common.h"
	20
0d79f4f4 TR	21	/* Cortex-A15 uses a cache line size of 64 bytes */
	22	#define CONFIG_SYS_CACHELINE_SIZE 64
	23
07067145 TW	24	/*
	25	* NS16550 Configuration
	26	*/
	27	#define V_NS16550_CLK 408000000 /* 408MHz (pllp_out0) */
	28
07067145 TW	29	/* Environment information, boards can override if required */
	30	#define CONFIG_LOADADDR 0x80408000 /* def. location for kernel */
	31
	32	/*
	33	* Miscellaneous configurable options
	34	*/
	35	#define CONFIG_SYS_LOAD_ADDR 0x80A00800 /* default */
	36	#define CONFIG_STACKBASE 0x82800000 /* 40MB */
	37
	38	/*-----------------------------------------------------------------------
	39	* Physical Memory Map
	40	*/
	41	#define CONFIG_SYS_TEXT_BASE 0x8010E000
	42
	43	/*
	44	* Memory layout for where various images get loaded by boot scripts:
	45	*
	46	* scriptaddr can be pretty much anywhere that doesn't conflict with something
	47	* else. Put it above BOOTMAPSZ to eliminate conflicts.
	48	*
f940c72e SW	49	* pxefile_addr_r can be pretty much anywhere that doesn't conflict with
	50	* something else. Put it above BOOTMAPSZ to eliminate conflicts.
	51	*
07067145 TW	52	* kernel_addr_r must be within the first 128M of RAM in order for the
	53	* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
	54	* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
	55	* should not overlap that area, or the kernel will have to copy itself
	56	* somewhere else before decompression. Similarly, the address of any other
	57	* data passed to the kernel shouldn't overlap the start of RAM. Pushing
	58	* this up to 16M allows for a sizable kernel to be decompressed below the
	59	* compressed load address.
	60	*
	61	* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
	62	* the compressed kernel to be up to 16M too.
	63	*
	64	* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
	65	* for the FDT/DTB to be up to 1M, which is hopefully plenty.
	66	*/
	67	#define MEM_LAYOUT_ENV_SETTINGS \
	68	"scriptaddr=0x90000000\0" \
f940c72e	69	"pxefile_addr_r=0x90100000\0" \
07067145 TW	70	"kernel_addr_r=0x81000000\0" \
	71	"fdt_addr_r=0x82000000\0" \
	72	"ramdisk_addr_r=0x82100000\0"
	73
	74	/* Defines for SPL */
	75	#define CONFIG_SPL_TEXT_BASE 0x80108000
	76	#define CONFIG_SYS_SPL_MALLOC_START 0x80090000
	77	#define CONFIG_SPL_STACK 0x800ffffc
	78
a7f8b5e6 TW	79	/* Total I2C ports on Tegra114 */
	80	#define TEGRA_I2C_NUM_CONTROLLERS 5
	81
d6cf707e JL	82	/* For USB EHCI controller */
d6cf707e JL	83	#define CONFIG_EHCI_IS_TDI
81d21e98	84	#define CONFIG_USB_EHCI_TXFIFO_THRESH 0x10
f75dc784	85	#define CONFIG_SYS_USB_EHCI_MAX_ROOT_PORTS 1
d6cf707e	86
07067145	87	#endif /* _TEGRA114_COMMON_H_ */