[people/ms/u-boot.git] / include / configs / tegra2-common.h

/*
 *  (C) Copyright 2010,2011
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __TEGRA2_COMMON_H
#define __TEGRA2_COMMON_H
#include <asm/sizes.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
#define CONFIG_TEGRA2			/* in a NVidia Tegra2 core */
#define CONFIG_MACH_TEGRA_GENERIC	/* which is a Tegra generic machine */
#define CONFIG_L2_OFF			/* No L2 cache */

#define CONFIG_ENABLE_CORTEXA9		/* enable CPU (A9 complex) */

#include <asm/arch/tegra2.h>		/* get chip and board defs */

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_SKIP_RELOCATE_UBOOT
#define CONFIG_SKIP_LOWLEVEL_INIT

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */

/* Environment */
#define CONFIG_ENV_IS_NOWHERE
#define CONFIG_ENV_SIZE			0x20000	/* Total Size Environment */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */

/*
 * PllX Configuration
 */
#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			216000000	/* 216MHz (pllp_out0) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/* include default commands */
#include <config_cmd_default.h>

/* remove unused commands */
#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NFS		/* NFS support */
#undef CONFIG_CMD_NET		/* network support */

/* turn on command-line edit/hist/auto */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTOCOMPLETE

#define CONFIG_SYS_NO_FLASH

/* Environment information */
#define CONFIG_EXTRA_ENV_SETTINGS \
	"console=ttyS0,115200n8\0" \
	"mem=" TEGRA2_SYSMEM "\0" \
	"smpflag=smp\0" \

#define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT_HUSH_PS2	"> "
#define CONFIG_SYS_PROMPT		V_PROMPT
/*
 * Increasing the size of the IO buffer as default nfsargs size is more
 *  than 256 and so it is not possible to edit it
 */
#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(TEGRA2_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)

#define CONFIG_SYS_LOAD_ADDR		(0xA00800)	/* default */
#define CONFIG_SYS_HZ			1000

/*-----------------------------------------------------------------------
 * Stack sizes
 *
 * The stack sizes are set up in start.S using the settings below
 */
#define CONFIG_STACKBASE	0x2800000	/* 40MB */
#define CONFIG_STACKSIZE	0x20000		/* 128K regular stack*/

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		TEGRA2_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */

#define CONFIG_SYS_TEXT_BASE	0x00E08000
#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

#endif /* __TEGRA2_COMMON_H */
Commit	Line	Data
efc05ae1 TW	1	/*
	2	* (C) Copyright 2010,2011
	3	* NVIDIA Corporation <www.nvidia.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
	24	#ifndef __TEGRA2_COMMON_H
	25	#define __TEGRA2_COMMON_H
	26	#include <asm/sizes.h>
	27
	28	/*
	29	* High Level Configuration Options
	30	*/
	31	#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
	32	#define CONFIG_TEGRA2 /* in a NVidia Tegra2 core */
	33	#define CONFIG_MACH_TEGRA_GENERIC /* which is a Tegra generic machine */
	34	#define CONFIG_L2_OFF /* No L2 cache */
	35
74652cf6 TW	36	#define CONFIG_ENABLE_CORTEXA9 /* enable CPU (A9 complex) */
74652cf6 TW	37
efc05ae1 TW	38	#include <asm/arch/tegra2.h> /* get chip and board defs */
	39
	40	/*
	41	* Display CPU and Board information
	42	*/
	43	#define CONFIG_DISPLAY_CPUINFO
	44	#define CONFIG_DISPLAY_BOARDINFO
	45
	46	#define CONFIG_SKIP_RELOCATE_UBOOT
	47	#define CONFIG_SKIP_LOWLEVEL_INIT
	48
	49	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
2fa8ca98	50	#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
efc05ae1 TW	51
	52	/* Environment */
	53	#define CONFIG_ENV_IS_NOWHERE
	54	#define CONFIG_ENV_SIZE 0x20000 /* Total Size Environment */
	55
	56	/*
	57	* Size of malloc() pool
	58	*/
	59	#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
	60
	61	/*
	62	* PllX Configuration
	63	*/
	64	#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
	65
	66	/*
	67	* NS16550 Configuration
	68	*/
	69	#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
	70
	71	#define CONFIG_SYS_NS16550
	72	#define CONFIG_SYS_NS16550_SERIAL
	73	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	74	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	75
	76	/*
	77	* select serial console configuration
	78	*/
	79	#define CONFIG_CONS_INDEX 1
	80
	81	/* allow to overwrite serial and ethaddr */
	82	#define CONFIG_ENV_OVERWRITE
	83	#define CONFIG_BAUDRATE 115200
	84	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	85	115200}
	86
	87	/* include default commands */
	88	#include <config_cmd_default.h>
	89
	90	/* remove unused commands */
	91	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	92	#undef CONFIG_CMD_FPGA /* FPGA configuration support */
	93	#undef CONFIG_CMD_IMI
	94	#undef CONFIG_CMD_IMLS
	95	#undef CONFIG_CMD_NFS /* NFS support */
	96	#undef CONFIG_CMD_NET /* network support */
	97
	98	/* turn on command-line edit/hist/auto */
	99	#define CONFIG_CMDLINE_EDITING
	100	#define CONFIG_COMMAND_HISTORY
	101	#define CONFIG_AUTOCOMPLETE
	102
	103	#define CONFIG_SYS_NO_FLASH
	104
	105	/* Environment information */
	106	#define CONFIG_EXTRA_ENV_SETTINGS \
	107	"console=ttyS0,115200n8\0" \
	108	"mem=" TEGRA2_SYSMEM "\0" \
	109	"smpflag=smp\0" \
	110
	111	#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
	112	#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
	113
	114	/*
115	* Miscellaneous configurable options
116	*/
117	#define CONFIG_SYS_LONGHELP /* undef to save memory */
118	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
119	#define CONFIG_SYS_PROMPT_HUSH_PS2 "> "
120	#define CONFIG_SYS_PROMPT V_PROMPT
121	/*
122	* Increasing the size of the IO buffer as default nfsargs size is more
123	* than 256 and so it is not possible to edit it
124	*/
125	#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
126	/* Print Buffer Size */
127	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
128	sizeof(CONFIG_SYS_PROMPT) + 16)
129	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
130	/* Boot Argument Buffer Size */
131	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
132
133	#define CONFIG_SYS_MEMTEST_START (TEGRA2_SDRC_CS0 + 0x600000)
134	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
135
136	#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
137	#define CONFIG_SYS_HZ 1000
138
139	/*-----------------------------------------------------------------------
140	* Stack sizes
141	*
142	* The stack sizes are set up in start.S using the settings below
143	*/
144	#define CONFIG_STACKBASE 0x2800000 /* 40MB */
145	#define CONFIG_STACKSIZE 0x20000 /* 128K regular stack*/
146
147	/*-----------------------------------------------------------------------
148	* Physical Memory Map
149	*/
150	#define CONFIG_NR_DRAM_BANKS 1
151	#define PHYS_SDRAM_1 TEGRA2_SDRC_CS0
152	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
153
154	#define CONFIG_SYS_TEXT_BASE 0x00E08000
155	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
156
157	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
158	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
159	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
160	CONFIG_SYS_INIT_RAM_SIZE - \
161	GENERATED_GBL_DATA_SIZE)
162
163	#endif /* __TEGRA2_COMMON_H */