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efc05ae1 | 1 | /* |
52a8b820 | 2 | * (C) Copyright 2010-2012 |
efc05ae1 TW |
3 | * NVIDIA Corporation <www.nvidia.com> |
4 | * | |
5 | * See file CREDITS for list of people who contributed to this | |
6 | * project. | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or | |
9 | * modify it under the terms of the GNU General Public License as | |
10 | * published by the Free Software Foundation; either version 2 of | |
11 | * the License, or (at your option) any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; if not, write to the Free Software | |
20 | * Foundation, Inc., 59 Temple Place, Suite 330, Boston, | |
21 | * MA 02111-1307 USA | |
22 | */ | |
23 | ||
f01b631f TW |
24 | #ifndef _TEGRA20_COMMON_H_ |
25 | #define _TEGRA20_COMMON_H_ | |
26 | #include "tegra-common.h" | |
27 | ||
c44bb3a3 SW |
28 | /* |
29 | * Errata configuration | |
30 | */ | |
53612132 | 31 | #define CONFIG_ARM_ERRATA_716044 |
c44bb3a3 SW |
32 | #define CONFIG_ARM_ERRATA_742230 |
33 | #define CONFIG_ARM_ERRATA_751472 | |
34 | ||
f01b631f TW |
35 | /* |
36 | * NS16550 Configuration | |
37 | */ | |
38 | #define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */ | |
649d0ffb | 39 | |
efc05ae1 TW |
40 | /* |
41 | * High Level Configuration Options | |
42 | */ | |
f01b631f | 43 | #define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */ |
efc05ae1 | 44 | |
f01b631f TW |
45 | /* Environment information, boards can override if required */ |
46 | #define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */ | |
96d21237 | 47 | |
f01b631f TW |
48 | /* |
49 | * Miscellaneous configurable options | |
50 | */ | |
51 | #define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */ | |
52 | #define CONFIG_STACKBASE 0x02800000 /* 40MB */ | |
efc05ae1 | 53 | |
f01b631f TW |
54 | /*----------------------------------------------------------------------- |
55 | * Physical Memory Map | |
56 | */ | |
57 | #define CONFIG_SYS_TEXT_BASE 0x0010E000 | |
ad16617f | 58 | |
efc05ae1 | 59 | /* |
f01b631f TW |
60 | * Memory layout for where various images get loaded by boot scripts: |
61 | * | |
62 | * scriptaddr can be pretty much anywhere that doesn't conflict with something | |
63 | * else. Put it above BOOTMAPSZ to eliminate conflicts. | |
64 | * | |
65 | * kernel_addr_r must be within the first 128M of RAM in order for the | |
66 | * kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will | |
67 | * decompress itself to 0x8000 after the start of RAM, kernel_addr_r | |
68 | * should not overlap that area, or the kernel will have to copy itself | |
69 | * somewhere else before decompression. Similarly, the address of any other | |
70 | * data passed to the kernel shouldn't overlap the start of RAM. Pushing | |
71 | * this up to 16M allows for a sizable kernel to be decompressed below the | |
72 | * compressed load address. | |
73 | * | |
74 | * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for | |
75 | * the compressed kernel to be up to 16M too. | |
76 | * | |
77 | * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows | |
78 | * for the FDT/DTB to be up to 1M, which is hopefully plenty. | |
efc05ae1 | 79 | */ |
f01b631f TW |
80 | #define MEM_LAYOUT_ENV_SETTINGS \ |
81 | "scriptaddr=0x10000000\0" \ | |
82 | "kernel_addr_r=0x01000000\0" \ | |
83 | "fdt_addr_r=0x02000000\0" \ | |
84 | "ramdisk_addr_r=0x02100000\0" | |
efc05ae1 | 85 | |
f01b631f TW |
86 | /* Defines for SPL */ |
87 | #define CONFIG_SPL_TEXT_BASE 0x00108000 | |
88 | #define CONFIG_SYS_SPL_MALLOC_START 0x00090000 | |
89 | #define CONFIG_SPL_STACK 0x000ffffc | |
90 | ||
f01b631f TW |
91 | /* Align LCD to 1MB boundary */ |
92 | #define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE | |
efc05ae1 | 93 | |
29f3e3f2 | 94 | #ifdef CONFIG_TEGRA_LP0 |
649d0ffb SG |
95 | #define TEGRA_LP0_ADDR 0x1C406000 |
96 | #define TEGRA_LP0_SIZE 0x2000 | |
97 | #define TEGRA_LP0_VEC \ | |
f01b631f | 98 | "lp0_vec=" __stringify(TEGRA_LP0_SIZE) \ |
51926d5e | 99 | "@" __stringify(TEGRA_LP0_ADDR) " " |
649d0ffb SG |
100 | #else |
101 | #define TEGRA_LP0_VEC | |
102 | #endif | |
103 | ||
0291091c SG |
104 | /* |
105 | * This parameter affects a TXFILLTUNING field that controls how much data is | |
106 | * sent to the latency fifo before it is sent to the wire. Without this | |
107 | * parameter, the default (2) causes occasional Data Buffer Errors in OUT | |
108 | * packets depending on the buffer address and size. | |
109 | */ | |
110 | #define CONFIG_USB_EHCI_TXFIFO_THRESH 10 | |
111 | #define CONFIG_EHCI_IS_TDI | |
0291091c | 112 | |
00a2749d | 113 | /* Total I2C ports on Tegra20 */ |
c360033f SG |
114 | #define TEGRA_I2C_NUM_CONTROLLERS 4 |
115 | ||
0dd84084 | 116 | #define CONFIG_SYS_NAND_SELF_INIT |
a833b950 | 117 | #define CONFIG_SYS_NAND_ONFI_DETECTION |
0dd84084 | 118 | |
f01b631f | 119 | #endif /* _TEGRA20_COMMON_H_ */ |