[people/ms/u-boot.git] / include / configs / tegra20-common.h

/*
 *  (C) Copyright 2010-2012
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __TEGRA20_COMMON_H
#define __TEGRA20_COMMON_H
#include <asm/sizes.h>
#include <linux/stringify.h>

/*
 * High Level Configuration Options
 */
#define CONFIG_ARMCORTEXA9		/* This is an ARM V7 CPU core */
#define CONFIG_TEGRA20			/* in a NVidia Tegra20 core */
#define CONFIG_TEGRA			/* which is a Tegra generic machine */
#define CONFIG_SYS_L2CACHE_OFF		/* No L2 cache */

#define CONFIG_SYS_CACHELINE_SIZE	32

#include <asm/arch/tegra.h>		/* get chip and board defs */

/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE

/*
 * Display CPU and Board information
 */
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

#define CONFIG_CMDLINE_TAG		/* enable passing of ATAGs */
#define CONFIG_OF_LIBFDT		/* enable passing of devicetree */

#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR			0x1C406000
#define TEGRA_LP0_SIZE			0x2000
#define TEGRA_LP0_VEC \
	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)	\
	"@" __stringify(TEGRA_LP0_ADDR) " "
#else
#define TEGRA_LP0_VEC
#endif

/* Environment */
#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_SIZE			0x2000	/* Total Size Environment */

/*
 * Size of malloc() pool
 */
#define CONFIG_SYS_MALLOC_LEN		(4 << 20)	/* 4MB  */

/*
 * PllX Configuration
 */
#define CONFIG_SYS_CPU_OSC_FREQUENCY	1000000	/* Set CPU clock to 1GHz */

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK			216000000	/* 216MHz (pllp_out0) */

#define CONFIG_SYS_NS16550
#define CONFIG_SYS_NS16550_SERIAL
#define CONFIG_SYS_NS16550_REG_SIZE	(-4)
#define CONFIG_SYS_NS16550_CLK		V_NS16550_CLK

/*
 * select serial console configuration
 */
#define CONFIG_CONS_INDEX	1

/* allow to overwrite serial and ethaddr */
#define CONFIG_ENV_OVERWRITE
#define CONFIG_BAUDRATE			115200
#define CONFIG_SYS_BAUDRATE_TABLE	{4800, 9600, 19200, 38400, 57600,\
					115200}

/*
 * This parameter affects a TXFILLTUNING field that controls how much data is
 * sent to the latency fifo before it is sent to the wire. Without this
 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
 * packets depending on the buffer address and size.
 */
#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
#define CONFIG_EHCI_IS_TDI

/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS	4

/* include default commands */
#include <config_cmd_default.h>
#define CONFIG_PARTITION_UUIDS
#define CONFIG_CMD_PART

/* remove unused commands */
#undef CONFIG_CMD_FLASH		/* flinfo, erase, protect */
#undef CONFIG_CMD_FPGA		/* FPGA configuration support */
#undef CONFIG_CMD_IMI
#undef CONFIG_CMD_IMLS
#undef CONFIG_CMD_NFS		/* NFS support */
#undef CONFIG_CMD_NET		/* network support */

/* turn on command-line edit/hist/auto */
#define CONFIG_CMDLINE_EDITING
#define CONFIG_COMMAND_HISTORY
#define CONFIG_AUTO_COMPLETE

#define CONFIG_SYS_NO_FLASH

#define CONFIG_CONSOLE_MUX
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_LOADADDR		0x408000	/* def. location for kernel */
#define CONFIG_BOOTDELAY	2		/* -1 to disable auto boot */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		V_PROMPT
/*
 * Increasing the size of the IO buffer as default nfsargs size is more
 *  than 256 and so it is not possible to edit it
 */
#define CONFIG_SYS_CBSIZE		(256 * 2) /* Console I/O Buffer Size */
/* Print Buffer Size */
#define CONFIG_SYS_PBSIZE		(CONFIG_SYS_CBSIZE + \
					sizeof(CONFIG_SYS_PROMPT) + 16)
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		(CONFIG_SYS_CBSIZE)

#define CONFIG_SYS_MEMTEST_START	(NV_PA_SDRC_CS0 + 0x600000)
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_MEMTEST_START + 0x100000)

#define CONFIG_SYS_LOAD_ADDR		(0xA00800)	/* default */
#define CONFIG_SYS_HZ			1000

#define CONFIG_STACKBASE	0x2800000	/* 40MB */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_NR_DRAM_BANKS	1
#define PHYS_SDRAM_1		NV_PA_SDRC_CS0
#define PHYS_SDRAM_1_SIZE	0x20000000	/* 512M */

#define CONFIG_SYS_TEXT_BASE	0x0010c000
#define CONFIG_SYS_UBOOT_START	CONFIG_SYS_TEXT_BASE
#define CONFIG_SYS_SDRAM_BASE	PHYS_SDRAM_1

#define CONFIG_SYS_BOOTMAPSZ	(256 << 20) /* 256M */

#define CONFIG_SYS_INIT_RAM_ADDR	CONFIG_STACKBASE
#define CONFIG_SYS_INIT_RAM_SIZE	CONFIG_SYS_MALLOC_LEN
#define CONFIG_SYS_INIT_SP_ADDR		(CONFIG_SYS_INIT_RAM_ADDR + \
						CONFIG_SYS_INIT_RAM_SIZE - \
						GENERATED_GBL_DATA_SIZE)

#define CONFIG_TEGRA_GPIO
#define CONFIG_CMD_GPIO
#define CONFIG_CMD_ENTERRCM
#define CONFIG_CMD_BOOTZ

/* Defines for SPL */
#define CONFIG_SPL
#define CONFIG_SPL_FRAMEWORK
#define CONFIG_SPL_RAM_DEVICE
#define CONFIG_SPL_BOARD_INIT
#define CONFIG_SPL_NAND_SIMPLE
#define CONFIG_SPL_TEXT_BASE		0x00108000
#define CONFIG_SPL_MAX_SIZE		(CONFIG_SYS_TEXT_BASE - \
						CONFIG_SPL_TEXT_BASE)
#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
#define CONFIG_SYS_SPL_MALLOC_SIZE	0x00010000
#define CONFIG_SPL_STACK		0x000ffffc

#define CONFIG_SPL_LIBCOMMON_SUPPORT
#define CONFIG_SPL_LIBGENERIC_SUPPORT
#define CONFIG_SPL_SERIAL_SUPPORT
#define CONFIG_SPL_GPIO_SUPPORT
#define CONFIG_SPL_LDSCRIPT		"$(CPUDIR)/tegra20/u-boot-spl.lds"

#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION

/* Misc utility code */
#define CONFIG_BOUNCE_BUFFER

#endif /* __TEGRA20_COMMON_H */
Commit	Line	Data
efc05ae1	1	/*
52a8b820	2	* (C) Copyright 2010-2012
efc05ae1 TW	3	* NVIDIA Corporation <www.nvidia.com>
	4	*
	5	* See file CREDITS for list of people who contributed to this
	6	* project.
	7	*
	8	* This program is free software; you can redistribute it and/or
	9	* modify it under the terms of the GNU General Public License as
	10	* published by the Free Software Foundation; either version 2 of
	11	* the License, or (at your option) any later version.
	12	*
	13	* This program is distributed in the hope that it will be useful,
	14	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	15	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	16	* GNU General Public License for more details.
	17	*
	18	* You should have received a copy of the GNU General Public License
	19	* along with this program; if not, write to the Free Software
	20	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	21	* MA 02111-1307 USA
	22	*/
	23
00a2749d AM	24	#ifndef __TEGRA20_COMMON_H
00a2749d AM	25	#define __TEGRA20_COMMON_H
efc05ae1	26	#include <asm/sizes.h>
51926d5e	27	#include <linux/stringify.h>
649d0ffb	28
efc05ae1 TW	29	/*
	30	* High Level Configuration Options
	31	*/
	32	#define CONFIG_ARMCORTEXA9 /* This is an ARM V7 CPU core */
00a2749d	33	#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
7e5fd8fb	34	#define CONFIG_TEGRA /* which is a Tegra generic machine */
e47f2db5	35	#define CONFIG_SYS_L2CACHE_OFF /* No L2 cache */
efc05ae1	36
96d21237 A	37	#define CONFIG_SYS_CACHELINE_SIZE 32
96d21237 A	38
150c2493	39	#include <asm/arch/tegra.h> /* get chip and board defs */
efc05ae1	40
ad16617f SG	41	/* Align LCD to 1MB boundary */
	42	#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
	43
efc05ae1 TW	44	/*
	45	* Display CPU and Board information
	46	*/
	47	#define CONFIG_DISPLAY_CPUINFO
	48	#define CONFIG_DISPLAY_BOARDINFO
	49
efc05ae1	50	#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */
2fa8ca98	51	#define CONFIG_OF_LIBFDT /* enable passing of devicetree */
efc05ae1	52
29f3e3f2	53	#ifdef CONFIG_TEGRA_LP0
649d0ffb SG	54	#define TEGRA_LP0_ADDR 0x1C406000
	55	#define TEGRA_LP0_SIZE 0x2000
	56	#define TEGRA_LP0_VEC \
51926d5e MV	57	"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
51926d5e MV	58	"@" __stringify(TEGRA_LP0_ADDR) " "
649d0ffb SG	59	#else
	60	#define TEGRA_LP0_VEC
	61	#endif
	62
efc05ae1	63	/* Environment */
0a7bec7f	64	#define CONFIG_ENV_VARS_UBOOT_CONFIG
9dd79fdb	65	#define CONFIG_ENV_SIZE 0x2000 /* Total Size Environment */
efc05ae1 TW	66
	67	/*
	68	* Size of malloc() pool
	69	*/
	70	#define CONFIG_SYS_MALLOC_LEN (4 << 20) /* 4MB */
	71
	72	/*
	73	* PllX Configuration
	74	*/
	75	#define CONFIG_SYS_CPU_OSC_FREQUENCY 1000000 /* Set CPU clock to 1GHz */
	76
	77	/*
	78	* NS16550 Configuration
	79	*/
	80	#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
	81
	82	#define CONFIG_SYS_NS16550
	83	#define CONFIG_SYS_NS16550_SERIAL
	84	#define CONFIG_SYS_NS16550_REG_SIZE (-4)
	85	#define CONFIG_SYS_NS16550_CLK V_NS16550_CLK
	86
	87	/*
	88	* select serial console configuration
	89	*/
	90	#define CONFIG_CONS_INDEX 1
	91
	92	/* allow to overwrite serial and ethaddr */
	93	#define CONFIG_ENV_OVERWRITE
	94	#define CONFIG_BAUDRATE 115200
	95	#define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600,\
	96	115200}
	97
0291091c SG	98	/*
	99	* This parameter affects a TXFILLTUNING field that controls how much data is
	100	* sent to the latency fifo before it is sent to the wire. Without this
	101	* parameter, the default (2) causes occasional Data Buffer Errors in OUT
	102	* packets depending on the buffer address and size.
	103	*/
	104	#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
	105	#define CONFIG_EHCI_IS_TDI
0291091c	106
00a2749d	107	/* Total I2C ports on Tegra20 */
c360033f SG	108	#define TEGRA_I2C_NUM_CONTROLLERS 4
c360033f SG	109
efc05ae1 TW	110	/* include default commands */
efc05ae1 TW	111	#include <config_cmd_default.h>
01ca2865 SW	112	#define CONFIG_PARTITION_UUIDS
01ca2865 SW	113	#define CONFIG_CMD_PART
efc05ae1 TW	114
	115	/* remove unused commands */
	116	#undef CONFIG_CMD_FLASH /* flinfo, erase, protect */
	117	#undef CONFIG_CMD_FPGA /* FPGA configuration support */
	118	#undef CONFIG_CMD_IMI
	119	#undef CONFIG_CMD_IMLS
	120	#undef CONFIG_CMD_NFS /* NFS support */
	121	#undef CONFIG_CMD_NET /* network support */
	122
	123	/* turn on command-line edit/hist/auto */
	124	#define CONFIG_CMDLINE_EDITING
	125	#define CONFIG_COMMAND_HISTORY
ed0fc4b1	126	#define CONFIG_AUTO_COMPLETE
efc05ae1 TW	127
	128	#define CONFIG_SYS_NO_FLASH
	129
4120c271 SG	130	#define CONFIG_CONSOLE_MUX
4120c271 SG	131	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
4120c271	132
efc05ae1 TW	133	#define CONFIG_LOADADDR 0x408000 /* def. location for kernel */
	134	#define CONFIG_BOOTDELAY 2 /* -1 to disable auto boot */
	135
	136	/*
	137	* Miscellaneous configurable options
	138	*/
	139	#define CONFIG_SYS_LONGHELP /* undef to save memory */
	140	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
efc05ae1 TW	141	#define CONFIG_SYS_PROMPT V_PROMPT
	142	/*
	143	* Increasing the size of the IO buffer as default nfsargs size is more
	144	* than 256 and so it is not possible to edit it
	145	*/
	146	#define CONFIG_SYS_CBSIZE (256 * 2) /* Console I/O Buffer Size */
	147	/* Print Buffer Size */
	148	#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE + \
	149	sizeof(CONFIG_SYS_PROMPT) + 16)
	150	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	151	/* Boot Argument Buffer Size */
	152	#define CONFIG_SYS_BARGSIZE (CONFIG_SYS_CBSIZE)
	153
29f3e3f2	154	#define CONFIG_SYS_MEMTEST_START (NV_PA_SDRC_CS0 + 0x600000)
efc05ae1 TW	155	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_MEMTEST_START + 0x100000)
	156
	157	#define CONFIG_SYS_LOAD_ADDR (0xA00800) /* default */
	158	#define CONFIG_SYS_HZ 1000
	159
efc05ae1	160	#define CONFIG_STACKBASE 0x2800000 /* 40MB */
efc05ae1 TW	161
	162	/*-----------------------------------------------------------------------
	163	* Physical Memory Map
	164	*/
	165	#define CONFIG_NR_DRAM_BANKS 1
29f3e3f2	166	#define PHYS_SDRAM_1 NV_PA_SDRC_CS0
efc05ae1 TW	167	#define PHYS_SDRAM_1_SIZE 0x20000000 /* 512M */
efc05ae1 TW	168
12b7b70c	169	#define CONFIG_SYS_TEXT_BASE 0x0010c000
b2f98938	170	#define CONFIG_SYS_UBOOT_START CONFIG_SYS_TEXT_BASE
efc05ae1 TW	171	#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1
efc05ae1 TW	172
7f1b767a SW	173	#define CONFIG_SYS_BOOTMAPSZ (256 << 20) /* 256M */
7f1b767a SW	174
efc05ae1 TW	175	#define CONFIG_SYS_INIT_RAM_ADDR CONFIG_STACKBASE
	176	#define CONFIG_SYS_INIT_RAM_SIZE CONFIG_SYS_MALLOC_LEN
	177	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_INIT_RAM_ADDR + \
	178	CONFIG_SYS_INIT_RAM_SIZE - \
	179	GENERATED_GBL_DATA_SIZE)
	180
52a8b820	181	#define CONFIG_TEGRA_GPIO
f84d64db	182	#define CONFIG_CMD_GPIO
9cd3f3ad	183	#define CONFIG_CMD_ENTERRCM
dd8ab953	184	#define CONFIG_CMD_BOOTZ
12b7b70c AM	185
	186	/* Defines for SPL */
	187	#define CONFIG_SPL
b2f98938 AM	188	#define CONFIG_SPL_FRAMEWORK
	189	#define CONFIG_SPL_RAM_DEVICE
	190	#define CONFIG_SPL_BOARD_INIT
12b7b70c AM	191	#define CONFIG_SPL_NAND_SIMPLE
12b7b70c AM	192	#define CONFIG_SPL_TEXT_BASE 0x00108000
644a69ec SW	193	#define CONFIG_SPL_MAX_SIZE (CONFIG_SYS_TEXT_BASE - \
644a69ec SW	194	CONFIG_SPL_TEXT_BASE)
12b7b70c AM	195	#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
	196	#define CONFIG_SYS_SPL_MALLOC_SIZE 0x00010000
	197	#define CONFIG_SPL_STACK 0x000ffffc
	198
	199	#define CONFIG_SPL_LIBCOMMON_SUPPORT
	200	#define CONFIG_SPL_LIBGENERIC_SUPPORT
	201	#define CONFIG_SPL_SERIAL_SUPPORT
	202	#define CONFIG_SPL_GPIO_SUPPORT
	203	#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/tegra20/u-boot-spl.lds"
	204
0dd84084	205	#define CONFIG_SYS_NAND_SELF_INIT
a833b950	206	#define CONFIG_SYS_NAND_ONFI_DETECTION
0dd84084	207
19815399 SW	208	/* Misc utility code */
	209	#define CONFIG_BOUNCE_BUFFER
	210
00a2749d	211	#endif /* __TEGRA20_COMMON_H */