[people/ms/u-boot.git] / include / configs / tegra20-common.h

/*
 *  (C) Copyright 2010-2012
 *  NVIDIA Corporation <www.nvidia.com>
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef _TEGRA20_COMMON_H_
#define _TEGRA20_COMMON_H_
#include "tegra-common.h"

/* Cortex-A9 uses a cache line size of 32 bytes */
#define CONFIG_SYS_CACHELINE_SIZE	32

/*
 * Errata configuration
 */
#define CONFIG_ARM_ERRATA_716044
#define CONFIG_ARM_ERRATA_742230
#define CONFIG_ARM_ERRATA_751472

/*
 * NS16550 Configuration
 */
#define V_NS16550_CLK		216000000	/* 216MHz (pllp_out0) */

/*
 * High Level Configuration Options
 */
#define CONFIG_TEGRA20				/* in a NVidia Tegra20 core */

/* Environment information, boards can override if required */
#define CONFIG_LOADADDR		0x00408000	/* def. location for kernel */

/*
 * Miscellaneous configurable options
 */
#define CONFIG_SYS_LOAD_ADDR	0x00A00800	/* default */
#define CONFIG_STACKBASE	0x02800000	/* 40MB */

/*-----------------------------------------------------------------------
 * Physical Memory Map
 */
#define CONFIG_SYS_TEXT_BASE	0x0010E000

/*
 * Memory layout for where various images get loaded by boot scripts:
 *
 * scriptaddr can be pretty much anywhere that doesn't conflict with something
 *   else. Put it above BOOTMAPSZ to eliminate conflicts.
 *
 * kernel_addr_r must be within the first 128M of RAM in order for the
 *   kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
 *   decompress itself to 0x8000 after the start of RAM, kernel_addr_r
 *   should not overlap that area, or the kernel will have to copy itself
 *   somewhere else before decompression. Similarly, the address of any other
 *   data passed to the kernel shouldn't overlap the start of RAM. Pushing
 *   this up to 16M allows for a sizable kernel to be decompressed below the
 *   compressed load address.
 *
 * fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
 *   the compressed kernel to be up to 16M too.
 *
 * ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
 *   for the FDT/DTB to be up to 1M, which is hopefully plenty.
 */
#define MEM_LAYOUT_ENV_SETTINGS \
	"scriptaddr=0x10000000\0" \
	"kernel_addr_r=0x01000000\0" \
	"fdt_addr_r=0x02000000\0" \
	"ramdisk_addr_r=0x02100000\0"

/* Defines for SPL */
#define CONFIG_SPL_TEXT_BASE		0x00108000
#define CONFIG_SYS_SPL_MALLOC_START	0x00090000
#define CONFIG_SPL_STACK		0x000ffffc

/* Align LCD to 1MB boundary */
#define CONFIG_LCD_ALIGNMENT	MMU_SECTION_SIZE

#ifdef CONFIG_TEGRA_LP0
#define TEGRA_LP0_ADDR			0x1C406000
#define TEGRA_LP0_SIZE			0x2000
#define TEGRA_LP0_VEC \
	"lp0_vec=" __stringify(TEGRA_LP0_SIZE)  \
	"@" __stringify(TEGRA_LP0_ADDR) " "
#else
#define TEGRA_LP0_VEC
#endif

/*
 * This parameter affects a TXFILLTUNING field that controls how much data is
 * sent to the latency fifo before it is sent to the wire. Without this
 * parameter, the default (2) causes occasional Data Buffer Errors in OUT
 * packets depending on the buffer address and size.
 */
#define CONFIG_USB_EHCI_TXFIFO_THRESH	10
#define CONFIG_EHCI_IS_TDI

/* Total I2C ports on Tegra20 */
#define TEGRA_I2C_NUM_CONTROLLERS	4

#define CONFIG_SYS_NAND_SELF_INIT
#define CONFIG_SYS_NAND_ONFI_DETECTION

#endif /* _TEGRA20_COMMON_H_ */
Commit	Line	Data
efc05ae1	1	/*
52a8b820	2	* (C) Copyright 2010-2012
efc05ae1 TW	3	* NVIDIA Corporation <www.nvidia.com>
efc05ae1 TW	4	*
1a459660	5	* SPDX-License-Identifier: GPL-2.0+
efc05ae1 TW	6	*/
efc05ae1 TW	7
f01b631f TW	8	#ifndef _TEGRA20_COMMON_H_
	9	#define _TEGRA20_COMMON_H_
	10	#include "tegra-common.h"
	11
0d79f4f4 TR	12	/* Cortex-A9 uses a cache line size of 32 bytes */
	13	#define CONFIG_SYS_CACHELINE_SIZE 32
	14
c44bb3a3 SW	15	/*
	16	* Errata configuration
	17	*/
53612132	18	#define CONFIG_ARM_ERRATA_716044
c44bb3a3 SW	19	#define CONFIG_ARM_ERRATA_742230
	20	#define CONFIG_ARM_ERRATA_751472
	21
f01b631f TW	22	/*
	23	* NS16550 Configuration
	24	*/
	25	#define V_NS16550_CLK 216000000 /* 216MHz (pllp_out0) */
649d0ffb	26
efc05ae1 TW	27	/*
	28	* High Level Configuration Options
	29	*/
f01b631f	30	#define CONFIG_TEGRA20 /* in a NVidia Tegra20 core */
efc05ae1	31
f01b631f TW	32	/* Environment information, boards can override if required */
f01b631f TW	33	#define CONFIG_LOADADDR 0x00408000 /* def. location for kernel */
96d21237	34
f01b631f TW	35	/*
	36	* Miscellaneous configurable options
	37	*/
	38	#define CONFIG_SYS_LOAD_ADDR 0x00A00800 /* default */
	39	#define CONFIG_STACKBASE 0x02800000 /* 40MB */
efc05ae1	40
f01b631f TW	41	/*-----------------------------------------------------------------------
	42	* Physical Memory Map
	43	*/
	44	#define CONFIG_SYS_TEXT_BASE 0x0010E000
ad16617f	45
efc05ae1	46	/*
f01b631f TW	47	* Memory layout for where various images get loaded by boot scripts:
	48	*
	49	* scriptaddr can be pretty much anywhere that doesn't conflict with something
	50	* else. Put it above BOOTMAPSZ to eliminate conflicts.
	51	*
	52	* kernel_addr_r must be within the first 128M of RAM in order for the
	53	* kernel's CONFIG_AUTO_ZRELADDR option to work. Since the kernel will
	54	* decompress itself to 0x8000 after the start of RAM, kernel_addr_r
	55	* should not overlap that area, or the kernel will have to copy itself
	56	* somewhere else before decompression. Similarly, the address of any other
	57	* data passed to the kernel shouldn't overlap the start of RAM. Pushing
	58	* this up to 16M allows for a sizable kernel to be decompressed below the
	59	* compressed load address.
	60	*
	61	* fdt_addr_r simply shouldn't overlap anything else. Choosing 32M allows for
	62	* the compressed kernel to be up to 16M too.
	63	*
	64	* ramdisk_addr_r simply shouldn't overlap anything else. Choosing 33M allows
	65	* for the FDT/DTB to be up to 1M, which is hopefully plenty.
efc05ae1	66	*/
f01b631f TW	67	#define MEM_LAYOUT_ENV_SETTINGS \
	68	"scriptaddr=0x10000000\0" \
	69	"kernel_addr_r=0x01000000\0" \
	70	"fdt_addr_r=0x02000000\0" \
	71	"ramdisk_addr_r=0x02100000\0"
efc05ae1	72
f01b631f TW	73	/* Defines for SPL */
	74	#define CONFIG_SPL_TEXT_BASE 0x00108000
	75	#define CONFIG_SYS_SPL_MALLOC_START 0x00090000
	76	#define CONFIG_SPL_STACK 0x000ffffc
	77
f01b631f TW	78	/* Align LCD to 1MB boundary */
f01b631f TW	79	#define CONFIG_LCD_ALIGNMENT MMU_SECTION_SIZE
efc05ae1	80
29f3e3f2	81	#ifdef CONFIG_TEGRA_LP0
649d0ffb SG	82	#define TEGRA_LP0_ADDR 0x1C406000
	83	#define TEGRA_LP0_SIZE 0x2000
	84	#define TEGRA_LP0_VEC \
f01b631f	85	"lp0_vec=" __stringify(TEGRA_LP0_SIZE) \
51926d5e	86	"@" __stringify(TEGRA_LP0_ADDR) " "
649d0ffb SG	87	#else
	88	#define TEGRA_LP0_VEC
	89	#endif
	90
0291091c SG	91	/*
	92	* This parameter affects a TXFILLTUNING field that controls how much data is
	93	* sent to the latency fifo before it is sent to the wire. Without this
	94	* parameter, the default (2) causes occasional Data Buffer Errors in OUT
	95	* packets depending on the buffer address and size.
	96	*/
	97	#define CONFIG_USB_EHCI_TXFIFO_THRESH 10
	98	#define CONFIG_EHCI_IS_TDI
0291091c	99
00a2749d	100	/* Total I2C ports on Tegra20 */
c360033f SG	101	#define TEGRA_I2C_NUM_CONTROLLERS 4
c360033f SG	102
0dd84084	103	#define CONFIG_SYS_NAND_SELF_INIT
a833b950	104	#define CONFIG_SYS_NAND_ONFI_DETECTION
0dd84084	105
f01b631f	106	#endif /* _TEGRA20_COMMON_H_ */