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b20c38a9 SR |
1 | /* |
2 | * Copyright (C) 2015-2016 Stefan Roese <sr@denx.de> | |
3 | * | |
4 | * SPDX-License-Identifier: GPL-2.0+ | |
5 | */ | |
6 | ||
7 | #ifndef _CONFIG_THEADORABLE_H | |
8 | #define _CONFIG_THEADORABLE_H | |
9 | ||
10 | /* | |
11 | * High Level Configuration Options (easy to change) | |
12 | */ | |
13 | #define CONFIG_DISPLAY_BOARDINFO_LATE | |
14 | ||
15 | /* | |
16 | * TEXT_BASE needs to be below 16MiB, since this area is scrubbed | |
17 | * for DDR ECC byte filling in the SPL before loading the main | |
18 | * U-Boot into it. | |
19 | */ | |
20 | #define CONFIG_SYS_TEXT_BASE 0x00800000 | |
21 | #define CONFIG_SYS_TCLK 250000000 /* 250MHz */ | |
22 | ||
23 | /* | |
24 | * Commands configuration | |
25 | */ | |
b20c38a9 SR |
26 | |
27 | /* | |
28 | * The debugging version enables USB support via defconfig. | |
29 | * This version should also enable all other non-production | |
30 | * interfaces / features. | |
31 | */ | |
b20c38a9 SR |
32 | |
33 | /* I2C */ | |
34 | #define CONFIG_SYS_I2C | |
35 | #define CONFIG_SYS_I2C_MVTWSI | |
36 | #define CONFIG_I2C_MVTWSI_BASE0 MVEBU_TWSI_BASE | |
8ac71da9 | 37 | #define CONFIG_I2C_MVTWSI_BASE1 MVEBU_TWSI1_BASE |
b20c38a9 SR |
38 | #define CONFIG_SYS_I2C_SLAVE 0x0 |
39 | #define CONFIG_SYS_I2C_SPEED 100000 | |
40 | ||
41 | /* USB/EHCI configuration */ | |
42 | #define CONFIG_EHCI_IS_TDI | |
43 | #define CONFIG_USB_MAX_CONTROLLER_COUNT 3 | |
44 | ||
b20c38a9 SR |
45 | /* SPI NOR flash default params, used by sf commands */ |
46 | #define CONFIG_SF_DEFAULT_SPEED 27777777 /* for fast SPL booting */ | |
47 | #define CONFIG_SF_DEFAULT_MODE SPI_MODE_3 | |
48 | ||
49 | /* Environment in SPI NOR flash */ | |
b20c38a9 SR |
50 | #define CONFIG_ENV_OFFSET (1 << 20) /* 1MiB in */ |
51 | #define CONFIG_ENV_SIZE (64 << 10) /* 64KiB */ | |
52 | #define CONFIG_ENV_SECT_SIZE (256 << 10) /* 256KiB sectors */ | |
53 | #define CONFIG_ENV_OVERWRITE | |
54 | ||
55 | #define CONFIG_PHY_MARVELL /* there is a marvell phy */ | |
56 | #define PHY_ANEG_TIMEOUT 8000 /* PHY needs a longer aneg time */ | |
57 | ||
b20c38a9 SR |
58 | #define CONFIG_SYS_ALT_MEMTEST |
59 | #define CONFIG_PREBOOT | |
b20c38a9 | 60 | |
b20c38a9 SR |
61 | /* Keep device tree and initrd in lower memory so the kernel can access them */ |
62 | #define CONFIG_EXTRA_ENV_SETTINGS \ | |
63 | "fdt_high=0x10000000\0" \ | |
64 | "initrd_high=0x10000000\0" | |
65 | ||
66 | /* SATA support */ | |
67 | #define CONFIG_SYS_SATA_MAX_DEVICE 1 | |
b20c38a9 | 68 | #define CONFIG_LBA48 |
b20c38a9 SR |
69 | |
70 | /* Additional FS support/configuration */ | |
71 | #define CONFIG_SUPPORT_VFAT | |
72 | ||
73 | /* PCIe support */ | |
74 | #ifdef CONFIG_CMD_PCI | |
75 | #ifndef CONFIG_SPL_BUILD | |
b20c38a9 | 76 | #define CONFIG_PCI_MVEBU |
b20c38a9 SR |
77 | #endif |
78 | #endif | |
79 | ||
80 | /* Enable LCD and reserve 512KB from top of memory*/ | |
81 | #define CONFIG_SYS_MEM_TOP_HIDE 0x80000 | |
82 | ||
aea02abe | 83 | /* FPGA programming support */ |
aea02abe SR |
84 | #define CONFIG_FPGA_STRATIX_V |
85 | ||
28226b9a SR |
86 | /* |
87 | * Bootcounter | |
88 | */ | |
89 | #define CONFIG_BOOTCOUNT_LIMIT | |
90 | #define CONFIG_BOOTCOUNT_RAM | |
91 | /* Max size of RAM minus BOOTCOUNT_ADDR is the bootcounter address */ | |
92 | #define BOOTCOUNT_ADDR 0x1000 | |
93 | ||
b20c38a9 SR |
94 | /* |
95 | * mv-common.h should be defined after CMD configs since it used them | |
96 | * to enable certain macros | |
97 | */ | |
98 | #include "mv-common.h" | |
99 | ||
100 | /* | |
101 | * Memory layout while starting into the bin_hdr via the | |
102 | * BootROM: | |
103 | * | |
104 | * 0x4000.4000 - 0x4003.4000 headers space (192KiB) | |
105 | * 0x4000.4030 bin_hdr start address | |
106 | * 0x4003.4000 - 0x4004.7c00 BootROM memory allocations (15KiB) | |
107 | * 0x4007.fffc BootROM stack top | |
108 | * | |
109 | * The address space between 0x4007.fffc and 0x400f.fff is not locked in | |
110 | * L2 cache thus cannot be used. | |
111 | */ | |
112 | ||
113 | /* SPL */ | |
114 | /* Defines for SPL */ | |
115 | #define CONFIG_SPL_FRAMEWORK | |
116 | #define CONFIG_SPL_TEXT_BASE 0x40004030 | |
117 | #define CONFIG_SPL_MAX_SIZE ((128 << 10) - 0x4030) | |
118 | ||
119 | #define CONFIG_SPL_BSS_START_ADDR (0x40000000 + (128 << 10)) | |
120 | #define CONFIG_SPL_BSS_MAX_SIZE (16 << 10) | |
121 | ||
122 | #ifdef CONFIG_SPL_BUILD | |
123 | #define CONFIG_SYS_MALLOC_SIMPLE | |
124 | #endif | |
125 | ||
126 | #define CONFIG_SPL_STACK (0x40000000 + ((192 - 16) << 10)) | |
127 | #define CONFIG_SPL_BOOTROM_SAVE (CONFIG_SPL_STACK + 4) | |
128 | ||
b20c38a9 | 129 | /* SPL related SPI defines */ |
b20c38a9 | 130 | #define CONFIG_SPL_SPI_LOAD |
b20c38a9 SR |
131 | #define CONFIG_SYS_SPI_U_BOOT_OFFS 0x1a000 |
132 | #define CONFIG_SYS_U_BOOT_OFFS CONFIG_SYS_SPI_U_BOOT_OFFS | |
133 | ||
134 | /* Enable DDR support in SPL (DDR3 training from Marvell bin_hdr) */ | |
135 | #define CONFIG_DDR_FIXED_SIZE (2 << 20) /* 2GiB */ | |
136 | ||
137 | #endif /* _CONFIG_THEADORABLE_H */ |