]>
Commit | Line | Data |
---|---|---|
9a0f4004 NM |
1 | /* |
2 | * ti_armv7_omap.h | |
3 | * | |
4 | * Copyright (C) 2015 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | * | |
8 | * The various ARMv7 SoCs from TI all share a number of IP blocks when | |
9 | * implementing a given feature. This is meant to isolate the features | |
10 | * that are based on OMAP architecture. | |
11 | */ | |
12 | #ifndef __CONFIG_TI_ARMV7_OMAP_H__ | |
13 | #define __CONFIG_TI_ARMV7_OMAP_H__ | |
14 | ||
15 | /* Common defines for all OMAP architecture based SoCs */ | |
16 | #define CONFIG_OMAP | |
17 | #define CONFIG_OMAP_COMMON | |
18 | ||
19 | /* I2C IP block */ | |
20 | #define CONFIG_SYS_OMAP24_I2C_SPEED 100000 | |
21 | #define CONFIG_SYS_OMAP24_I2C_SLAVE 1 | |
22 | #define CONFIG_SYS_I2C_OMAP24XX | |
23 | ||
24 | /* MMC/SD IP block */ | |
25 | #define CONFIG_OMAP_HSMMC | |
26 | ||
27 | /* SPI IP Block */ | |
28 | #define CONFIG_OMAP3_SPI | |
29 | ||
30 | /* GPIO block */ | |
31 | #define CONFIG_OMAP_GPIO | |
32 | ||
33 | /* | |
34 | * GPMC NAND block. We support 1 device and the physical address to | |
35 | * access CS0 at is 0x8000000. | |
36 | */ | |
37 | #ifdef CONFIG_NAND | |
38 | #define CONFIG_NAND_OMAP_GPMC | |
39 | #ifndef CONFIG_SYS_NAND_BASE | |
40 | #define CONFIG_SYS_NAND_BASE 0x8000000 | |
41 | #endif | |
42 | #define CONFIG_SYS_MAX_NAND_DEVICE 1 | |
43 | #define CONFIG_CMD_NAND | |
44 | #endif | |
45 | ||
46 | /* Now for the remaining common defines */ | |
47 | #include <configs/ti_armv7_common.h> | |
48 | ||
49 | #endif /* __CONFIG_TI_ARMV7_OMAP_H__ */ |