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c7964f86 EBS |
1 | /* |
2 | * ti_omap3_common.h | |
3 | * | |
4 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
5 | * | |
6 | * SPDX-License-Identifier: GPL-2.0+ | |
7 | * | |
8 | * For more details, please see the technical documents listed at | |
9 | * http://www.ti.com/product/omap3530 | |
10 | * http://www.ti.com/product/omap3630 | |
11 | * http://www.ti.com/product/dm3730 | |
12 | */ | |
13 | ||
14 | #ifndef __CONFIG_TI_OMAP3_COMMON_H__ | |
15 | #define __CONFIG_TI_OMAP3_COMMON_H__ | |
16 | ||
c7964f86 EBS |
17 | |
18 | #include <asm/arch/cpu.h> | |
987ec585 | 19 | #include <asm/arch/omap.h> |
c7964f86 | 20 | |
c6f90e14 NM |
21 | /* Common ARM Erratas */ |
22 | #define CONFIG_ARM_ERRATA_454179 | |
23 | #define CONFIG_ARM_ERRATA_430973 | |
24 | #define CONFIG_ARM_ERRATA_621766 | |
25 | ||
c7964f86 EBS |
26 | /* The chip has SDRC controller */ |
27 | #define CONFIG_SDRC | |
28 | ||
29 | /* Clock Defines */ | |
30 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
31 | #define V_SCLK (V_OSCK >> 1) | |
32 | ||
33 | /* NS16550 Configuration */ | |
34 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
c7b9686d | 35 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
b3f4ca11 SG |
36 | #ifdef CONFIG_SPL_BUILD |
37 | # define CONFIG_SYS_NS16550_SERIAL | |
38 | # define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
b3f4ca11 | 39 | #endif |
c7964f86 EBS |
40 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ |
41 | 115200} | |
42 | ||
43 | /* Select serial console configuration */ | |
44 | #define CONFIG_CONS_INDEX 3 | |
b3f4ca11 | 45 | #ifdef CONFIG_SPL_BUILD |
c7964f86 EBS |
46 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
47 | #define CONFIG_SERIAL3 3 | |
b3f4ca11 | 48 | #endif |
c7964f86 EBS |
49 | |
50 | /* Physical Memory Map */ | |
51 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
52 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
53 | ||
54 | /* | |
55 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
56 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
57 | * This rate is divided by a local divisor. | |
58 | */ | |
59 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
60 | ||
61 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
62 | ||
63 | /* TWL4030 */ | |
689821fd | 64 | #define CONFIG_TWL4030_POWER |
c7964f86 EBS |
65 | |
66 | /* SPL */ | |
67 | #define CONFIG_SPL_TEXT_BASE 0x40200800 | |
68 | #define CONFIG_SPL_MAX_SIZE (54 * 1024) | |
69 | #define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" | |
70 | #define CONFIG_SPL_POWER_SUPPORT | |
d3289aac TR |
71 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
72 | (64 << 20)) | |
73 | ||
c7964f86 EBS |
74 | |
75 | #ifdef CONFIG_NAND | |
c7964f86 | 76 | #define CONFIG_SPL_NAND_SIMPLE |
df4dbb5d | 77 | #define CONFIG_SYS_NAND_BASE 0x30000000 |
c7964f86 EBS |
78 | #endif |
79 | ||
80 | /* Now bring in the rest of the common code. */ | |
9a0f4004 | 81 | #include <configs/ti_armv7_omap.h> |
c7964f86 EBS |
82 | |
83 | #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ |