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83d290c5 | 1 | /* SPDX-License-Identifier: GPL-2.0+ */ |
c7964f86 EBS |
2 | /* |
3 | * ti_omap3_common.h | |
4 | * | |
5 | * Copyright (C) 2013 Texas Instruments Incorporated - http://www.ti.com/ | |
6 | * | |
c7964f86 EBS |
7 | * For more details, please see the technical documents listed at |
8 | * http://www.ti.com/product/omap3530 | |
9 | * http://www.ti.com/product/omap3630 | |
10 | * http://www.ti.com/product/dm3730 | |
11 | */ | |
12 | ||
13 | #ifndef __CONFIG_TI_OMAP3_COMMON_H__ | |
14 | #define __CONFIG_TI_OMAP3_COMMON_H__ | |
15 | ||
3709844f AA |
16 | /* |
17 | * High Level Configuration Options | |
18 | */ | |
19 | ||
c7964f86 | 20 | #include <asm/arch/cpu.h> |
987ec585 | 21 | #include <asm/arch/omap.h> |
c7964f86 | 22 | |
c7964f86 EBS |
23 | /* Clock Defines */ |
24 | #define V_OSCK 26000000 /* Clock output from T2 */ | |
25 | #define V_SCLK (V_OSCK >> 1) | |
26 | ||
27 | /* NS16550 Configuration */ | |
28 | #define V_NS16550_CLK 48000000 /* 48MHz (APLL96/2) */ | |
c7b9686d | 29 | #define CONFIG_SYS_NS16550_CLK V_NS16550_CLK |
313ed5d5 | 30 | #if !defined(CONFIG_DM_SERIAL) |
750df197 | 31 | #define CONFIG_SYS_NS16550_SERIAL |
313ed5d5 DW |
32 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) |
33 | #endif /* !CONFIG_DM_SERIAL */ | |
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34 | #define CONFIG_SYS_BAUDRATE_TABLE {4800, 9600, 19200, 38400, 57600, \ |
35 | 115200} | |
36 | ||
37 | /* Select serial console configuration */ | |
b3f4ca11 | 38 | #ifdef CONFIG_SPL_BUILD |
bdaf24f8 AF |
39 | #define CONFIG_SYS_NS16550_COM1 OMAP34XX_UART1 |
40 | #define CONFIG_SYS_NS16550_COM2 OMAP34XX_UART2 | |
c7964f86 | 41 | #define CONFIG_SYS_NS16550_COM3 OMAP34XX_UART3 |
b3f4ca11 | 42 | #endif |
c7964f86 EBS |
43 | |
44 | /* Physical Memory Map */ | |
45 | #define PHYS_SDRAM_1 OMAP34XX_SDRC_CS0 | |
46 | #define PHYS_SDRAM_2 OMAP34XX_SDRC_CS1 | |
47 | ||
48 | /* | |
49 | * OMAP3 has 12 GP timers, they can be driven by the system clock | |
50 | * (12/13/16.8/19.2/38.4MHz) or by 32KHz clock. We use 13MHz (V_SCLK). | |
51 | * This rate is divided by a local divisor. | |
52 | */ | |
53 | #define CONFIG_SYS_TIMERBASE (OMAP34XX_GPT2) | |
54 | ||
55 | #define CONFIG_SYS_MONITOR_LEN (256 << 10) | |
56 | ||
c7964f86 | 57 | /* SPL */ |
d3289aac TR |
58 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
59 | (64 << 20)) | |
60 | ||
88718be3 | 61 | #ifdef CONFIG_MTD_RAW_NAND |
df4dbb5d | 62 | #define CONFIG_SYS_NAND_BASE 0x30000000 |
c7964f86 EBS |
63 | #endif |
64 | ||
65 | /* Now bring in the rest of the common code. */ | |
9a0f4004 | 66 | #include <configs/ti_armv7_omap.h> |
c7964f86 EBS |
67 | |
68 | #endif /* __CONFIG_TI_OMAP3_COMMON_H__ */ |