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3ef5ebeb LV |
1 | /* |
2 | * (C) Copyright 2013 | |
3 | * Texas Instruments Incorporated. | |
4 | * Sricharan R <r.sricharan@ti.com> | |
5 | * | |
6 | * Derived from OMAP4 done by: | |
7 | * Aneesh V <aneesh@ti.com> | |
8 | * | |
9 | * TI OMAP5 AND DRA7XX common configuration settings | |
10 | * | |
3765b3e7 | 11 | * SPDX-License-Identifier: GPL-2.0+ |
a8017574 TR |
12 | * |
13 | * For more details, please see the technical documents listed at | |
14 | * http://www.ti.com/product/omap5432 | |
3ef5ebeb LV |
15 | */ |
16 | ||
3d657a05 EBS |
17 | #ifndef __CONFIG_TI_OMAP5_COMMON_H |
18 | #define __CONFIG_TI_OMAP5_COMMON_H | |
3ef5ebeb | 19 | |
a8017574 TR |
20 | /* Use General purpose timer 1 */ |
21 | #define CONFIG_SYS_TIMERBASE GPT2_BASE | |
22 | ||
078aa4f1 TR |
23 | /* |
24 | * For the DDR timing information we can either dynamically determine | |
25 | * the timings to use or use pre-determined timings (based on using the | |
26 | * dynamic method. Default to the static timing infomation. | |
27 | */ | |
a8017574 | 28 | #define CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
a8017574 TR |
29 | #ifndef CONFIG_SYS_EMIF_PRECALCULATED_TIMING_REGS |
30 | #define CONFIG_SYS_AUTOMATIC_SDRAM_DETECTION | |
31 | #define CONFIG_SYS_DEFAULT_LPDDR2_TIMINGS | |
32 | #endif | |
33 | ||
a8017574 | 34 | #define CONFIG_PALMAS_POWER |
a8017574 TR |
35 | |
36 | #include <asm/arch/cpu.h> | |
37 | #include <asm/arch/omap.h> | |
3ef5ebeb | 38 | |
9a0f4004 | 39 | #include <configs/ti_armv7_omap.h> |
3ef5ebeb LV |
40 | |
41 | /* | |
a8017574 | 42 | * Hardware drivers |
3ef5ebeb | 43 | */ |
c7b9686d | 44 | #define CONFIG_SYS_NS16550_CLK 48000000 |
0a3f407a | 45 | #if !defined(CONFIG_DM_SERIAL) |
3ef5ebeb LV |
46 | #define CONFIG_SYS_NS16550_SERIAL |
47 | #define CONFIG_SYS_NS16550_REG_SIZE (-4) | |
01e870b7 | 48 | #endif |
3ef5ebeb | 49 | |
3ef5ebeb LV |
50 | /* |
51 | * Environment setup | |
52 | */ | |
9552ee3e | 53 | |
7a5a3e37 KVA |
54 | #ifndef DFUARGS |
55 | #define DFUARGS | |
56 | #endif | |
57 | ||
4fd79ac9 | 58 | #include <environment/ti/boot.h> |
88fdfcd2 SN |
59 | #include <environment/ti/mmc.h> |
60 | ||
4ec3f6e5 | 61 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG |
3ef5ebeb | 62 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
fb3ad9bd | 63 | DEFAULT_LINUX_BOOT_ENV \ |
85d17be3 | 64 | DEFAULT_MMC_TI_ARGS \ |
1e93cc84 | 65 | DEFAULT_FIT_TI_ARGS \ |
4fd79ac9 SP |
66 | DEFAULT_COMMON_BOOT_TI_ARGS \ |
67 | DEFAULT_FDT_TI_ARGS \ | |
7a5a3e37 | 68 | DFUARGS \ |
2320866b | 69 | NETARGS \ |
3ef5ebeb | 70 | |
078aa4f1 TR |
71 | /* |
72 | * SPL related defines. The Public RAM memory map the ROM defines the | |
b9b8403f DA |
73 | * area between 0x40300000 and 0x4031E000 as a download area for OMAP5. |
74 | * On DRA7xx/AM57XX the download area is between 0x40300000 and 0x4037E000. | |
75 | * We set CONFIG_SPL_DISPLAY_PRINT to have omap_rev_string() called and | |
078aa4f1 TR |
76 | * print some information. |
77 | */ | |
b9b8403f DA |
78 | #ifdef CONFIG_TI_SECURE_DEVICE |
79 | /* | |
80 | * For memory booting on HS parts, the first 4KB of the internal RAM is | |
81 | * reserved for secure world use and the flash loader image is | |
82 | * preceded by a secure certificate. The SPL will therefore run in internal | |
83 | * RAM from address 0x40301350 (0x40300000+0x1000(reserved)+0x350(cert)). | |
84 | */ | |
85 | #define TI_OMAP5_SECURE_BOOT_RESV_SRAM_SZ 0x1000 | |
86 | #define CONFIG_SPL_TEXT_BASE 0x40301350 | |
32d333f2 DA |
87 | /* If no specific start address is specified then the secure EMIF |
88 | * region will be placed at the end of the DDR space. In order to prevent | |
89 | * the main u-boot relocation from clobbering that memory and causing a | |
90 | * firewall violation, we tell u-boot that memory is protected RAM (PRAM) | |
91 | */ | |
92 | #if (CONFIG_TI_SECURE_EMIF_REGION_START == 0) | |
93 | #define CONFIG_PRAM (CONFIG_TI_SECURE_EMIF_TOTAL_REGION_SIZE) >> 10 | |
94 | #endif | |
b9b8403f DA |
95 | #else |
96 | /* | |
97 | * For all booting on GP parts, the flash loader image is | |
98 | * downloaded into internal RAM at address 0x40300000. | |
99 | */ | |
100 | #define CONFIG_SPL_TEXT_BASE 0x40300000 | |
101 | #endif | |
102 | ||
d3289aac TR |
103 | #define CONFIG_SYS_SPL_ARGS_ADDR (CONFIG_SYS_SDRAM_BASE + \ |
104 | (128 << 20)) | |
3ef5ebeb | 105 | |
136b1013 | 106 | #ifdef CONFIG_SPL_BUILD |
30a0cdb6 | 107 | #undef CONFIG_TIMER |
136b1013 M |
108 | #endif |
109 | ||
3d657a05 | 110 | #endif /* __CONFIG_TI_OMAP5_COMMON_H */ |