[people/ms/u-boot.git] / include / configs / trats.h

/*
 * Copyright (C) 2011 Samsung Electronics
 * Heungjun Kim <riverful.kim@samsung.com>
 *
 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
 *
 * SPDX-License-Identifier:	GPL-2.0+
 */

#ifndef __CONFIG_TRATS_H
#define __CONFIG_TRATS_H

#include <configs/exynos4-common.h>

#define CONFIG_SYS_PROMPT	"Trats # "	/* Monitor Command Prompt */

#define CONFIG_TRATS


#define CONFIG_TIZEN			/* TIZEN lib */

#define CONFIG_SYS_L2CACHE_OFF
#ifndef CONFIG_SYS_L2CACHE_OFF
#define CONFIG_SYS_L2_PL310
#define CONFIG_SYS_PL310_BASE	0x10502000
#endif

/* TRATS has 4 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS		4
#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define PHYS_SDRAM_1			CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_TEXT_BASE		0x63300000
#define SDRAM_BANK_SIZE			(256 << 20)	/* 256 MB */

/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)

#define CONFIG_SYS_TEXT_BASE		0x63300000

/* select serial console configuration */
#define CONFIG_SERIAL2
#define CONFIG_BAUDRATE			115200

/* Console configuration */
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
#define MACH_TYPE_TRATS			3928
#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS

#define CONFIG_FIT
#define CONFIG_FIT_VERBOSE
#define CONFIG_BOOTARGS			"Please use defined boot"
#define CONFIG_BOOTCOMMAND		"run autoboot"
#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR \
					- GENERATED_GBL_DATA_SIZE)

#define CONFIG_SYS_MEM_TOP_HIDE	(1 << 20)	/* ram console */

#define CONFIG_SYS_MONITOR_BASE	0x00000000

#define CONFIG_BOOTBLOCK		"10"
#define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"

#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		CONFIG_MMC_DEFAULT_DEV
#define CONFIG_ENV_SIZE			4096
#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */

#define CONFIG_ENV_OVERWRITE

#define CONFIG_ENV_VARS_UBOOT_CONFIG
#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG

/* Tizen - partitions definitions */
#define PARTS_CSA		"csa-mmc"
#define PARTS_BOOT		"boot"
#define PARTS_QBOOT		"qboot"
#define PARTS_CSC		"csc"
#define PARTS_ROOT		"platform"
#define PARTS_DATA		"data"
#define PARTS_UMS		"ums"

#define PARTS_DEFAULT \
	"uuid_disk=${uuid_gpt_disk};" \
	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \

#define CONFIG_DFU_ALT \
	"u-boot raw 0x80 0x400;" \
	"/uImage ext4 0 2;" \
	"/modem.bin ext4 0 2;" \
	"/exynos4210-trats.dtb ext4 0 2;" \
	""PARTS_CSA" part 0 1;" \
	""PARTS_BOOT" part 0 2;" \
	""PARTS_QBOOT" part 0 3;" \
	""PARTS_CSC" part 0 4;" \
	""PARTS_ROOT" part 0 5;" \
	""PARTS_DATA" part 0 6;" \
	""PARTS_UMS" part 0 7;" \
	"params.bin raw 0x38 0x8;" \
	"/Image.itb ext4 0 2\0"

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootk=" \
		"run loaduimage;" \
		"if run loaddtb; then " \
			"bootm 0x40007FC0 - ${fdtaddr};" \
		"fi;" \
		"bootm 0x40007FC0;\0" \
	"updatebackup=" \
		"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
		"mmc dev 0 0\0" \
	"updatebootb=" \
		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	"lpj=lpj=3981312\0" \
	"nfsboot=" \
		"setenv bootargs root=/dev/nfs rw " \
		"nfsroot=${nfsroot},nolock,tcp " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
		"; run bootk\0" \
	"ramfsboot=" \
		"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
		"${console} ${meminfo} " \
		"initrd=0x43000000,8M ramdisk=8192\0" \
	"mmcboot=" \
		"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
		"run bootk\0" \
	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	"verify=n\0" \
	"rootfstype=ext4\0" \
	"console=" CONFIG_DEFAULT_CONSOLE \
	"meminfo=crashkernel=32M@0x50000000\0" \
	"nfsroot=/nfsroot/arm\0" \
	"bootblock=" CONFIG_BOOTBLOCK "\0" \
	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
		"${fdtfile}\0" \
	"mmcdev=0\0" \
	"mmcbootpart=2\0" \
	"mmcrootpart=5\0" \
	"opts=always_resume=1\0" \
	"partitions=" PARTS_DEFAULT \
	"dfu_alt_info=" CONFIG_DFU_ALT \
	"spladdr=0x40000100\0" \
	"splsize=0x200\0" \
	"splfile=falcon.bin\0" \
	"spl_export=" \
		   "setexpr spl_imgsize ${splsize} + 8 ;" \
		   "setenv spl_imgsize 0x${spl_imgsize};" \
		   "setexpr spl_imgaddr ${spladdr} - 8 ;" \
		   "setexpr spl_addr_tmp ${spladdr} - 4 ;" \
		   "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
		   "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		   "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
		   "spl export atags 0x40007FC0;" \
		   "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
		   "mw.l ${spl_addr_tmp} ${splsize};" \
		   "ext4write mmc ${mmcdev}:${mmcbootpart}" \
		   " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
		   "setenv spl_imgsize;" \
		   "setenv spl_imgaddr;" \
		   "setenv spl_addr_tmp;\0" \
	CONFIG_EXTRA_ENV_ITB \
	"fdtaddr=40800000\0" \

/* Falcon mode definitions */
#define CONFIG_CMD_SPL
#define CONFIG_SYS_SPL_ARGS_ADDR        CONFIG_SYS_SDRAM_BASE + 0x100

/* GPT */
#define CONFIG_RANDOM_UUID

/* I2C */
#include <asm/arch/gpio.h>

#define CONFIG_CMD_I2C

#define CONFIG_SYS_I2C
#define CONFIG_SYS_I2C_S3C24X0
#define CONFIG_SYS_I2C_S3C24X0_SPEED	100000
#define CONFIG_SYS_I2C_S3C24X0_SLAVE	0xFE
#define CONFIG_MAX_I2C_NUM		8
#define CONFIG_SYS_I2C_SOFT		/* I2C bit-banged */
#define CONFIG_SYS_I2C_SOFT_SPEED	50000
#define CONFIG_SYS_I2C_SOFT_SLAVE	0x7F
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_INIT_BOARD

/* I2C FG */
#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40

/* POWER */
#define CONFIG_POWER
#define CONFIG_POWER_I2C
#define CONFIG_POWER_MAX8997

#define CONFIG_POWER_FG
#define CONFIG_POWER_FG_MAX17042
#define CONFIG_POWER_MUIC
#define CONFIG_POWER_MUIC_MAX8997
#define CONFIG_POWER_BATTERY
#define CONFIG_POWER_BATTERY_TRATS

/* Security subsystem - enable hw_rand() */
#define CONFIG_EXYNOS_ACE_SHA
#define CONFIG_LIB_HW_RAND

/* Common misc for Samsung */
#define CONFIG_MISC_COMMON

#define CONFIG_MISC_INIT_R

/* Download menu - Samsung common */
#define CONFIG_LCD_MENU
#define CONFIG_LCD_MENU_BOARD

/* Download menu - definitions for check keys */
#ifndef __ASSEMBLY__
#include <power/max8997_pmic.h>

#define KEY_PWR_PMIC_NAME		"MAX8997_PMIC"
#define KEY_PWR_STATUS_REG		MAX8997_REG_STATUS1
#define KEY_PWR_STATUS_MASK		(1 << 0)
#define KEY_PWR_INTERRUPT_REG		MAX8997_REG_INT1
#define KEY_PWR_INTERRUPT_MASK		(1 << 0)

#define KEY_VOL_UP_GPIO			EXYNOS4_GPIO_X20
#define KEY_VOL_DOWN_GPIO		EXYNOS4_GPIO_X21
#endif /* __ASSEMBLY__ */

/* LCD console */
#define LCD_BPP			LCD_COLOR16
#define CONFIG_SYS_WHITE_ON_BLACK

/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_16BPP
#define CONFIG_FB_ADDR		0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE  ((500 * 160 * 4) + 54)

#endif	/* __CONFIG_H */
Commit	Line	Data
89f95492 HK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	* Heungjun Kim <riverful.kim@samsung.com>
	4	*
	5	* Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
	6	*
1a459660	7	* SPDX-License-Identifier: GPL-2.0+
89f95492 HK	8	*/
89f95492 HK	9
fe601647 PW	10	#ifndef __CONFIG_TRATS_H
fe601647 PW	11	#define __CONFIG_TRATS_H
89f95492	12
4c7bb1d2	13	#include <configs/exynos4-common.h>
fe601647 PW	14
	15	#define CONFIG_SYS_PROMPT "Trats # " /* Monitor Command Prompt */
	16
	17	#define CONFIG_TRATS
89f95492	18
89f95492	19
fe601647	20	#define CONFIG_TIZEN /* TIZEN lib */
89f95492	21
c4e96dbf	22	#define CONFIG_SYS_L2CACHE_OFF
d0460b01 ŁM	23	#ifndef CONFIG_SYS_L2CACHE_OFF
	24	#define CONFIG_SYS_L2_PL310
	25	#define CONFIG_SYS_PL310_BASE 0x10502000
	26	#endif
89f95492	27
fe601647 PW	28	/* TRATS has 4 banks of DRAM */
fe601647 PW	29	#define CONFIG_NR_DRAM_BANKS 4
89f95492	30	#define CONFIG_SYS_SDRAM_BASE 0x40000000
fe601647	31	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE
89f95492	32	#define CONFIG_SYS_TEXT_BASE 0x63300000
fe601647	33	#define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */
89f95492	34
fe601647 PW	35	/* memtest works on */
	36	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	37	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
	38	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
89f95492	39
fe601647	40	#define CONFIG_SYS_TEXT_BASE 0x63300000
89f95492	41
89f95492	42	/* select serial console configuration */
fe601647	43	#define CONFIG_SERIAL2
89f95492 HK	44	#define CONFIG_BAUDRATE 115200
89f95492 HK	45
fe601647 PW	46	/* Console configuration */
	47	#define CONFIG_SYS_CONSOLE_INFO_QUIET
	48	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	49
	50	/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
	51	#define MACH_TYPE_TRATS 3928
	52	#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
	53
0a1387bf ŁM	54	#define CONFIG_FIT
0a1387bf ŁM	55	#define CONFIG_FIT_VERBOSE
89f95492	56	#define CONFIG_BOOTARGS "Please use defined boot"
0a1387bf	57	#define CONFIG_BOOTCOMMAND "run autoboot"
6afc3f6e	58	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
fe601647 PW	59
	60	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \
	61	- GENERATED_GBL_DATA_SIZE)
	62
	63	#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
	64
	65	#define CONFIG_SYS_MONITOR_BASE 0x00000000
89f95492	66
89f95492 HK	67	#define CONFIG_BOOTBLOCK "10"
	68	#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
	69
fe601647 PW	70	#define CONFIG_ENV_IS_IN_MMC
	71	#define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV
	72	#define CONFIG_ENV_SIZE 4096
	73	#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
	74
	75	#define CONFIG_ENV_OVERWRITE
	76
	77	#define CONFIG_ENV_VARS_UBOOT_CONFIG
	78	#define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG
	79
9960d9a8 ŁM	80	/* Tizen - partitions definitions */
9960d9a8 ŁM	81	#define PARTS_CSA "csa-mmc"
9960d9a8	82	#define PARTS_BOOT "boot"
18f3e0eb PM	83	#define PARTS_QBOOT "qboot"
18f3e0eb PM	84	#define PARTS_CSC "csc"
9960d9a8 ŁM	85	#define PARTS_ROOT "platform"
9960d9a8 ŁM	86	#define PARTS_DATA "data"
9960d9a8 ŁM	87	#define PARTS_UMS "ums"
	88
	89	#define PARTS_DEFAULT \
	90	"uuid_disk=${uuid_gpt_disk};" \
18f3e0eb PM	91	"name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \
	92	"name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \
	93	"name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \
9960d9a8	94	"name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \
18f3e0eb PM	95	"name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \
18f3e0eb PM	96	"name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \
9960d9a8 ŁM	97	"name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \
9960d9a8 ŁM	98
93a1ab57	99	#define CONFIG_DFU_ALT \
b7d4259a	100	"u-boot raw 0x80 0x400;" \
dcb7eb66 ŁM	101	"/uImage ext4 0 2;" \
	102	"/modem.bin ext4 0 2;" \
	103	"/exynos4210-trats.dtb ext4 0 2;" \
18f3e0eb	104	""PARTS_CSA" part 0 1;" \
cdd15bce	105	""PARTS_BOOT" part 0 2;" \
18f3e0eb PM	106	""PARTS_QBOOT" part 0 3;" \
18f3e0eb PM	107	""PARTS_CSC" part 0 4;" \
cdd15bce ŁM	108	""PARTS_ROOT" part 0 5;" \
cdd15bce ŁM	109	""PARTS_DATA" part 0 6;" \
a0afc6f3	110	""PARTS_UMS" part 0 7;" \
0a1387bf ŁM	111	"params.bin raw 0x38 0x8;" \
0a1387bf ŁM	112	"/Image.itb ext4 0 2\0"
93a1ab57	113
89f95492 HK	114	#define CONFIG_EXTRA_ENV_SETTINGS \
89f95492 HK	115	"bootk=" \
425e26de PW	116	"run loaduimage;" \
	117	"if run loaddtb; then " \
	118	"bootm 0x40007FC0 - ${fdtaddr};" \
	119	"fi;" \
	120	"bootm 0x40007FC0;\0" \
89f95492	121	"updatebackup=" \
188c42b3 JC	122	"mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \
188c42b3 JC	123	"mmc dev 0 0\0" \
89f95492 HK	124	"updatebootb=" \
	125	"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	126	"lpj=lpj=3981312\0" \
	127	"nfsboot=" \
35777e22	128	"setenv bootargs root=/dev/nfs rw " \
89f95492 HK	129	"nfsroot=${nfsroot},nolock,tcp " \
	130	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	131	"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
	132	"; run bootk\0" \
	133	"ramfsboot=" \
35777e22	134	"setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \
89f95492 HK	135	"${console} ${meminfo} " \
	136	"initrd=0x43000000,8M ramdisk=8192\0" \
	137	"mmcboot=" \
35777e22	138	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
89f95492	139	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
425e26de	140	"run bootk\0" \
35777e22	141	"bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \
89f95492 HK	142	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	143	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	144	"verify=n\0" \
	145	"rootfstype=ext4\0" \
	146	"console=" CONFIG_DEFAULT_CONSOLE \
	147	"meminfo=crashkernel=32M@0x50000000\0" \
	148	"nfsroot=/nfsroot/arm\0" \
	149	"bootblock=" CONFIG_BOOTBLOCK "\0" \
35777e22	150	"loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \
4ef400b9	151	"loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \
ba223bb2	152	"${fdtfile}\0" \
89f95492 HK	153	"mmcdev=0\0" \
89f95492 HK	154	"mmcbootpart=2\0" \
35777e22	155	"mmcrootpart=5\0" \
93a1ab57	156	"opts=always_resume=1\0" \
9960d9a8	157	"partitions=" PARTS_DEFAULT \
35777e22 ŁM	158	"dfu_alt_info=" CONFIG_DFU_ALT \
	159	"spladdr=0x40000100\0" \
	160	"splsize=0x200\0" \
	161	"splfile=falcon.bin\0" \
	162	"spl_export=" \
	163	"setexpr spl_imgsize ${splsize} + 8 ;" \
dc993a65	164	"setenv spl_imgsize 0x${spl_imgsize};" \
35777e22 ŁM	165	"setexpr spl_imgaddr ${spladdr} - 8 ;" \
	166	"setexpr spl_addr_tmp ${spladdr} - 4 ;" \
	167	"mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \
	168	"setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
	169	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \
	170	"spl export atags 0x40007FC0;" \
	171	"crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \
	172	"mw.l ${spl_addr_tmp} ${splsize};" \
	173	"ext4write mmc ${mmcdev}:${mmcbootpart}" \
	174	" /${splfile} ${spl_imgaddr} ${spl_imgsize};" \
	175	"setenv spl_imgsize;" \
	176	"setenv spl_imgaddr;" \
ba223bb2	177	"setenv spl_addr_tmp;\0" \
0a1387bf	178	CONFIG_EXTRA_ENV_ITB \
ba223bb2	179	"fdtaddr=40800000\0" \
ba223bb2	180
35777e22 ŁM	181	/* Falcon mode definitions */
35777e22 ŁM	182	#define CONFIG_CMD_SPL
fe601647	183	#define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100
89f95492	184
9960d9a8	185	/* GPT */
aafd2c5d	186	#define CONFIG_RANDOM_UUID
9960d9a8	187
fe601647 PW	188	/* I2C */
fe601647 PW	189	#include <asm/arch/gpio.h>
9960d9a8	190
fe601647	191	#define CONFIG_CMD_I2C
89f95492	192
ea818dbb	193	#define CONFIG_SYS_I2C
2d8f1e27 PW	194	#define CONFIG_SYS_I2C_S3C24X0
	195	#define CONFIG_SYS_I2C_S3C24X0_SPEED 100000
	196	#define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE
	197	#define CONFIG_MAX_I2C_NUM 8
ea818dbb HS	198	#define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */
ea818dbb HS	199	#define CONFIG_SYS_I2C_SOFT_SPEED 50000
2d8f1e27	200	#define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F
89f95492	201	#define CONFIG_SOFT_I2C_READ_REPEATED_START
fd8dca83	202	#define CONFIG_SYS_I2C_INIT_BOARD
fd8dca83	203
fd8dca83	204	/* I2C FG */
9b97b727 AS	205	#define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41
9b97b727 AS	206	#define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40
89f95492	207
fe601647	208	/* POWER */
be3b51aa ŁM	209	#define CONFIG_POWER
	210	#define CONFIG_POWER_I2C
	211	#define CONFIG_POWER_MAX8997
89f95492	212
5a77358c ŁM	213	#define CONFIG_POWER_FG
5a77358c ŁM	214	#define CONFIG_POWER_FG_MAX17042
7dcda99d ŁM	215	#define CONFIG_POWER_MUIC
7dcda99d ŁM	216	#define CONFIG_POWER_MUIC_MAX8997
61365ffc ŁM	217	#define CONFIG_POWER_BATTERY
61365ffc ŁM	218	#define CONFIG_POWER_BATTERY_TRATS
89f95492	219
e0021706 PM	220	/* Security subsystem - enable hw_rand() */
	221	#define CONFIG_EXYNOS_ACE_SHA
	222	#define CONFIG_LIB_HW_RAND
	223
679549d1 PM	224	/* Common misc for Samsung */
	225	#define CONFIG_MISC_COMMON
	226
	227	#define CONFIG_MISC_INIT_R
	228
00e64ab6 PM	229	/* Download menu - Samsung common */
	230	#define CONFIG_LCD_MENU
	231	#define CONFIG_LCD_MENU_BOARD
	232
	233	/* Download menu - definitions for check keys */
	234	#ifndef __ASSEMBLY__
	235	#include <power/max8997_pmic.h>
	236
	237	#define KEY_PWR_PMIC_NAME "MAX8997_PMIC"
	238	#define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1
	239	#define KEY_PWR_STATUS_MASK (1 << 0)
	240	#define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1
	241	#define KEY_PWR_INTERRUPT_MASK (1 << 0)
	242
9b97b727 AS	243	#define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20
9b97b727 AS	244	#define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21
00e64ab6 PM	245	#endif /* __ASSEMBLY__ */
	246
	247	/* LCD console */
	248	#define LCD_BPP LCD_COLOR16
	249	#define CONFIG_SYS_WHITE_ON_BLACK
	250
51b1cd6d DL	251	/* LCD */
	252	#define CONFIG_EXYNOS_FB
	253	#define CONFIG_LCD
90464971	254	#define CONFIG_CMD_BMP
2df21cb3	255	#define CONFIG_BMP_16BPP
51b1cd6d DL	256	#define CONFIG_FB_ADDR 0x52504000
	257	#define CONFIG_S6E8AX0
	258	#define CONFIG_EXYNOS_MIPI_DSIM
90464971	259	#define CONFIG_VIDEO_BMP_GZIP
903afe18	260	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54)
51b1cd6d	261
89f95492	262	#endif /* __CONFIG_H */