[people/ms/u-boot.git] / include / configs / trats.h

/*
 * Copyright (C) 2011 Samsung Electronics
 * Heungjun Kim <riverful.kim@samsung.com>
 *
 * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
 *
 * See file CREDITS for list of people who contributed to this
 * project.
 *
 * This program is free software; you can redistribute it and/or
 * modify it under the terms of the GNU General Public License as
 * published by the Free Software Foundation; either version 2 of
 * the License, or (at your option) any later version.
 *
 * This program is distributed in the hope that it will be useful,
 * but WITHOUT ANY WARRANTY; without even the implied warranty of
 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 * GNU General Public License for more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program; if not, write to the Free Software
 * Foundation, Inc., 59 Temple Place, Suite 330, Boston,
 * MA 02111-1307 USA
 */

#ifndef __CONFIG_H
#define __CONFIG_H

/*
 * High Level Configuration Options
 * (easy to change)
 */
#define CONFIG_SAMSUNG		/* in a SAMSUNG core */
#define CONFIG_S5P		/* which is in a S5P Family */
#define CONFIG_EXYNOS4210	/* which is in a EXYNOS4210 */
#define CONFIG_TRATS		/* working with TRATS */
#define CONFIG_TIZEN		/* TIZEN lib */

#include <asm/arch/cpu.h>	/* get chip and board defs */

#define CONFIG_ARCH_CPU_INIT
#define CONFIG_DISPLAY_CPUINFO
#define CONFIG_DISPLAY_BOARDINFO

/* Keep L2 Cache Disabled */
#define CONFIG_SYS_L2CACHE_OFF

#define CONFIG_SYS_SDRAM_BASE		0x40000000
#define CONFIG_SYS_TEXT_BASE		0x63300000

/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
#define CONFIG_SYS_CLK_FREQ_C210	24000000
#define CONFIG_SYS_CLK_FREQ		CONFIG_SYS_CLK_FREQ_C210

#define CONFIG_SETUP_MEMORY_TAGS
#define CONFIG_CMDLINE_TAG
#define CONFIG_REVISION_TAG
#define CONFIG_CMDLINE_EDITING
#define CONFIG_SKIP_LOWLEVEL_INIT
#define CONFIG_BOARD_EARLY_INIT_F

/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
#define MACH_TYPE_TRATS			3928
#define CONFIG_MACH_TYPE		MACH_TYPE_TRATS

/* Size of malloc() pool */
#define CONFIG_SYS_MALLOC_LEN		(CONFIG_ENV_SIZE + (1 << 20))

/* select serial console configuration */
#define CONFIG_SERIAL_MULTI
#define CONFIG_SERIAL2			/* use SERIAL 2 */
#define CONFIG_BAUDRATE			115200

/* MMC */
#define CONFIG_GENERIC_MMC
#define CONFIG_MMC
#define CONFIG_S5P_SDHCI
#define CONFIG_SDHCI

/* PWM */
#define CONFIG_PWM

/* It should define before config_cmd_default.h */
#define CONFIG_SYS_NO_FLASH

/* Command definition */
#include <config_cmd_default.h>

#undef CONFIG_CMD_FPGA
#undef CONFIG_CMD_MISC
#undef CONFIG_CMD_NET
#undef CONFIG_CMD_NFS
#undef CONFIG_CMD_XIMG
#undef CONFIG_CMD_CACHE
#undef CONFIG_CMD_ONENAND
#undef CONFIG_CMD_MTDPARTS
#define CONFIG_CMD_MMC

#define CONFIG_BOOTDELAY		1
#define CONFIG_ZERO_BOOTDELAY_CHECK
#define CONFIG_BOOTARGS			"Please use defined boot"
#define CONFIG_BOOTCOMMAND		"run mmcboot"

#define CONFIG_DEFAULT_CONSOLE		"console=ttySAC2,115200n8\0"
#define CONFIG_BOOTBLOCK		"10"
#define CONFIG_ENV_COMMON_BOOT		"${console} ${meminfo}"

#define CONFIG_ENV_OVERWRITE
#define CONFIG_SYS_CONSOLE_INFO_QUIET
#define CONFIG_SYS_CONSOLE_IS_IN_ENV

#define CONFIG_EXTRA_ENV_SETTINGS \
	"bootk=" \
		"run loaduimage; bootm 0x40007FC0\0" \
	"updatemmc=" \
		"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
		"mmc boot 0 1 1 0\0" \
	"updatebackup=" \
		"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
		"mmc boot 0 1 1 0\0" \
	"updatebootb=" \
		"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	"lpj=lpj=3981312\0" \
	"nfsboot=" \
		"set bootargs root=/dev/nfs rw " \
		"nfsroot=${nfsroot},nolock,tcp " \
		"ip=${ipaddr}:${serverip}:${gatewayip}:" \
		"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
		"; run bootk\0" \
	"ramfsboot=" \
		"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
		"${console} ${meminfo} " \
		"initrd=0x43000000,8M ramdisk=8192\0" \
	"mmcboot=" \
		"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
		"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
		"run loaduimage; bootm 0x40007FC0\0" \
	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	"verify=n\0" \
	"rootfstype=ext4\0" \
	"console=" CONFIG_DEFAULT_CONSOLE \
	"meminfo=crashkernel=32M@0x50000000\0" \
	"nfsroot=/nfsroot/arm\0" \
	"bootblock=" CONFIG_BOOTBLOCK "\0" \
	"mmcdev=0\0" \
	"mmcbootpart=2\0" \
	"mmcrootpart=3\0" \
	"opts=always_resume=1"

/* Miscellaneous configurable options */
#define CONFIG_SYS_LONGHELP		/* undef to save memory */
#define CONFIG_SYS_HUSH_PARSER		/* use "hush" command parser */
#define CONFIG_SYS_PROMPT		"TRATS # "
#define CONFIG_SYS_CBSIZE		256	/* Console I/O Buffer Size */
#define CONFIG_SYS_PBSIZE		384	/* Print Buffer Size */
#define CONFIG_SYS_MAXARGS		16	/* max number of command args */
/* Boot Argument Buffer Size */
#define CONFIG_SYS_BARGSIZE		CONFIG_SYS_CBSIZE
/* memtest works on */
#define CONFIG_SYS_MEMTEST_START	CONFIG_SYS_SDRAM_BASE
#define CONFIG_SYS_MEMTEST_END		(CONFIG_SYS_SDRAM_BASE + 0x5000000)
#define CONFIG_SYS_LOAD_ADDR		(CONFIG_SYS_SDRAM_BASE + 0x4800000)

#define CONFIG_SYS_HZ			1000

/* Stack sizes */
#define CONFIG_STACKSIZE		(256 << 10) /* regular stack 256KB */

/* TRATS has 2 banks of DRAM */
#define CONFIG_NR_DRAM_BANKS	2
#define PHYS_SDRAM_1		CONFIG_SYS_SDRAM_BASE	/* LDDDR2 DMC 0 */
#define PHYS_SDRAM_1_SIZE	(512 << 20)		/* 512 MB in CS 0 */
#define PHYS_SDRAM_2		0x50000000		/* LPDDR2 DMC 1 */
#define PHYS_SDRAM_2_SIZE	(512 << 20)		/* 512 MB in CS 0 */

#define CONFIG_SYS_MEM_TOP_HIDE		(1 << 20)	/* ram console */

#define CONFIG_SYS_MONITOR_BASE		0x00000000
#define CONFIG_SYS_MONITOR_LEN		(256 << 10)	/* Reserve 2 sectors */

#define CONFIG_ENV_IS_IN_MMC
#define CONFIG_SYS_MMC_ENV_DEV		0
#define CONFIG_ENV_SIZE			4096
#define CONFIG_ENV_OFFSET		((32 - 4) << 10) /* 32KiB - 4KiB */

#define CONFIG_DOS_PARTITION

#define CONFIG_SYS_INIT_SP_ADDR	(CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
#define CONFIG_SYS_CACHELINE_SIZE       32

#include <asm/arch/gpio.h>
/*
 * I2C Settings
 */
#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)

#define CONFIG_SOFT_I2C
#define CONFIG_SOFT_I2C_READ_REPEATED_START
#define CONFIG_SYS_I2C_SPEED	50000
#define CONFIG_I2C_MULTI_BUS
#define CONFIG_SYS_MAX_I2C_BUS	7

#define CONFIG_PMIC
#define CONFIG_PMIC_I2C
#define CONFIG_PMIC_MAX8997

#define CONFIG_USB_GADGET
#define CONFIG_USB_GADGET_S3C_UDC_OTG
#define CONFIG_USB_GADGET_DUALSPEED

/* LCD */
#define CONFIG_EXYNOS_FB
#define CONFIG_LCD
#define CONFIG_CMD_BMP
#define CONFIG_BMP_32BPP
#define CONFIG_FB_ADDR		0x52504000
#define CONFIG_S6E8AX0
#define CONFIG_EXYNOS_MIPI_DSIM
#define CONFIG_VIDEO_BMP_GZIP
#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))

#endif	/* __CONFIG_H */
Commit	Line	Data
89f95492 HK	1	/*
	2	* Copyright (C) 2011 Samsung Electronics
	3	* Heungjun Kim <riverful.kim@samsung.com>
	4	*
	5	* Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board.
	6	*
	7	* See file CREDITS for list of people who contributed to this
	8	* project.
	9	*
	10	* This program is free software; you can redistribute it and/or
	11	* modify it under the terms of the GNU General Public License as
	12	* published by the Free Software Foundation; either version 2 of
	13	* the License, or (at your option) any later version.
	14	*
	15	* This program is distributed in the hope that it will be useful,
	16	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	17	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	18	* GNU General Public License for more details.
	19	*
	20	* You should have received a copy of the GNU General Public License
	21	* along with this program; if not, write to the Free Software
	22	* Foundation, Inc., 59 Temple Place, Suite 330, Boston,
	23	* MA 02111-1307 USA
	24	*/
	25
	26	#ifndef __CONFIG_H
	27	#define __CONFIG_H
	28
	29	/*
	30	* High Level Configuration Options
	31	* (easy to change)
	32	*/
	33	#define CONFIG_SAMSUNG /* in a SAMSUNG core */
	34	#define CONFIG_S5P /* which is in a S5P Family */
	35	#define CONFIG_EXYNOS4210 /* which is in a EXYNOS4210 */
	36	#define CONFIG_TRATS /* working with TRATS */
90464971	37	#define CONFIG_TIZEN /* TIZEN lib */
89f95492 HK	38
	39	#include <asm/arch/cpu.h> /* get chip and board defs */
	40
	41	#define CONFIG_ARCH_CPU_INIT
	42	#define CONFIG_DISPLAY_CPUINFO
	43	#define CONFIG_DISPLAY_BOARDINFO
	44
	45	/* Keep L2 Cache Disabled */
	46	#define CONFIG_SYS_L2CACHE_OFF
	47
	48	#define CONFIG_SYS_SDRAM_BASE 0x40000000
	49	#define CONFIG_SYS_TEXT_BASE 0x63300000
	50
	51	/* input clock of PLL: TRATS has 24MHz input clock at EXYNOS4210 */
	52	#define CONFIG_SYS_CLK_FREQ_C210 24000000
5e46f83c	53	#define CONFIG_SYS_CLK_FREQ CONFIG_SYS_CLK_FREQ_C210
89f95492 HK	54
	55	#define CONFIG_SETUP_MEMORY_TAGS
	56	#define CONFIG_CMDLINE_TAG
89f95492 HK	57	#define CONFIG_REVISION_TAG
	58	#define CONFIG_CMDLINE_EDITING
	59	#define CONFIG_SKIP_LOWLEVEL_INIT
	60	#define CONFIG_BOARD_EARLY_INIT_F
	61
	62	/* MACH_TYPE_TRATS macro will be removed once added to mach-types */
	63	#define MACH_TYPE_TRATS 3928
	64	#define CONFIG_MACH_TYPE MACH_TYPE_TRATS
	65
	66	/* Size of malloc() pool */
	67	#define CONFIG_SYS_MALLOC_LEN (CONFIG_ENV_SIZE + (1 << 20))
	68
	69	/* select serial console configuration */
	70	#define CONFIG_SERIAL_MULTI
	71	#define CONFIG_SERIAL2 /* use SERIAL 2 */
	72	#define CONFIG_BAUDRATE 115200
	73
	74	/* MMC */
	75	#define CONFIG_GENERIC_MMC
	76	#define CONFIG_MMC
7d2d58b4 JC	77	#define CONFIG_S5P_SDHCI
7d2d58b4 JC	78	#define CONFIG_SDHCI
89f95492 HK	79
	80	/* PWM */
	81	#define CONFIG_PWM
	82
	83	/* It should define before config_cmd_default.h */
	84	#define CONFIG_SYS_NO_FLASH
	85
	86	/* Command definition */
	87	#include <config_cmd_default.h>
	88
	89	#undef CONFIG_CMD_FPGA
	90	#undef CONFIG_CMD_MISC
	91	#undef CONFIG_CMD_NET
	92	#undef CONFIG_CMD_NFS
	93	#undef CONFIG_CMD_XIMG
	94	#undef CONFIG_CMD_CACHE
	95	#undef CONFIG_CMD_ONENAND
	96	#undef CONFIG_CMD_MTDPARTS
	97	#define CONFIG_CMD_MMC
	98
	99	#define CONFIG_BOOTDELAY 1
	100	#define CONFIG_ZERO_BOOTDELAY_CHECK
	101	#define CONFIG_BOOTARGS "Please use defined boot"
	102	#define CONFIG_BOOTCOMMAND "run mmcboot"
	103
	104	#define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0"
	105	#define CONFIG_BOOTBLOCK "10"
	106	#define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}"
	107
	108	#define CONFIG_ENV_OVERWRITE
	109	#define CONFIG_SYS_CONSOLE_INFO_QUIET
	110	#define CONFIG_SYS_CONSOLE_IS_IN_ENV
	111
	112	#define CONFIG_EXTRA_ENV_SETTINGS \
	113	"bootk=" \
	114	"run loaduimage; bootm 0x40007FC0\0" \
	115	"updatemmc=" \
	116	"mmc boot 0 1 1 1; mmc write 0 0x42008000 0 0x200;" \
	117	"mmc boot 0 1 1 0\0" \
	118	"updatebackup=" \
	119	"mmc boot 0 1 1 2; mmc write 0 0x42100000 0 0x200;" \
	120	"mmc boot 0 1 1 0\0" \
	121	"updatebootb=" \
	122	"mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \
	123	"lpj=lpj=3981312\0" \
	124	"nfsboot=" \
	125	"set bootargs root=/dev/nfs rw " \
	126	"nfsroot=${nfsroot},nolock,tcp " \
	127	"ip=${ipaddr}:${serverip}:${gatewayip}:" \
	128	"${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \
	129	"; run bootk\0" \
	130	"ramfsboot=" \
	131	"set bootargs root=/dev/ram0 rw rootfstype=ext2 " \
	132	"${console} ${meminfo} " \
	133	"initrd=0x43000000,8M ramdisk=8192\0" \
	134	"mmcboot=" \
	135	"set bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \
	136	"${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \
	137	"run loaduimage; bootm 0x40007FC0\0" \
	138	"bootchart=set opts init=/sbin/bootchartd; run bootcmd\0" \
	139	"boottrace=setenv opts initcall_debug; run bootcmd\0" \
	140	"mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \
	141	"verify=n\0" \
	142	"rootfstype=ext4\0" \
143	"console=" CONFIG_DEFAULT_CONSOLE \
144	"meminfo=crashkernel=32M@0x50000000\0" \
145	"nfsroot=/nfsroot/arm\0" \
146	"bootblock=" CONFIG_BOOTBLOCK "\0" \
147	"mmcdev=0\0" \
148	"mmcbootpart=2\0" \
149	"mmcrootpart=3\0" \
150	"opts=always_resume=1"
151
152	/* Miscellaneous configurable options */
153	#define CONFIG_SYS_LONGHELP /* undef to save memory */
154	#define CONFIG_SYS_HUSH_PARSER /* use "hush" command parser */
89f95492 HK	155	#define CONFIG_SYS_PROMPT "TRATS # "
	156	#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */
	157	#define CONFIG_SYS_PBSIZE 384 /* Print Buffer Size */
	158	#define CONFIG_SYS_MAXARGS 16 /* max number of command args */
	159	/* Boot Argument Buffer Size */
	160	#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE
	161	/* memtest works on */
	162	#define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE
	163	#define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000)
	164	#define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000)
	165
	166	#define CONFIG_SYS_HZ 1000
	167
89f95492 HK	168	/* Stack sizes */
	169	#define CONFIG_STACKSIZE (256 << 10) /* regular stack 256KB */
	170
	171	/* TRATS has 2 banks of DRAM */
	172	#define CONFIG_NR_DRAM_BANKS 2
	173	#define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE /* LDDDR2 DMC 0 */
e687c5a8	174	#define PHYS_SDRAM_1_SIZE (512 << 20) /* 512 MB in CS 0 */
89f95492	175	#define PHYS_SDRAM_2 0x50000000 /* LPDDR2 DMC 1 */
e687c5a8	176	#define PHYS_SDRAM_2_SIZE (512 << 20) /* 512 MB in CS 0 */
89f95492 HK	177
	178	#define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */
	179
	180	#define CONFIG_SYS_MONITOR_BASE 0x00000000
	181	#define CONFIG_SYS_MONITOR_LEN (256 << 10) /* Reserve 2 sectors */
	182
	183	#define CONFIG_ENV_IS_IN_MMC
	184	#define CONFIG_SYS_MMC_ENV_DEV 0
	185	#define CONFIG_ENV_SIZE 4096
	186	#define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */
	187
	188	#define CONFIG_DOS_PARTITION
	189
	190	#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR - GENERATED_GBL_DATA_SIZE)
	191	#define CONFIG_SYS_CACHELINE_SIZE 32
	192
	193	#include <asm/arch/gpio.h>
	194	/*
	195	* I2C Settings
	196	*/
	197	#define CONFIG_SOFT_I2C_GPIO_SCL exynos4_gpio_part1_get_nr(b, 7)
	198	#define CONFIG_SOFT_I2C_GPIO_SDA exynos4_gpio_part1_get_nr(b, 6)
	199
	200	#define CONFIG_SOFT_I2C
	201	#define CONFIG_SOFT_I2C_READ_REPEATED_START
	202	#define CONFIG_SYS_I2C_SPEED 50000
	203	#define CONFIG_I2C_MULTI_BUS
	204	#define CONFIG_SYS_MAX_I2C_BUS 7
	205
	206	#define CONFIG_PMIC
	207	#define CONFIG_PMIC_I2C
04ce68ee	208	#define CONFIG_PMIC_MAX8997
89f95492 HK	209
	210	#define CONFIG_USB_GADGET
	211	#define CONFIG_USB_GADGET_S3C_UDC_OTG
	212	#define CONFIG_USB_GADGET_DUALSPEED
	213
51b1cd6d DL	214	/* LCD */
	215	#define CONFIG_EXYNOS_FB
	216	#define CONFIG_LCD
90464971 DL	217	#define CONFIG_CMD_BMP
90464971 DL	218	#define CONFIG_BMP_32BPP
51b1cd6d DL	219	#define CONFIG_FB_ADDR 0x52504000
	220	#define CONFIG_S6E8AX0
	221	#define CONFIG_EXYNOS_MIPI_DSIM
90464971 DL	222	#define CONFIG_VIDEO_BMP_GZIP
90464971 DL	223	#define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 120 * 4) + (1 << 12))
51b1cd6d	224
89f95492	225	#endif /* __CONFIG_H */