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89f95492 HK |
1 | /* |
2 | * Copyright (C) 2011 Samsung Electronics | |
3 | * Heungjun Kim <riverful.kim@samsung.com> | |
4 | * | |
5 | * Configuation settings for the SAMSUNG TRATS (EXYNOS4210) board. | |
6 | * | |
1a459660 | 7 | * SPDX-License-Identifier: GPL-2.0+ |
89f95492 HK |
8 | */ |
9 | ||
fe601647 PW |
10 | #ifndef __CONFIG_TRATS_H |
11 | #define __CONFIG_TRATS_H | |
89f95492 | 12 | |
4c7bb1d2 | 13 | #include <configs/exynos4-common.h> |
fe601647 | 14 | |
fe601647 | 15 | #define CONFIG_TRATS |
89f95492 | 16 | |
89f95492 | 17 | |
fe601647 | 18 | #define CONFIG_TIZEN /* TIZEN lib */ |
89f95492 | 19 | |
c4e96dbf | 20 | #define CONFIG_SYS_L2CACHE_OFF |
d0460b01 ŁM |
21 | #ifndef CONFIG_SYS_L2CACHE_OFF |
22 | #define CONFIG_SYS_L2_PL310 | |
23 | #define CONFIG_SYS_PL310_BASE 0x10502000 | |
24 | #endif | |
89f95492 | 25 | |
fe601647 PW |
26 | /* TRATS has 4 banks of DRAM */ |
27 | #define CONFIG_NR_DRAM_BANKS 4 | |
89f95492 | 28 | #define CONFIG_SYS_SDRAM_BASE 0x40000000 |
fe601647 | 29 | #define PHYS_SDRAM_1 CONFIG_SYS_SDRAM_BASE |
89f95492 | 30 | #define CONFIG_SYS_TEXT_BASE 0x63300000 |
fe601647 | 31 | #define SDRAM_BANK_SIZE (256 << 20) /* 256 MB */ |
89f95492 | 32 | |
fe601647 PW |
33 | /* memtest works on */ |
34 | #define CONFIG_SYS_MEMTEST_START CONFIG_SYS_SDRAM_BASE | |
35 | #define CONFIG_SYS_MEMTEST_END (CONFIG_SYS_SDRAM_BASE + 0x5000000) | |
36 | #define CONFIG_SYS_LOAD_ADDR (CONFIG_SYS_SDRAM_BASE + 0x4800000) | |
89f95492 | 37 | |
fe601647 | 38 | #define CONFIG_SYS_TEXT_BASE 0x63300000 |
89f95492 | 39 | |
89f95492 | 40 | /* select serial console configuration */ |
fe601647 | 41 | #define CONFIG_SERIAL2 |
89f95492 HK |
42 | #define CONFIG_BAUDRATE 115200 |
43 | ||
fe601647 PW |
44 | /* Console configuration */ |
45 | #define CONFIG_SYS_CONSOLE_INFO_QUIET | |
46 | #define CONFIG_SYS_CONSOLE_IS_IN_ENV | |
47 | ||
48 | /* MACH_TYPE_TRATS macro will be removed once added to mach-types */ | |
49 | #define MACH_TYPE_TRATS 3928 | |
50 | #define CONFIG_MACH_TYPE MACH_TYPE_TRATS | |
51 | ||
89f95492 | 52 | #define CONFIG_BOOTARGS "Please use defined boot" |
0a1387bf | 53 | #define CONFIG_BOOTCOMMAND "run autoboot" |
6afc3f6e | 54 | #define CONFIG_DEFAULT_CONSOLE "console=ttySAC2,115200n8\0" |
fe601647 PW |
55 | |
56 | #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_LOAD_ADDR \ | |
57 | - GENERATED_GBL_DATA_SIZE) | |
58 | ||
59 | #define CONFIG_SYS_MEM_TOP_HIDE (1 << 20) /* ram console */ | |
60 | ||
61 | #define CONFIG_SYS_MONITOR_BASE 0x00000000 | |
89f95492 | 62 | |
89f95492 HK |
63 | #define CONFIG_BOOTBLOCK "10" |
64 | #define CONFIG_ENV_COMMON_BOOT "${console} ${meminfo}" | |
65 | ||
fe601647 PW |
66 | #define CONFIG_ENV_IS_IN_MMC |
67 | #define CONFIG_SYS_MMC_ENV_DEV CONFIG_MMC_DEFAULT_DEV | |
68 | #define CONFIG_ENV_SIZE 4096 | |
69 | #define CONFIG_ENV_OFFSET ((32 - 4) << 10) /* 32KiB - 4KiB */ | |
70 | ||
71 | #define CONFIG_ENV_OVERWRITE | |
72 | ||
73 | #define CONFIG_ENV_VARS_UBOOT_CONFIG | |
74 | #define CONFIG_ENV_VARS_UBOOT_RUNTIME_CONFIG | |
75 | ||
9960d9a8 ŁM |
76 | /* Tizen - partitions definitions */ |
77 | #define PARTS_CSA "csa-mmc" | |
9960d9a8 | 78 | #define PARTS_BOOT "boot" |
18f3e0eb PM |
79 | #define PARTS_QBOOT "qboot" |
80 | #define PARTS_CSC "csc" | |
9960d9a8 ŁM |
81 | #define PARTS_ROOT "platform" |
82 | #define PARTS_DATA "data" | |
9960d9a8 ŁM |
83 | #define PARTS_UMS "ums" |
84 | ||
85 | #define PARTS_DEFAULT \ | |
86 | "uuid_disk=${uuid_gpt_disk};" \ | |
18f3e0eb PM |
87 | "name="PARTS_CSA",start=5MiB,size=8MiB,uuid=${uuid_gpt_"PARTS_CSA"};" \ |
88 | "name="PARTS_BOOT",size=60MiB,uuid=${uuid_gpt_"PARTS_BOOT"};" \ | |
89 | "name="PARTS_QBOOT",size=100MiB,uuid=${uuid_gpt_"PARTS_QBOOT"};" \ | |
9960d9a8 | 90 | "name="PARTS_CSC",size=150MiB,uuid=${uuid_gpt_"PARTS_CSC"};" \ |
18f3e0eb PM |
91 | "name="PARTS_ROOT",size=1536MiB,uuid=${uuid_gpt_"PARTS_ROOT"};" \ |
92 | "name="PARTS_DATA",size=3000MiB,uuid=${uuid_gpt_"PARTS_DATA"};" \ | |
9960d9a8 ŁM |
93 | "name="PARTS_UMS",size=-,uuid=${uuid_gpt_"PARTS_UMS"}\0" \ |
94 | ||
93a1ab57 | 95 | #define CONFIG_DFU_ALT \ |
b7d4259a | 96 | "u-boot raw 0x80 0x400;" \ |
dcb7eb66 ŁM |
97 | "/uImage ext4 0 2;" \ |
98 | "/modem.bin ext4 0 2;" \ | |
99 | "/exynos4210-trats.dtb ext4 0 2;" \ | |
18f3e0eb | 100 | ""PARTS_CSA" part 0 1;" \ |
cdd15bce | 101 | ""PARTS_BOOT" part 0 2;" \ |
18f3e0eb PM |
102 | ""PARTS_QBOOT" part 0 3;" \ |
103 | ""PARTS_CSC" part 0 4;" \ | |
cdd15bce ŁM |
104 | ""PARTS_ROOT" part 0 5;" \ |
105 | ""PARTS_DATA" part 0 6;" \ | |
a0afc6f3 | 106 | ""PARTS_UMS" part 0 7;" \ |
0a1387bf ŁM |
107 | "params.bin raw 0x38 0x8;" \ |
108 | "/Image.itb ext4 0 2\0" | |
93a1ab57 | 109 | |
89f95492 HK |
110 | #define CONFIG_EXTRA_ENV_SETTINGS \ |
111 | "bootk=" \ | |
425e26de PW |
112 | "run loaduimage;" \ |
113 | "if run loaddtb; then " \ | |
114 | "bootm 0x40007FC0 - ${fdtaddr};" \ | |
115 | "fi;" \ | |
116 | "bootm 0x40007FC0;\0" \ | |
89f95492 | 117 | "updatebackup=" \ |
188c42b3 JC |
118 | "mmc dev 0 2; mmc write 0 0x42100000 0 0x200;" \ |
119 | "mmc dev 0 0\0" \ | |
89f95492 HK |
120 | "updatebootb=" \ |
121 | "mmc read 0 0x42100000 0x80 0x200; run updatebackup\0" \ | |
122 | "lpj=lpj=3981312\0" \ | |
123 | "nfsboot=" \ | |
35777e22 | 124 | "setenv bootargs root=/dev/nfs rw " \ |
89f95492 HK |
125 | "nfsroot=${nfsroot},nolock,tcp " \ |
126 | "ip=${ipaddr}:${serverip}:${gatewayip}:" \ | |
127 | "${netmask}:generic:usb0:off " CONFIG_ENV_COMMON_BOOT \ | |
128 | "; run bootk\0" \ | |
129 | "ramfsboot=" \ | |
35777e22 | 130 | "setenv bootargs root=/dev/ram0 rw rootfstype=ext2 " \ |
89f95492 HK |
131 | "${console} ${meminfo} " \ |
132 | "initrd=0x43000000,8M ramdisk=8192\0" \ | |
133 | "mmcboot=" \ | |
35777e22 | 134 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ |
89f95492 | 135 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo}; " \ |
425e26de | 136 | "run bootk\0" \ |
35777e22 | 137 | "bootchart=setenv opts init=/sbin/bootchartd; run bootcmd\0" \ |
89f95492 HK |
138 | "boottrace=setenv opts initcall_debug; run bootcmd\0" \ |
139 | "mmcoops=mmc read 0 0x40000000 0x40 8; md 0x40000000 0x400\0" \ | |
140 | "verify=n\0" \ | |
141 | "rootfstype=ext4\0" \ | |
142 | "console=" CONFIG_DEFAULT_CONSOLE \ | |
143 | "meminfo=crashkernel=32M@0x50000000\0" \ | |
144 | "nfsroot=/nfsroot/arm\0" \ | |
145 | "bootblock=" CONFIG_BOOTBLOCK "\0" \ | |
35777e22 | 146 | "loaduimage=ext4load mmc ${mmcdev}:${mmcbootpart} 0x40007FC0 uImage\0" \ |
4ef400b9 | 147 | "loaddtb=ext4load mmc ${mmcdev}:${mmcbootpart} ${fdtaddr} " \ |
ba223bb2 | 148 | "${fdtfile}\0" \ |
89f95492 HK |
149 | "mmcdev=0\0" \ |
150 | "mmcbootpart=2\0" \ | |
35777e22 | 151 | "mmcrootpart=5\0" \ |
93a1ab57 | 152 | "opts=always_resume=1\0" \ |
9960d9a8 | 153 | "partitions=" PARTS_DEFAULT \ |
35777e22 ŁM |
154 | "dfu_alt_info=" CONFIG_DFU_ALT \ |
155 | "spladdr=0x40000100\0" \ | |
156 | "splsize=0x200\0" \ | |
157 | "splfile=falcon.bin\0" \ | |
158 | "spl_export=" \ | |
159 | "setexpr spl_imgsize ${splsize} + 8 ;" \ | |
dc993a65 | 160 | "setenv spl_imgsize 0x${spl_imgsize};" \ |
35777e22 ŁM |
161 | "setexpr spl_imgaddr ${spladdr} - 8 ;" \ |
162 | "setexpr spl_addr_tmp ${spladdr} - 4 ;" \ | |
163 | "mw.b ${spl_imgaddr} 0x00 ${spl_imgsize};run loaduimage;" \ | |
164 | "setenv bootargs root=/dev/mmcblk${mmcdev}p${mmcrootpart} " \ | |
165 | "${lpj} rootwait ${console} ${meminfo} ${opts} ${lcdinfo};" \ | |
166 | "spl export atags 0x40007FC0;" \ | |
167 | "crc32 ${spladdr} ${splsize} ${spl_imgaddr};" \ | |
168 | "mw.l ${spl_addr_tmp} ${splsize};" \ | |
169 | "ext4write mmc ${mmcdev}:${mmcbootpart}" \ | |
170 | " /${splfile} ${spl_imgaddr} ${spl_imgsize};" \ | |
171 | "setenv spl_imgsize;" \ | |
172 | "setenv spl_imgaddr;" \ | |
ba223bb2 | 173 | "setenv spl_addr_tmp;\0" \ |
0a1387bf | 174 | CONFIG_EXTRA_ENV_ITB \ |
ba223bb2 | 175 | "fdtaddr=40800000\0" \ |
ba223bb2 | 176 | |
35777e22 ŁM |
177 | /* Falcon mode definitions */ |
178 | #define CONFIG_CMD_SPL | |
fe601647 | 179 | #define CONFIG_SYS_SPL_ARGS_ADDR CONFIG_SYS_SDRAM_BASE + 0x100 |
89f95492 | 180 | |
9960d9a8 | 181 | /* GPT */ |
aafd2c5d | 182 | #define CONFIG_RANDOM_UUID |
9960d9a8 | 183 | |
fe601647 PW |
184 | /* I2C */ |
185 | #include <asm/arch/gpio.h> | |
9960d9a8 | 186 | |
89f95492 | 187 | |
ea818dbb | 188 | #define CONFIG_SYS_I2C |
2d8f1e27 PW |
189 | #define CONFIG_SYS_I2C_S3C24X0 |
190 | #define CONFIG_SYS_I2C_S3C24X0_SPEED 100000 | |
191 | #define CONFIG_SYS_I2C_S3C24X0_SLAVE 0xFE | |
192 | #define CONFIG_MAX_I2C_NUM 8 | |
ea818dbb HS |
193 | #define CONFIG_SYS_I2C_SOFT /* I2C bit-banged */ |
194 | #define CONFIG_SYS_I2C_SOFT_SPEED 50000 | |
2d8f1e27 | 195 | #define CONFIG_SYS_I2C_SOFT_SLAVE 0x7F |
89f95492 | 196 | #define CONFIG_SOFT_I2C_READ_REPEATED_START |
fd8dca83 | 197 | #define CONFIG_SYS_I2C_INIT_BOARD |
fd8dca83 | 198 | |
fd8dca83 | 199 | /* I2C FG */ |
9b97b727 AS |
200 | #define CONFIG_SOFT_I2C_GPIO_SCL EXYNOS4_GPIO_Y41 |
201 | #define CONFIG_SOFT_I2C_GPIO_SDA EXYNOS4_GPIO_Y40 | |
89f95492 | 202 | |
fe601647 | 203 | /* POWER */ |
be3b51aa ŁM |
204 | #define CONFIG_POWER |
205 | #define CONFIG_POWER_I2C | |
206 | #define CONFIG_POWER_MAX8997 | |
89f95492 | 207 | |
5a77358c ŁM |
208 | #define CONFIG_POWER_FG |
209 | #define CONFIG_POWER_FG_MAX17042 | |
7dcda99d ŁM |
210 | #define CONFIG_POWER_MUIC |
211 | #define CONFIG_POWER_MUIC_MAX8997 | |
61365ffc ŁM |
212 | #define CONFIG_POWER_BATTERY |
213 | #define CONFIG_POWER_BATTERY_TRATS | |
89f95492 | 214 | |
e0021706 PM |
215 | /* Security subsystem - enable hw_rand() */ |
216 | #define CONFIG_EXYNOS_ACE_SHA | |
217 | #define CONFIG_LIB_HW_RAND | |
218 | ||
679549d1 PM |
219 | /* Common misc for Samsung */ |
220 | #define CONFIG_MISC_COMMON | |
221 | ||
222 | #define CONFIG_MISC_INIT_R | |
223 | ||
00e64ab6 PM |
224 | /* Download menu - Samsung common */ |
225 | #define CONFIG_LCD_MENU | |
226 | #define CONFIG_LCD_MENU_BOARD | |
227 | ||
228 | /* Download menu - definitions for check keys */ | |
229 | #ifndef __ASSEMBLY__ | |
230 | #include <power/max8997_pmic.h> | |
231 | ||
232 | #define KEY_PWR_PMIC_NAME "MAX8997_PMIC" | |
233 | #define KEY_PWR_STATUS_REG MAX8997_REG_STATUS1 | |
234 | #define KEY_PWR_STATUS_MASK (1 << 0) | |
235 | #define KEY_PWR_INTERRUPT_REG MAX8997_REG_INT1 | |
236 | #define KEY_PWR_INTERRUPT_MASK (1 << 0) | |
237 | ||
9b97b727 AS |
238 | #define KEY_VOL_UP_GPIO EXYNOS4_GPIO_X20 |
239 | #define KEY_VOL_DOWN_GPIO EXYNOS4_GPIO_X21 | |
00e64ab6 PM |
240 | #endif /* __ASSEMBLY__ */ |
241 | ||
242 | /* LCD console */ | |
243 | #define LCD_BPP LCD_COLOR16 | |
244 | #define CONFIG_SYS_WHITE_ON_BLACK | |
245 | ||
51b1cd6d DL |
246 | /* LCD */ |
247 | #define CONFIG_EXYNOS_FB | |
248 | #define CONFIG_LCD | |
90464971 | 249 | #define CONFIG_CMD_BMP |
2df21cb3 | 250 | #define CONFIG_BMP_16BPP |
51b1cd6d DL |
251 | #define CONFIG_FB_ADDR 0x52504000 |
252 | #define CONFIG_S6E8AX0 | |
253 | #define CONFIG_EXYNOS_MIPI_DSIM | |
90464971 | 254 | #define CONFIG_VIDEO_BMP_GZIP |
903afe18 | 255 | #define CONFIG_SYS_VIDEO_LOGO_MAX_SIZE ((500 * 160 * 4) + 54) |
51b1cd6d | 256 | |
89f95492 | 257 | #endif /* __CONFIG_H */ |